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5  software/include/base/irq.h
@@ -49,9 +49,4 @@ static inline unsigned int irq_pending(void)
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        return pending;
50 50
 }
51 51
 
52  
-static inline void irq_ack(unsigned int mask)
53  
-{
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-       __asm__ __volatile__("wcsr IP, %0" : : "r" (mask));
55  
-}
56  
-
57 52
 #endif /* __IRQ_H */
4  software/libbase/system.c
@@ -44,7 +44,7 @@ __attribute__((noreturn)) void reboot(void)
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 {
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 	uart_sync();
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 	irq_setmask(0);
47  
-	irq_enable(0);
  47
+	irq_setie(0);
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 	CSR_SYSTEM_ID = 1; /* Writing to CSR_SYSTEM_ID causes a system reset */
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 	while(1);
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 }
@@ -61,7 +61,7 @@ __attribute__((noreturn)) void reconf(void)
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 {
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 	uart_sync();
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 	irq_setmask(0);
64  
-	irq_enable(0);
  64
+	irq_setie(0);
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 	icap_write(0, 0xffff); /* dummy word */
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 	icap_write(0, 0xffff); /* dummy word */
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 	icap_write(0, 0xffff); /* dummy word */
3  software/libbase/uart.c
@@ -62,7 +62,6 @@ void uart_isr(void)
62 62
 	}
63 63
 
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 	CSR_UART_EV_PENDING = stat;
65  
-	irq_ack(IRQ_UART);
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 }
67 66
 
68 67
 /* Do not use in interrupt handlers! */
@@ -108,8 +107,6 @@ void uart_init(void)
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 	tx_consume = 0;
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 	tx_cts = 1;
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111  
-	irq_ack(IRQ_UART);
112  
-
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 	/* ack any events */
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 	CSR_UART_EV_PENDING = CSR_UART_EV_PENDING;
115 112
 
15  verilog/lm32/lm32_interrupt.v
@@ -93,7 +93,7 @@ parameter interrupts = `CFG_INTERRUPTS;         // Number of interrupts
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 input clk_i;                                    // Clock
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 input rst_i;                                    // Reset
95 95
 
96  
-input [interrupts-1:0] interrupt;               // Interrupt pins, active-low
  96
+input [interrupts-1:0] interrupt;               // Interrupt pins
97 97
 
98 98
 input stall_x;                                  // Stall X pipeline stage
99 99
 
@@ -126,8 +126,6 @@ reg    [`LM32_WORD_RNG] csr_read_data;
126 126
 // Internal nets and registers 
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 /////////////////////////////////////////////////////
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129  
-wire [interrupts-1:0] asserted;                 // Which interrupts are currently being asserted
130  
-//pragma attribute asserted preserve_signal true
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 wire [interrupts-1:0] interrupt_n_exception;
132 130
 
133 131
 // Interrupt CSRs
@@ -149,9 +147,6 @@ assign interrupt_n_exception = ip & im;
149 147
 
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 // Determine if any unmasked interrupts have occured
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 assign interrupt_exception = (|interrupt_n_exception) & ie;
152  
-
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-// Determine which interrupts are currently being asserted (active-low) or are already pending
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-assign asserted = ip | interrupt;
155 150
        
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 assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 
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 `ifdef CFG_DEBUG_ENABLED
@@ -231,7 +226,7 @@ begin
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     else
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     begin
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         // Set IP bit when interrupt line is asserted
234  
-        ip <= asserted;
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+        ip <= interrupt;
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 `ifdef CFG_DEBUG_ENABLED
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         if (non_debug_exception == `TRUE)
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         begin
@@ -276,8 +271,6 @@ begin
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                 end
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                 if (csr == `LM32_CSR_IM)
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                     im <= csr_write_data[interrupts-1:0];
279  
-                if (csr == `LM32_CSR_IP)
280  
-                    ip <= asserted & ~csr_write_data[interrupts-1:0];
281 274
             end
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         end
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     end
@@ -300,7 +293,7 @@ begin
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     else
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     begin
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         // Set IP bit when interrupt line is asserted
303  
-        ip <= asserted;
  296
+        ip <= interrupt;
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 `ifdef CFG_DEBUG_ENABLED
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         if (non_debug_exception == `TRUE)
306 299
         begin
@@ -343,8 +336,6 @@ begin
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                     bie <= csr_write_data[2];
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 `endif
345 338
                 end
346  
-                if (csr == `LM32_CSR_IP)
347  
-                    ip <= asserted & ~csr_write_data[interrupts-1:0];
348 339
             end
349 340
         end
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     end

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