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  • 2 commits
  • 3 files changed
  • 0 commit comments
  • 1 contributor
Commits on May 20, 2012
@sbourdeauducq sbourdeauducq Connect Ethernet IRQ 8ad251c
Commits on May 21, 2012
@sbourdeauducq sbourdeauducq Add timer 9424551
Showing with 38 additions and 3 deletions.
  1. +2 −1  common/csrbase.h
  2. +30 −0 milkymist/timer/__init__.py
  3. +6 −2 top.py
View
3  common/csrbase.h
@@ -4,6 +4,7 @@
#define UART_BASE 0xe0000000
#define DFII_BASE 0xe0000800
#define ID_BASE 0xe0001000
-#define MINIMAC_BASE 0xe0001800
+#define TIMER0_BASE 0xe0001800
+#define MINIMAC_BASE 0xe0002000
#endif /* __CSRBASE_H */
View
30 milkymist/timer/__init__.py
@@ -0,0 +1,30 @@
+from migen.fhdl.structure import *
+from migen.bank.description import *
+from migen.bank.eventmanager import *
+from migen.bank import csrgen
+
+class Timer:
+ def __init__(self, address, width=32):
+ self._en = RegisterField("en")
+ self._value = RegisterField("value", width, access_dev=READ_WRITE)
+ self._reload = RegisterField("reload", width)
+ regs = [self._en, self._value, self._reload]
+
+ self.event = EventSourceLevel()
+ self.events = EventManager(self.event)
+
+ self.bank = csrgen.Bank(regs + self.events.get_registers(), address=address)
+
+ def get_fragment(self):
+ comb = [
+ If(self._value.field.r == 0,
+ self._value.field.w.eq(self._reload.field.r)
+ ).Else(
+ self._value.field.w.eq(self._value.field.r - 1)
+ ),
+ self._value.field.we.eq(self._en.field.r),
+ self.event.trigger.eq(self._value.field.r != 0)
+ ]
+ return Fragment(comb) \
+ + self.events.get_fragment() \
+ + self.bank.get_fragment()
View
8 top.py
@@ -5,7 +5,7 @@
from migen.fhdl import verilog, autofragment
from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
-from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, identifier, minimac3
+from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, identifier, timer, minimac3
from cmacros import get_macros
from constraints import Constraints
@@ -117,10 +117,12 @@ def get():
#
uart0 = uart.UART(csr_offset("UART"), clk_freq, baud=115200)
identifier0 = identifier.Identifier(csr_offset("ID"), 0x4D31, version)
+ timer0 = timer.Timer(csr_offset("TIMER0"))
csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
uart0.bank.interface,
dfii0.bank.interface,
identifier0.bank.interface,
+ timer0.bank.interface,
minimac0.bank.interface
])
@@ -128,7 +130,9 @@ def get():
# Interrupts
#
interrupts = Fragment([
- cpu0.interrupt[0].eq(uart0.events.irq)
+ cpu0.interrupt[0].eq(uart0.events.irq),
+ cpu0.interrupt[1].eq(timer0.events.irq),
+ cpu0.interrupt[2].eq(minimac0.events.irq)
])
#

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