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3  common/csrbase.h
@@ -4,6 +4,7 @@
4 4
 #define UART_BASE	0xe0000000
5 5
 #define DFII_BASE	0xe0000800
6 6
 #define ID_BASE		0xe0001000
7  
-#define MINIMAC_BASE	0xe0001800
  7
+#define TIMER0_BASE	0xe0001800
  8
+#define MINIMAC_BASE	0xe0002000
8 9
 
9 10
 #endif /* __CSRBASE_H */
30  milkymist/timer/__init__.py
... ...
@@ -0,0 +1,30 @@
  1
+from migen.fhdl.structure import *
  2
+from migen.bank.description import *
  3
+from migen.bank.eventmanager import *
  4
+from migen.bank import csrgen
  5
+
  6
+class Timer:
  7
+	def __init__(self, address, width=32):
  8
+		self._en = RegisterField("en")
  9
+		self._value = RegisterField("value", width, access_dev=READ_WRITE)
  10
+		self._reload = RegisterField("reload", width)
  11
+		regs = [self._en, self._value, self._reload]
  12
+		
  13
+		self.event = EventSourceLevel()
  14
+		self.events = EventManager(self.event)
  15
+		
  16
+		self.bank = csrgen.Bank(regs + self.events.get_registers(), address=address)
  17
+
  18
+	def get_fragment(self):
  19
+		comb = [
  20
+			If(self._value.field.r == 0,
  21
+				self._value.field.w.eq(self._reload.field.r)
  22
+			).Else(
  23
+				self._value.field.w.eq(self._value.field.r - 1)
  24
+			),
  25
+			self._value.field.we.eq(self._en.field.r),
  26
+			self.event.trigger.eq(self._value.field.r != 0)
  27
+		]
  28
+		return Fragment(comb) \
  29
+			+ self.events.get_fragment() \
  30
+			+ self.bank.get_fragment()
8  top.py
@@ -5,7 +5,7 @@
5 5
 from migen.fhdl import verilog, autofragment
6 6
 from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
7 7
 
8  
-from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, identifier, minimac3
  8
+from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, identifier, timer, minimac3
9 9
 from cmacros import get_macros
10 10
 from constraints import Constraints
11 11
 
@@ -117,10 +117,12 @@ def get():
117 117
 	#
118 118
 	uart0 = uart.UART(csr_offset("UART"), clk_freq, baud=115200)
119 119
 	identifier0 = identifier.Identifier(csr_offset("ID"), 0x4D31, version)
  120
+	timer0 = timer.Timer(csr_offset("TIMER0"))
120 121
 	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
121 122
 		uart0.bank.interface,
122 123
 		dfii0.bank.interface,
123 124
 		identifier0.bank.interface,
  125
+		timer0.bank.interface,
124 126
 		minimac0.bank.interface
125 127
 	])
126 128
 	
@@ -128,7 +130,9 @@ def get():
128 130
 	# Interrupts
129 131
 	#
130 132
 	interrupts = Fragment([
131  
-		cpu0.interrupt[0].eq(uart0.events.irq)
  133
+		cpu0.interrupt[0].eq(uart0.events.irq),
  134
+		cpu0.interrupt[1].eq(timer0.events.irq),
  135
+		cpu0.interrupt[2].eq(minimac0.events.irq)
132 136
 	])
133 137
 	
134 138
 	#

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