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5  build.py
@@ -20,6 +20,11 @@ def main():
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 PIN "m1crg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
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+NET "vga_clk" TNM_NET = "GRPvga_clk";
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+NET "sys_clk" TNM_NET = "GRPsys_clk";
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+TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
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+TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
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+
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 NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk";
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 NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk";
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 TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%;
4  milkymist/dvisampler/clocking.py
@@ -13,8 +13,8 @@ def __init__(self, pads):
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 		self.serdesstrobe = Signal()
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 		self.clock_domains._cd_pix = ClockDomain()
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 		self.clock_domains._cd_pix5x = ClockDomain()
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-		self.clock_domains._cd_pix10x = ClockDomain()
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-		self.clock_domains._cd_pix20x = ClockDomain()
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+		self.clock_domains._cd_pix10x = ClockDomain(reset_less=True)
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+		self.clock_domains._cd_pix20x = ClockDomain(reset_less=True)
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 		###
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2  milkymist/m1crg/__init__.py
@@ -13,7 +13,7 @@ def __init__(self, pads, outfreq1x):
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 		self.clock_domains.cd_sys4x_rd = ClockDomain()
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 		self.clock_domains.cd_eth_rx = ClockDomain()
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 		self.clock_domains.cd_eth_tx = ClockDomain()
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-		self.clock_domains.cd_vga = ClockDomain()
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+		self.clock_domains.cd_vga = ClockDomain(reset_less=True)
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 		self.clk4x_wr_strb = Signal()
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 		self.clk4x_rd_strb = Signal()

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