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230  milkymist/cif.py
@@ -67,30 +67,30 @@ def get_csr_header(csr_base, bank_array, interrupt_map):
67 67
 	return r
68 68
 
69 69
 def get_sdram_phy_header(sdram_phy):
70  
-		if sdram_phy.phy_settings.type not in ["SDR", "DDR", "LPDDR", "DDR2"]:
71  
-			raise NotImplementedError("The SDRAM PHY header generator only supports SDR, DDR, LPDDR and DDR2")
  70
+	if sdram_phy.phy_settings.memtype not in ["SDR", "DDR", "LPDDR", "DDR2"]:
  71
+		raise NotImplementedError("The SDRAM PHY header generator only supports SDR, DDR, LPDDR and DDR2")
72 72
 
73  
-		r = "#ifndef __HW_SDRAM_PHY_H\n#define __HW_SDRAM_PHY_H\n"
74  
-		r += "#include <hw/common.h>\n#include <hw/csr.h>\n#include <hw/flags.h>\n\n"
  73
+	r = "#ifndef __HW_SDRAM_PHY_H\n#define __HW_SDRAM_PHY_H\n"
  74
+	r += "#include <hw/common.h>\n#include <hw/csr.h>\n#include <hw/flags.h>\n\n"
75 75
 
76  
-		r += "static void cdelay(int i);\n"
  76
+	r += "static void cdelay(int i);\n"
77 77
 
78  
-		#
79  
-		# commands_px functions
80  
-		# 
81  
-		for n in range(sdram_phy.phy_settings.nphases):
82  
-			r += """
  78
+	#
  79
+	# commands_px functions
  80
+	# 
  81
+	for n in range(sdram_phy.phy_settings.nphases):
  82
+		r += """
83 83
 static void command_p{n}(int cmd)
84 84
 {{
85 85
 	dfii_pi{n}_command_write(cmd);
86 86
 	dfii_pi{n}_command_issue_write(1);
87 87
 }}""".format(n=str(n))
88  
-		r += "\n\n"
  88
+	r += "\n\n"
89 89
 
90  
-		#
91  
-		# rd/wr access macros
92  
-		#
93  
-		r += """
  90
+	#
  91
+	# rd/wr access macros
  92
+	#
  93
+	r += """
94 94
 #define dfii_pird_address_write(X) dfii_pi{rdphase}_address_write(X)
95 95
 #define dfii_piwr_address_write(X) dfii_pi{wrphase}_address_write(X)
96 96
 
@@ -100,105 +100,105 @@ def get_sdram_phy_header(sdram_phy):
100 100
 #define command_prd(X) command_p{rdphase}(X)
101 101
 #define command_pwr(X) command_p{wrphase}(X)
102 102
 """.format(rdphase=str(sdram_phy.phy_settings.rdphase), wrphase=str(sdram_phy.phy_settings.wrphase)) 
103  
-		r +="\n"
104  
-		
105  
-		#
106  
-		# init sequence
107  
-		# 
108  
-		cmds = {
109  
-			"PRECHARGE_ALL" : "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
110  
-			"MODE_REGISTER" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
111  
-			"AUTO_REFRESH"  : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS",
112  
-			"CKE"           : "DFII_CONTROL_CKE"
113  
-		}
114  
-
115  
-		def gen_cmd(comment, a, ba, cmd, delay):	
116  
-			r = "\t/* {0} */\n".format(comment)
117  
-			r += "\tdfii_pi0_address_write({0:#x});\n".format(a)
118  
-			r += "\tdfii_pi0_baddress_write({0:d});\n".format(ba)
119  
-			if "CKE" in cmd:
120  
-				r += "\tdfii_control_write({0});\n".format(cmd)
121  
-			else:
122  
-				r += "\tcommand_p0({0});\n".format(cmd)
123  
-			r += "\tcdelay({0:d});\n".format(delay)
124  
-			r += "\n"
125  
-			return r
126  
-
127  
-
128  
-		r += "static void init_sequence(void)\n{\n"
129  
-
130  
-		cl = sdram_phy.phy_settings.cl
131  
-		
132  
-		if sdram_phy.phy_settings.type == "SDR":
133  
-			bl = 1*sdram_phy.phy_settings.nphases
134  
-			mr  = log2_int(bl) + (cl << 4)
135  
-			reset_dll = 1 << 8
136  
-
137  
-			init_sequence = [
138  
-				("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
139  
-				("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
140  
-				("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
141  
-				("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
142  
-				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
143  
-				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
144  
-				("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
145  
-			]
146  
-
147  
-		elif sdram_phy.phy_settings.type == "DDR":
148  
-			bl = 2*sdram_phy.phy_settings.nphases
149  
-			mr  = log2_int(bl) + (cl << 4)
150  
-			emr = 0
151  
-			reset_dll = 1 << 8
152  
- 
153  
-			init_sequence = [
154  
-				("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
155  
-				("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
156  
-				("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
157  
-				("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
158  
-				("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
159  
-				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
160  
-				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
161  
-				("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
162  
-			]
163  
-
164  
-		elif sdram_phy.phy_settings.type == "LPDDR":
165  
-			bl = 2*sdram_phy.phy_settings.nphases
166  
-			mr  = log2_int(bl) + (cl << 4)
167  
-			emr = 0
168  
-			reset_dll = 1 << 8
169  
-
170  
-			init_sequence = [
171  
-				("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
172  
-				("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
173  
-				("Load Extended Mode Register", emr, 2, cmds["MODE_REGISTER"], 0),
174  
-				("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
175  
-				("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
176  
-				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
177  
-				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
178  
-				("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
179  
-			]
180  
-
181  
-		elif sdram_phy.phy_settings.type == "DDR2":
182  
-			bl = 2*sdram_phy.phy_settings.nphases
183  
-			mr  = log2_int(bl) + (cl << 4)
184  
-			emr = 0
185  
-			reset_dll = 1 << 8
186  
-
187  
-			init_sequence = [
188  
-				("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
189  
-				("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
190  
-				("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
191  
-				("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
192  
-				("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
193  
-				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
194  
-				("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
195  
-				("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
196  
-			]
197  
-
198  
-		for comment, a, ba, cmd, delay in init_sequence:
199  
-			r += gen_cmd(comment, a, ba, cmd, delay)
  103
+	r +="\n"
  104
+	
  105
+	#
  106
+	# init sequence
  107
+	# 
  108
+	cmds = {
  109
+		"PRECHARGE_ALL" : "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
  110
+		"MODE_REGISTER" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
  111
+		"AUTO_REFRESH"  : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS",
  112
+		"CKE"           : "DFII_CONTROL_CKE"
  113
+	}
  114
+
  115
+	def gen_cmd(comment, a, ba, cmd, delay):	
  116
+		r = "\t/* {0} */\n".format(comment)
  117
+		r += "\tdfii_pi0_address_write({0:#x});\n".format(a)
  118
+		r += "\tdfii_pi0_baddress_write({0:d});\n".format(ba)
  119
+		if "CKE" in cmd:
  120
+			r += "\tdfii_control_write({0});\n".format(cmd)
  121
+		else:
  122
+			r += "\tcommand_p0({0});\n".format(cmd)
  123
+		r += "\tcdelay({0:d});\n".format(delay)
  124
+		r += "\n"
  125
+		return r
200 126
 
201  
-		r += "}\n"
202  
-		r += "#endif\n"
203 127
 
204  
-		return r
  128
+	r += "static void init_sequence(void)\n{\n"
  129
+
  130
+	cl = sdram_phy.phy_settings.cl
  131
+	
  132
+	if sdram_phy.phy_settings.memtype == "SDR":
  133
+		bl = 1*sdram_phy.phy_settings.nphases
  134
+		mr  = log2_int(bl) + (cl << 4)
  135
+		reset_dll = 1 << 8
  136
+
  137
+		init_sequence = [
  138
+			("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
  139
+			("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
  140
+			("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
  141
+			("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
  142
+			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
  143
+			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
  144
+			("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
  145
+		]
  146
+
  147
+	elif sdram_phy.phy_settings.memtype == "DDR":
  148
+		bl = 2*sdram_phy.phy_settings.nphases
  149
+		mr  = log2_int(bl) + (cl << 4)
  150
+		emr = 0
  151
+		reset_dll = 1 << 8
  152
+
  153
+		init_sequence = [
  154
+			("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
  155
+			("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
  156
+			("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
  157
+			("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
  158
+			("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
  159
+			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
  160
+			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
  161
+			("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
  162
+		]
  163
+
  164
+	elif sdram_phy.phy_settings.memtype == "LPDDR":
  165
+		bl = 2*sdram_phy.phy_settings.nphases
  166
+		mr  = log2_int(bl) + (cl << 4)
  167
+		emr = 0
  168
+		reset_dll = 1 << 8
  169
+
  170
+		init_sequence = [
  171
+			("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
  172
+			("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
  173
+			("Load Extended Mode Register", emr, 2, cmds["MODE_REGISTER"], 0),
  174
+			("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
  175
+			("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
  176
+			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
  177
+			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
  178
+			("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
  179
+		]
  180
+
  181
+	elif sdram_phy.phy_settings.memtype == "DDR2":
  182
+		bl = 2*sdram_phy.phy_settings.nphases
  183
+		mr  = log2_int(bl) + (cl << 4)
  184
+		emr = 0
  185
+		reset_dll = 1 << 8
  186
+
  187
+		init_sequence = [
  188
+			("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
  189
+			("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
  190
+			("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
  191
+			("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
  192
+			("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
  193
+			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
  194
+			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
  195
+			("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
  196
+		]
  197
+
  198
+	for comment, a, ba, cmd, delay in init_sequence:
  199
+		r += gen_cmd(comment, a, ba, cmd, delay)
  200
+
  201
+	r += "}\n"
  202
+	r += "#endif\n"
  203
+
  204
+	return r
7  milkymist/lasmicon/__init__.py
@@ -7,14 +7,13 @@
7 7
 from milkymist.lasmicon.bankmachine import *
8 8
 from milkymist.lasmicon.multiplexer import *
9 9
 
10  
-PhySettings = namedtuple("PhySettings", "type dfi_d nphases rdphase wrphase cl")
  10
+PhySettings = namedtuple("PhySettings", "memtype dfi_d nphases rdphase wrphase cl read_latency write_latency")
11 11
 
12 12
 class GeomSettings(namedtuple("_GeomSettings", "bank_a row_a col_a")):
13 13
 	def __init__(self, *args, **kwargs):
14 14
 		self.mux_a = max(self.row_a, self.col_a)
15 15
 
16 16
 TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC" \
17  
-	" read_latency write_latency" \
18 17
 	" req_queue_size read_time write_time")
19 18
 
20 19
 class LASMIcon(Module):
@@ -31,8 +30,8 @@ def __init__(self, phy_settings, geom_settings, timing_settings):
31 30
 			dw=phy_settings.dfi_d*phy_settings.nphases,
32 31
 			nbanks=2**geom_settings.bank_a,
33 32
 			req_queue_size=timing_settings.req_queue_size,
34  
-			read_latency=timing_settings.read_latency+1,
35  
-			write_latency=timing_settings.write_latency+1)
  33
+			read_latency=phy_settings.read_latency+1,
  34
+			write_latency=phy_settings.write_latency+1)
36 35
 		self.nrowbits = geom_settings.col_a - address_align
37 36
 	
38 37
 		###
2  milkymist/lasmicon/multiplexer.py
@@ -178,7 +178,7 @@ def anti_starvation(timeout):
178 178
 			steerer.sel[0].eq(STEER_REFRESH),
179 179
 			If(~refresher.req, NextState("READ"))
180 180
 		)
181  
-		fsm.delayed_enter("RTW", "WRITE", timing_settings.read_latency-1)
  181
+		fsm.delayed_enter("RTW", "WRITE", phy_settings.read_latency-1) # FIXME: reduce this, actual limit is around (cl+1)/nphases
182 182
 		fsm.delayed_enter("WTR", "READ", timing_settings.tWTR-1)
183 183
 		# FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
184 184
 		fsm.finalize()
54  milkymist/s6ddrphy/__init__.py
... ...
@@ -1,4 +1,3 @@
1  
-#
2 1
 # 1:2 frequency-ratio DDR / LPDDR / DDR2 PHY for 
3 2
 # Spartan-6
4 3
 # 
@@ -8,31 +7,46 @@
8 7
 #
9 8
 # Assert dfi_rddata_en in the same cycle as the read
10 9
 # command. The data will come back on dfi_rddata
11  
-# CL + 2 cycles later, along with the assertion 
  10
+# 5 cycles later, along with the assertion 
12 11
 # of dfi_rddata_valid.
13 12
 #
14  
-# This PHY supports configurable CAS Latency.
15  
-# Read commands must be sent on phase RDPHASE.
16  
-# Write commands must be sent on phase WRPHASE.
17  
-#/
  13
+# This PHY only supports CAS Latency 3.
  14
+# Read commands must be sent on phase 0.
  15
+# Write commands must be sent on phase 1.
  16
+#
18 17
 
19 18
 # Todo:
20 19
 #	- use CSR for bitslip?
  20
+#	- add configurable CAS Latency
  21
+#	- automatically determines wrphase / rdphase / latencies
21 22
 
22 23
 from migen.fhdl.std import *
23 24
 from migen.bus.dfi import *
24 25
 from migen.genlib.record import *
25 26
 
  27
+from milkymist import lasmicon
  28
+
26 29
 class S6DDRPHY(Module):
27  
-	def __init__(self, pads, phy_settings, bitslip):
28  
-		if phy_settings.type not in ["DDR", "LPDDR", "DDR2"]:
  30
+	def __init__(self, pads, memtype, nphases, cl, bitslip):
  31
+		if memtype not in ["DDR", "LPDDR", "DDR2"]:
29 32
 			raise NotImplementedError("S6DDRPHY only supports DDR, LPDDR and DDR2")
  33
+		if cl != 3:
  34
+			raise NotImplementedError("S6DDRPHY only supports CAS LATENCY 3")
30 35
 
31 36
 		a = flen(pads.a)
32 37
 		ba = flen(pads.ba)
33 38
 		d = flen(pads.dq)
34  
-		nphases = phy_settings.nphases
35  
-		self.phy_settings = phy_settings
  39
+
  40
+		self.phy_settings = lasmicon.PhySettings(
  41
+			memtype=memtype,
  42
+			dfi_d=2*d,
  43
+			nphases=nphases,
  44
+			rdphase=0,
  45
+			wrphase=1,
  46
+			cl=cl,
  47
+			read_latency=5,
  48
+			write_latency=0
  49
+		)
36 50
 
37 51
 		self.dfi = Interface(a, ba, nphases*d, nphases)
38 52
 		self.clk4x_wr_strb = Signal()
@@ -57,7 +71,7 @@ def __init__(self, pads, phy_settings, bitslip):
57 71
 		#
58 72
 
59 73
 		# select active phase
60  
-		#             sys_clk   ____----____----
  74
+		#             sys_clk   ----____----____
61 75
 		#  phase_sel(nphases=1) 0       0
62 76
 		#  phase_sel(nphases=2) 0   1   0   1
63 77
 		#  phase_sel(nphases=4) 0 1 2 3 0 1 2 3
@@ -102,7 +116,7 @@ def __init__(self, pads, phy_settings, bitslip):
102 116
 		bitslip_inc = Signal()
103 117
 
104 118
 		sd_sys += [
105  
-			If(bitslip_cnt==bitslip, 
  119
+			If(bitslip_cnt == bitslip, 
106 120
 				bitslip_inc.eq(0)
107 121
 			).Else(
108 122
 				bitslip_cnt.eq(bitslip_cnt+1),
@@ -146,7 +160,7 @@ def __init__(self, pads, phy_settings, bitslip):
146 160
 				Instance.Input("S", 0),
147 161
 
148 162
 				Instance.Output("Q", dqs_o[i])
149  
-				)
  163
+			)
150 164
 
151 165
 			# DQS tristate cmd
152 166
 			self.specials += Instance("ODDR2",
@@ -164,7 +178,7 @@ def __init__(self, pads, phy_settings, bitslip):
164 178
 				Instance.Input("S", 0),
165 179
 
166 180
 				Instance.Output("Q", dqs_t[i])
167  
-				)
  181
+			)
168 182
 
169 183
 			# DQS tristate buffer
170 184
 			self.specials += Instance("OBUFT",
@@ -172,7 +186,7 @@ def __init__(self, pads, phy_settings, bitslip):
172 186
 				Instance.Input("T", dqs_t[i]),
173 187
 
174 188
 				Instance.Output("O", pads.dqs[i])
175  
-				)
  189
+			)
176 190
 
177 191
 		sd_sdram_half += postamble.eq(drive_dqs)
178 192
 
@@ -323,23 +337,23 @@ def __init__(self, pads, phy_settings, bitslip):
323 337
 				Instance.Output("SHIFTOUT4"),
324 338
 			)
325 339
 
326  
-
327 340
 		# 
328 341
 		# DQ/DQS/DM control
329 342
 		#
330  
-		self.comb += drive_dq.eq(d_dfi[phy_settings.wrphase].wrdata_en)
  343
+		self.comb += drive_dq.eq(d_dfi[self.phy_settings.wrphase].wrdata_en)
331 344
 		sd_sys += d_drive_dq.eq(drive_dq)
332 345
 
333 346
 		d_dfi_wrdata_en = Signal()
334  
-		sd_sys += d_dfi_wrdata_en.eq(d_dfi[phy_settings.wrphase].wrdata_en)
  347
+		sd_sys += d_dfi_wrdata_en.eq(d_dfi[self.phy_settings.wrphase].wrdata_en)
335 348
 		
336 349
 		r_dfi_wrdata_en = Signal(2)
337 350
 		sd_sdram_half += r_dfi_wrdata_en.eq(Cat(d_dfi_wrdata_en, r_dfi_wrdata_en[0])) 
338 351
 
339 352
 		self.comb += drive_dqs.eq(r_dfi_wrdata_en[1])
340 353
 
341  
-		rddata_sr = Signal(phy_settings.cl+2)
342  
-		sd_sys += rddata_sr.eq(Cat(rddata_sr[1:phy_settings.cl+2], d_dfi[phy_settings.rdphase].rddata_en))
  354
+		rddata_sr = Signal(self.phy_settings.read_latency)
  355
+		sd_sys += rddata_sr.eq(Cat(rddata_sr[1:self.phy_settings.read_latency],
  356
+			d_dfi[self.phy_settings.rdphase].rddata_en))
343 357
 		
344 358
 		for n, phase in enumerate(self.dfi.phases):
345 359
 			self.comb += [
32  top.py
@@ -25,14 +25,6 @@ def ns(t, margin=True):
25 25
 		t += clk_period_ns/2
26 26
 	return ceil(t/clk_period_ns)
27 27
 
28  
-sdram_phy = lasmicon.PhySettings(
29  
-	type="DDR",
30  
-	dfi_d=64, 
31  
-	nphases=2,
32  
-	rdphase=0,
33  
-	wrphase=1,
34  
-	cl=3
35  
-)
36 28
 sdram_geom = lasmicon.GeomSettings(
37 29
 	bank_a=2,
38 30
 	row_a=13,
@@ -45,9 +37,6 @@ def ns(t, margin=True):
45 37
 	tWTR=2,
46 38
 	tREFI=ns(7800, False),
47 39
 	tRFC=ns(70),
48  
-	
49  
-	read_latency=5,
50  
-	write_latency=0,
51 40
 
52 41
 	req_queue_size=8,
53 42
 	read_time=32,
@@ -104,9 +93,19 @@ class SoC(Module):
104 93
 
105 94
 	def __init__(self, platform, platform_name, with_memtest):
106 95
 		#
  96
+		# DFI
  97
+		#
  98
+		self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR", nphases=2, cl=3, bitslip=0)
  99
+		self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a,
  100
+			self.ddrphy.phy_settings.dfi_d, self.ddrphy.phy_settings.nphases)
  101
+		self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, self.ddrphy.dfi)
  102
+
  103
+		#
107 104
 		# LASMI
108 105
 		#
109  
-		self.submodules.lasmicon = lasmicon.LASMIcon(sdram_phy, sdram_geom, sdram_timing)
  106
+		self.submodules.lasmicon = lasmicon.LASMIcon(self.ddrphy.phy_settings, sdram_geom, sdram_timing)
  107
+		self.submodules.dficon1 = dfi.Interconnect(self.lasmicon.dfi, self.dfii.slave)
  108
+
110 109
 		n_lasmims = 7 if with_memtest else 5
111 110
 		self.submodules.lasmixbar = lasmibus.Crossbar([self.lasmicon.lasmic], n_lasmims, self.lasmicon.nrowbits)
112 111
 		lasmims = list(self.lasmixbar.masters)
@@ -114,15 +113,6 @@ def __init__(self, platform, platform_name, with_memtest):
114 113
 		if with_memtest:
115 114
 			lasmim_mtw, lasmim_mtr = lasmims.pop(), lasmims.pop()
116 115
 		assert(not lasmims)
117  
-		
118  
-		#
119  
-		# DFI
120  
-		#
121  
-		self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), sdram_phy, 0)
122  
-		self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d,
123  
-			sdram_phy.nphases)
124  
-		self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, self.ddrphy.dfi)
125  
-		self.submodules.dficon1 = dfi.Interconnect(self.lasmicon.dfi, self.dfii.slave)
126 116
 
127 117
 		#
128 118
 		# WISHBONE

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