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2  verilog/lm32/submodule
... ...
@@ -1 +1 @@
1  
-Subproject commit 57d998d38fa1cd77c1c5eed72f079aaa2b0b0721
  1
+Subproject commit cf2281b28e42c99ea9ed17fb2195608df24c1f89
36  verilog/m1crg/m1crg.v
@@ -101,6 +101,7 @@ wire pllout1;
101 101
 wire pllout2;
102 102
 wire pllout3;
103 103
 wire pllout4;
  104
+wire pllout5;
104 105
 
105 106
 PLL_ADV #(
106 107
 	.BANDWIDTH("OPTIMIZED"),
@@ -108,24 +109,31 @@ PLL_ADV #(
108 109
 	.CLKFBOUT_PHASE(0.0),
109 110
 	.CLKIN1_PERIOD(in_period),
110 111
 	.CLKIN2_PERIOD(in_period),
  112
+
111 113
 	.CLKOUT0_DIVIDE(f_div),
112 114
 	.CLKOUT0_DUTY_CYCLE(0.5),
113  
-	.CLKOUT0_PHASE(0),
  115
+	.CLKOUT0_PHASE(0.0),
  116
+	
114 117
 	.CLKOUT1_DIVIDE(f_div),
115 118
 	.CLKOUT1_DUTY_CYCLE(0.5),
116  
-	.CLKOUT1_PHASE(0),
  119
+	.CLKOUT1_PHASE(0.0),
  120
+	
117 121
 	.CLKOUT2_DIVIDE(2*f_div),
118 122
 	.CLKOUT2_DUTY_CYCLE(0.5),
119 123
 	.CLKOUT2_PHASE(270.0),
  124
+	
120 125
 	.CLKOUT3_DIVIDE(4*f_div),
121 126
 	.CLKOUT3_DUTY_CYCLE(0.5),
122 127
 	.CLKOUT3_PHASE(0.0),
  128
+	
123 129
 	.CLKOUT4_DIVIDE(4*f_mult),
124 130
 	.CLKOUT4_DUTY_CYCLE(0.5),
125  
-	.CLKOUT4_PHASE(0),
126  
-	.CLKOUT5_DIVIDE(7),
  131
+	.CLKOUT4_PHASE(0.0),
  132
+	
  133
+	.CLKOUT5_DIVIDE(2*f_div),
127 134
 	.CLKOUT5_DUTY_CYCLE(0.5),
128  
-	.CLKOUT5_PHASE(0.0),
  135
+	.CLKOUT5_PHASE(250.0),
  136
+	
129 137
 	.COMPENSATION("INTERNAL"),
130 138
 	.DIVCLK_DIVIDE(1),
131 139
 	.REF_JITTER(0.100),
@@ -136,10 +144,10 @@ PLL_ADV #(
136 144
 	.CLKFBOUT(buf_pll_fb_out),
137 145
 	.CLKOUT0(pllout0), /* < x4 clock for writes */
138 146
 	.CLKOUT1(pllout1), /* < x4 clock for reads */
139  
-	.CLKOUT2(pllout2), /* < x2 90 clock to generate memory clock, clock DQS and memory address and control signals. */
  147
+	.CLKOUT2(pllout2), /* < x2 270 clock for DQS, memory address and control signals */
140 148
 	.CLKOUT3(pllout3), /* < x1 clock for system and memory controller */
141 149
 	.CLKOUT4(pllout4), /* < buffered clk50 */
142  
-	.CLKOUT5(),
  150
+	.CLKOUT5(pllout5), /* < x2 clock to off-chip DDR */
143 151
 	.CLKOUTDCM0(),
144 152
 	.CLKOUTDCM1(),
145 153
 	.CLKOUTDCM2(),
@@ -194,6 +202,12 @@ BUFG bufg_x1(
194 202
 	.O(sys_clk)
195 203
 );
196 204
 
  205
+wire clk2x_off;
  206
+BUFG bufg_x2_offclk(
  207
+	.I(pllout5),
  208
+	.O(clk2x_off)
  209
+);
  210
+
197 211
 
198 212
 /* 
199 213
  * SDRAM clock
@@ -205,8 +219,8 @@ ODDR2 #(
205 219
 	.SRTYPE("SYNC")
206 220
 ) sd_clk_forward_p (
207 221
 	.Q(ddr_clk_pad_p),
208  
-	.C0(clk2x_270),
209  
-	.C1(~clk2x_270),
  222
+	.C0(clk2x_off),
  223
+	.C1(~clk2x_off),
210 224
 	.CE(1'b1),
211 225
 	.D0(1'b1),
212 226
 	.D1(1'b0),
@@ -219,8 +233,8 @@ ODDR2 #(
219 233
 	.SRTYPE("SYNC")
220 234
 ) sd_clk_forward_n (
221 235
 	.Q(ddr_clk_pad_n),
222  
-	.C0(clk2x_270),
223  
-	.C1(~clk2x_270),
  236
+	.C0(clk2x_off),
  237
+	.C1(~clk2x_off),
224 238
 	.CE(1'b1),
225 239
 	.D0(1'b0),
226 240
 	.D1(1'b1),

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