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  • 2 commits
  • 8 files changed
  • 0 commit comments
  • 1 contributor
Commits on Aug 04, 2012
@sbourdeauducq sbourdeauducq Add ASMIprobe core 855eec7
@sbourdeauducq sbourdeauducq bios: asmiprobe command
Because with reordering architectures come order-dependent intermittent bugs.
274a002
View
1  common/csrbase.h
@@ -7,5 +7,6 @@
#define TIMER0_BASE 0xe0001800
#define MINIMAC_BASE 0xe0002000
#define FB_BASE 0xe0002800
+#define ASMIPROBE_BASE 0xe0003000
#endif /* __CSRBASE_H */
View
36 milkymist/asmiprobe/__init__.py
@@ -0,0 +1,36 @@
+from migen.fhdl.structure import *
+from migen.bank.description import *
+from migen.bank import csrgen
+
+class ASMIprobe:
+ def __init__(self, address, hub, trace_depth=16):
+ self.hub = hub
+ self.trace_depth = trace_depth
+
+ slot_count = len(self.hub.get_slots())
+ assert(self.trace_depth < 256)
+ assert(slot_count < 256)
+
+ self._slot_count = RegisterField("slot_count", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
+ self._trace_depth = RegisterField("trace_depth", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
+ self._slot_status = [RegisterField("slot_status", 2, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
+ for i in range(slot_count)]
+ self._trace = [RegisterField("trace", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
+ for i in range(self.trace_depth)]
+
+ self.bank = csrgen.Bank([self._slot_count, self._trace_depth]
+ + self._slot_status + self._trace, address=address)
+
+ def get_fragment(self):
+ slots = self.hub.get_slots()
+ comb = [
+ self._slot_count.field.w.eq(len(slots)),
+ self._trace_depth.field.w.eq(self.trace_depth)
+ ]
+ for slot, status in zip(slots, self._slot_status):
+ comb.append(status.field.w.eq(slot.state))
+ shift_tags = [self._trace[n].field.w.eq(self._trace[n+1].field.w)
+ for n in range(len(self._trace) - 1)]
+ shift_tags.append(self._trace[-1].field.w.eq(self.hub.tag_call))
+ sync = [If(self.hub.call, *shift_tags)]
+ return Fragment(comb, sync) + self.bank.get_fragment()
View
3  milkymist/framebuffer/__init__.py
@@ -247,10 +247,11 @@ def __init__(self, address, asmiport, simulation=False):
"hres", "hsync_start", "hsync_end", "hscan",
"vres", "vsync_start", "vsync_end", "vscan"])
g.add_connection(vtg, fifo)
- self._comp_actor = CompositeActor(g, debugger=False)
+ self._comp_actor = CompositeActor(g, debugger=True)
self.bank = csrgen.Bank(fi.actor.get_registers() + self._comp_actor.get_registers(),
address=address)
+ self._comp_actor.debugger.print_map()
# VGA clock input
if not simulation:
View
2  software/bios/Makefile
@@ -1,7 +1,7 @@
M2DIR=../..
include $(M2DIR)/software/common.mak
-OBJECTS=crt0.o isr.o ddrinit.o main.o microudp.o tftp.o boot-helper.o boot.o dataflow.o
+OBJECTS=crt0.o isr.o sdram.o main.o microudp.o tftp.o boot-helper.o boot.o dataflow.o
all: bios.bin
View
3  software/bios/main.c
@@ -13,7 +13,7 @@
#include <hw/mem.h>
#include <hw/minimac.h>
-#include "ddrinit.h"
+#include "sdram.h"
#include "dataflow.h"
#include "boot.h"
@@ -367,6 +367,7 @@ static void do_command(char *c)
else if(strcmp(token, "ddrwr") == 0) ddrwr(get_token(&c));
else if(strcmp(token, "memtest") == 0) memtest();
else if(strcmp(token, "ddrinit") == 0) ddrinit();
+ else if(strcmp(token, "asmiprobe") == 0) asmiprobe();
else if(strcmp(token, "dfs") == 0) dfs(get_token(&c));
View
32 software/bios/ddrinit.c → software/bios/sdram.c
@@ -3,8 +3,9 @@
#include <hw/dfii.h>
#include <hw/mem.h>
+#include <csrbase.h>
-#include "ddrinit.h"
+#include "sdram.h"
static void cdelay(int i)
{
@@ -196,3 +197,32 @@ int ddrinit(void)
return 1;
}
+
+static const char *format_slot_state(int state)
+{
+ switch(state) {
+ case 0: return "Empty";
+ case 1: return "Pending";
+ case 2: return "Processing";
+ default: return "UNEXPECTED VALUE";
+ }
+}
+
+void asmiprobe(void)
+{
+ volatile unsigned int *regs = (unsigned int *)ASMIPROBE_BASE;
+ int slot_count;
+ int trace_depth;
+ int i;
+ int offset;
+
+ offset = 0;
+ slot_count = regs[offset++];
+ trace_depth = regs[offset++];
+ for(i=0;i<slot_count;i++)
+ printf("Slot #%d: %s\n", i, format_slot_state(regs[offset++]));
+ printf("Latest tags:\n");
+ for(i=0;i<trace_depth;i++)
+ printf("%d ", regs[offset++]);
+ printf("\n");
+}
View
8 software/bios/ddrinit.h → software/bios/sdram.h
@@ -1,5 +1,5 @@
-#ifndef __DDRINIT_H
-#define __DDRINIT_H
+#ifndef __SDRAM_H
+#define __SDRAM_H
void ddrsw(void);
void ddrhw(void);
@@ -10,4 +10,6 @@ int memtest_silent(void);
void memtest(void);
int ddrinit(void);
-#endif /* __DDRINIT_H */
+void asmiprobe(void);
+
+#endif /* __SDRAM_H */
View
6 top.py
@@ -6,7 +6,7 @@
from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, \
- identifier, timer, minimac3, framebuffer
+ identifier, timer, minimac3, framebuffer, asmiprobe
from cmacros import get_macros
from constraints import Constraints
@@ -124,13 +124,15 @@ def get():
identifier0 = identifier.Identifier(csr_offset("ID"), 0x4D31, version, int(clk_freq))
timer0 = timer.Timer(csr_offset("TIMER0"))
fb0 = framebuffer.Framebuffer(csr_offset("FB"), asmiport_fb)
+ asmiprobe0 = asmiprobe.ASMIprobe(csr_offset("ASMIPROBE"), asmicon0.hub)
csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
uart0.bank.interface,
dfii0.bank.interface,
identifier0.bank.interface,
timer0.bank.interface,
minimac0.bank.interface,
- fb0.bank.interface
+ fb0.bank.interface,
+ asmiprobe0.bank.interface
])
#

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