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5 milkymist/lasmicon/__init__.py
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@@ -20,7 +20,7 @@ def __init__(self, bank_a, row_a, col_a):
self.mux_a = max(row_a, col_a)
class TimingSettings:
- def __init__(self, tRP, tRCD, tWR, tWTR, tREFI, tRFC, CL, read_latency, write_latency, read_time, write_time):
+ def __init__(self, tRP, tRCD, tWR, tWTR, tREFI, tRFC, read_latency, write_latency, req_queue_size, read_time, write_time):
self.tRP = tRP
self.tRCD = tRCD
self.tWR = tWR
@@ -28,10 +28,10 @@ def __init__(self, tRP, tRCD, tWR, tWTR, tREFI, tRFC, CL, read_latency, write_la
self.tREFI = tREFI
self.tRFC = tRFC
- self.CL = CL
self.read_latency = read_latency
self.write_latency = write_latency
+ self.req_queue_size = req_queue_size
self.read_time = read_time
self.write_time = write_time
@@ -48,6 +48,7 @@ def __init__(self, phy_settings, geom_settings, timing_settings):
aw=geom_settings.row_a + geom_settings.col_a - address_align,
dw=phy_settings.dfi_d*phy_settings.nphases,
nbanks=2**geom_settings.bank_a,
+ req_queue_size=timing_settings.req_queue_size,
read_latency=timing_settings.read_latency+1,
write_latency=timing_settings.write_latency+1)
self.nrowbits = geom_settings.col_a - address_align
32 milkymist/lasmicon/bankmachine.py
View
@@ -3,6 +3,7 @@
from migen.genlib.roundrobin import *
from migen.genlib.fsm import FSM
from migen.genlib.misc import optree
+from migen.genlib.fifo import SyncFIFO
from milkymist.lasmicon.multiplexer import *
@@ -33,19 +34,32 @@ def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
###
+ # Request FIFO
+ self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", flen(req.adr))], timing_settings.req_queue_size)
+ self.comb += [
+ self.req_fifo.din.we.eq(req.we),
+ self.req_fifo.din.adr.eq(req.adr),
+ self.req_fifo.we.eq(req.stb),
+ req.req_ack.eq(self.req_fifo.writable),
+
+ self.req_fifo.re.eq(req.dat_ack),
+ req.lock.eq(self.req_fifo.readable)
+ ]
+ reqf = self.req_fifo.dout
+
slicer = _AddressSlicer(geom_settings.col_a, address_align)
# Row tracking
has_openrow = Signal()
openrow = Signal(geom_settings.row_a)
hit = Signal()
- self.comb += hit.eq(openrow == slicer.row(req.adr))
+ self.comb += hit.eq(openrow == slicer.row(reqf.adr))
track_open = Signal()
track_close = Signal()
self.sync += [
If(track_open,
has_openrow.eq(1),
- openrow.eq(slicer.row(req.adr))
+ openrow.eq(slicer.row(reqf.adr))
),
If(track_close,
has_openrow.eq(0)
@@ -57,9 +71,9 @@ def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
self.comb += [
self.cmd.ba.eq(bankn),
If(s_row_adr,
- self.cmd.a.eq(slicer.row(req.adr))
+ self.cmd.a.eq(slicer.row(reqf.adr))
).Else(
- self.cmd.a.eq(slicer.col(req.adr))
+ self.cmd.a.eq(slicer.col(reqf.adr))
)
]
@@ -85,16 +99,16 @@ def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
fsm.act(fsm.REGULAR,
If(self.refresh_req,
fsm.next_state(fsm.REFRESH)
- ).Elif(req.stb,
+ ).Elif(self.req_fifo.readable,
If(has_openrow,
If(hit,
# NB: write-to-read specification is enforced by multiplexer
self.cmd.stb.eq(1),
- req.ack.eq(self.cmd.ack),
- self.cmd.is_read.eq(~req.we),
- self.cmd.is_write.eq(req.we),
+ req.dat_ack.eq(self.cmd.ack),
+ self.cmd.is_read.eq(~reqf.we),
+ self.cmd.is_write.eq(reqf.we),
self.cmd.cas_n.eq(0),
- self.cmd.we_n.eq(~req.we)
+ self.cmd.we_n.eq(~reqf.we)
).Else(
fsm.next_state(fsm.PRECHARGE)
)
4 top.py
View
@@ -14,7 +14,7 @@
version = get_macros("common/version.h")["VERSION"][1:-1]
-clk_freq = (62 + Fraction(1, 2))*1000000
+clk_freq = (83 + Fraction(1, 3))*1000000
sram_size = 4096 # in bytes
l2_size = 8192 # in bytes
@@ -43,10 +43,10 @@ def ns(t, margin=True):
tREFI=ns(7800, False),
tRFC=ns(70),
- CL=3,
read_latency=5,
write_latency=0,
+ req_queue_size=8,
read_time=32,
write_time=16
)

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