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2  build.py
@@ -18,8 +18,6 @@ def main():
18 18
 """, clk50=platform.lookup_request("clk50"))
19 19
 
20 20
 	platform.add_platform_command("""
21  
-INST "m1crg/pll" LOC="PLL_ADV_X0Y1";
22  
-INST "m1crg/vga_clock_gen" LOC="DCM_X0Y6";
23 21
 INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
24 22
 INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
25 23
 
54  milkymist/dvisampler/__init__.py
... ...
@@ -1,8 +1,6 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.fhdl.module import Module
3  
-from migen.bank.description import *
4  
-from migen.genlib.fifo import AsyncFIFO
5  
-from migen.actorlib import structuring, dma_asmi, spi
  3
+from migen.bank.description import AutoCSR
6 4
 
7 5
 from milkymist.dvisampler.edid import EDID
8 6
 from milkymist.dvisampler.clocking import Clocking
@@ -10,11 +8,11 @@
10 8
 from milkymist.dvisampler.charsync import CharSync
11 9
 from milkymist.dvisampler.decoding import Decoding
12 10
 from milkymist.dvisampler.chansync import ChanSync
13  
-from milkymist.dvisampler.syncpol import SyncPolarity
14  
-from milkymist.dvisampler.resdetection import ResolutionDetection
  11
+from milkymist.dvisampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction
  12
+from milkymist.dvisampler.dma import DMA
15 13
 
16 14
 class DVISampler(Module, AutoCSR):
17  
-	def __init__(self, pads):
  15
+	def __init__(self, pads, asmiport):
18 16
 		self.submodules.edid = EDID(pads)
19 17
 		self.submodules.clocking = Clocking(pads)
20 18
 
@@ -54,6 +52,8 @@ def __init__(self, pads):
54 52
 			self.chansync.data_in2.eq(self.data2_decod.output),
55 53
 		]
56 54
 
  55
+		###
  56
+
57 57
 		self.submodules.syncpol = SyncPolarity()
58 58
 		self.comb += [
59 59
 			self.syncpol.valid_i.eq(self.chansync.chan_synced),
@@ -64,42 +64,20 @@ def __init__(self, pads):
64 64
 
65 65
 		self.submodules.resdetection = ResolutionDetection()
66 66
 		self.comb += [
  67
+			self.resdetection.valid_i.eq(self.syncpol.valid_o),
67 68
 			self.resdetection.de.eq(self.syncpol.de),
68 69
 			self.resdetection.vsync.eq(self.syncpol.vsync)
69 70
 		]
70 71
 
71  
-class RawDVISampler(Module, AutoCSR):
72  
-	def __init__(self, pads, asmiport):
73  
-		self.submodules.edid = EDID(pads)
74  
-		self.submodules.clocking = Clocking(pads)
75  
-
76  
-		invert = False
77  
-		try:
78  
-			s = getattr(pads, "data0")
79  
-		except AttributeError:
80  
-			s = getattr(pads, "data0_n")
81  
-			invert = True
82  
-		self.submodules.data0_cap = DataCapture(8, invert)
  72
+		self.submodules.frame = FrameExtraction()
83 73
 		self.comb += [
84  
-			self.data0_cap.pad.eq(s),
85  
-			self.data0_cap.serdesstrobe.eq(self.clocking.serdesstrobe)
  74
+			self.frame.valid_i.eq(self.syncpol.valid_o),
  75
+			self.frame.de.eq(self.syncpol.de),
  76
+			self.frame.vsync.eq(self.syncpol.vsync),
  77
+			self.frame.r.eq(self.syncpol.r),
  78
+			self.frame.g.eq(self.syncpol.g),
  79
+			self.frame.b.eq(self.syncpol.b)
86 80
 		]
87 81
 
88  
-		fifo = AsyncFIFO(10, 1024)
89  
-		self.add_submodule(fifo, {"write": "pix", "read": "sys"})
90  
-		self.comb += [
91  
-			fifo.din.eq(self.data0_cap.d),
92  
-			fifo.we.eq(1)
93  
-		]
94  
-
95  
-		pack_factor = asmiport.hub.dw//16
96  
-		self.submodules.packer = structuring.Pack([("word", 10), ("pad", 6)], pack_factor)
97  
-		self.submodules.cast = structuring.Cast(self.packer.source.payload.layout, asmiport.hub.dw)
98  
-		self.submodules.dma = spi.DMAWriteController(dma_asmi.Writer(asmiport), spi.MODE_SINGLE_SHOT)
99  
-		self.comb += [
100  
-			self.packer.sink.stb.eq(fifo.readable),
101  
-			fifo.re.eq(self.packer.sink.ack),
102  
-			self.packer.sink.payload.word.eq(fifo.dout),
103  
-			self.packer.source.connect(self.cast.sink, match_by_position=True),
104  
-			self.cast.source.connect(self.dma.data, match_by_position=True)
105  
-		]
  82
+		self.submodules.dma = DMA(asmiport)
  83
+		self.comb += self.frame.frame.connect(self.dma.frame)
148  milkymist/dvisampler/analysis.py
... ...
@@ -0,0 +1,148 @@
  1
+from migen.fhdl.structure import *
  2
+from migen.fhdl.module import Module
  3
+from migen.genlib.cdc import MultiReg
  4
+from migen.genlib.fifo import AsyncFIFO
  5
+from migen.genlib.record import Record
  6
+from migen.bank.description import *
  7
+from migen.flow.actor import *
  8
+
  9
+from milkymist.dvisampler.common import channel_layout, frame_layout
  10
+
  11
+class SyncPolarity(Module):
  12
+	def __init__(self):
  13
+		self.valid_i = Signal()
  14
+		self.data_in0 = Record(channel_layout)
  15
+		self.data_in1 = Record(channel_layout)
  16
+		self.data_in2 = Record(channel_layout)
  17
+
  18
+		self.valid_o = Signal()
  19
+		self.de = Signal()
  20
+		self.hsync = Signal()
  21
+		self.vsync = Signal()
  22
+		self.r = Signal(8)
  23
+		self.g = Signal(8)
  24
+		self.b = Signal(8)
  25
+
  26
+		###
  27
+
  28
+		de = self.data_in0.de
  29
+		de_r = Signal()
  30
+		c = self.data_in0.c
  31
+		c_polarity = Signal(2)
  32
+		c_out = Signal(2)
  33
+
  34
+		self.comb += [
  35
+			self.de.eq(de_r),
  36
+			self.hsync.eq(c_out[0]),
  37
+			self.vsync.eq(c_out[1])
  38
+		]
  39
+
  40
+		self.sync.pix += [
  41
+			self.valid_o.eq(self.valid_i),
  42
+			self.r.eq(self.data_in2.d),
  43
+			self.g.eq(self.data_in1.d),
  44
+			self.b.eq(self.data_in0.d),
  45
+
  46
+			de_r.eq(de),
  47
+			If(de_r & ~de,
  48
+				c_polarity.eq(c),
  49
+				c_out.eq(0)
  50
+			).Else(
  51
+				c_out.eq(c ^ c_polarity)
  52
+			)
  53
+		]
  54
+
  55
+class ResolutionDetection(Module, AutoCSR):
  56
+	def __init__(self, nbits=11):
  57
+		self.valid_i = Signal()
  58
+		self.vsync = Signal()
  59
+		self.de = Signal()
  60
+
  61
+		self._hres = CSRStatus(nbits)
  62
+		self._vres = CSRStatus(nbits)
  63
+
  64
+		###
  65
+
  66
+		# Detect DE transitions
  67
+		de_r = Signal()
  68
+		pn_de = Signal()
  69
+		self.sync.pix += de_r.eq(self.de)
  70
+		self.comb += pn_de.eq(~self.de & de_r)
  71
+
  72
+		# HRES
  73
+		hcounter = Signal(nbits)
  74
+		self.sync.pix += If(self.valid_i & self.de,
  75
+				hcounter.eq(hcounter + 1)
  76
+			).Else(
  77
+				hcounter.eq(0)
  78
+			)
  79
+
  80
+		hcounter_st = Signal(nbits)
  81
+		self.sync.pix += If(self.valid_i,
  82
+				If(pn_de, hcounter_st.eq(hcounter))
  83
+			).Else(
  84
+				hcounter_st.eq(0)
  85
+			)
  86
+		self.specials += MultiReg(hcounter_st, self._hres.status)
  87
+
  88
+		# VRES
  89
+		vsync_r = Signal()
  90
+		p_vsync = Signal()
  91
+		self.sync.pix += vsync_r.eq(self.vsync),
  92
+		self.comb += p_vsync.eq(self.vsync & ~vsync_r)
  93
+
  94
+		vcounter = Signal(nbits)
  95
+		self.sync.pix += If(self.valid_i & p_vsync,
  96
+				vcounter.eq(0)
  97
+			).Elif(pn_de,
  98
+				vcounter.eq(vcounter + 1)
  99
+			)
  100
+
  101
+		vcounter_st = Signal(nbits)
  102
+		self.sync.pix += If(self.valid_i,
  103
+				If(p_vsync, vcounter_st.eq(vcounter))
  104
+			).Else(
  105
+				vcounter_st.eq(0)
  106
+			)
  107
+		self.specials += MultiReg(vcounter_st, self._vres.status)
  108
+
  109
+class FrameExtraction(Module):
  110
+	def __init__(self):
  111
+		# in pix clock domain
  112
+		self.valid_i = Signal()
  113
+		self.vsync = Signal()
  114
+		self.de = Signal()
  115
+		self.r = Signal(8)
  116
+		self.g = Signal(8)
  117
+		self.b = Signal(8)
  118
+
  119
+		# in sys clock domain
  120
+		self.frame = Source(frame_layout)
  121
+		self.busy = Signal()
  122
+
  123
+		###
  124
+
  125
+		fifo_stb = Signal()
  126
+		fifo_in = Record(frame_layout)
  127
+		self.comb += [
  128
+			fifo_stb.eq(self.valid_i & self.de),
  129
+			fifo_in.r.eq(self.r),
  130
+			fifo_in.g.eq(self.g),
  131
+			fifo_in.b.eq(self.b),
  132
+		]
  133
+		vsync_r = Signal()
  134
+		self.sync.pix += [
  135
+			If(self.vsync & ~vsync_r, fifo_in.parity.eq(~fifo_in.parity)),
  136
+			vsync_r.eq(self.vsync)
  137
+		]
  138
+
  139
+		fifo = AsyncFIFO(layout_len(frame_layout), 256)
  140
+		self.add_submodule(fifo, {"write": "pix", "read": "sys"})
  141
+		self.comb += [
  142
+			fifo.we.eq(fifo_stb),
  143
+			fifo.din.eq(fifo_in.raw_bits()),
  144
+			self.frame.stb.eq(fifo.readable),
  145
+			self.frame.payload.raw_bits().eq(fifo.dout),
  146
+			fifo.re.eq(self.frame.ack),
  147
+			self.busy.eq(0)
  148
+		]
1  milkymist/dvisampler/common.py
... ...
@@ -1,2 +1,3 @@
1 1
 control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011]
2 2
 channel_layout = [("d", 8), ("c", 2), ("de", 1)]
  3
+frame_layout = [("parity", 1), ("r", 8), ("g", 8), ("b", 8)]
46  milkymist/dvisampler/debug.py
... ...
@@ -0,0 +1,46 @@
  1
+from migen.fhdl.structure import *
  2
+from migen.fhdl.module import Module
  3
+from migen.genlib.fifo import AsyncFIFO
  4
+from migen.genlib.record import layout_len
  5
+from migen.bank.description import AutoCSR
  6
+from migen.actorlib import structuring, dma_asmi, spi
  7
+
  8
+from milkymist.dvisampler.edid import EDID
  9
+from milkymist.dvisampler.clocking import Clocking
  10
+from milkymist.dvisampler.datacapture import DataCapture
  11
+
  12
+class RawDVISampler(Module, AutoCSR):
  13
+	def __init__(self, pads, asmiport):
  14
+		self.submodules.edid = EDID(pads)
  15
+		self.submodules.clocking = Clocking(pads)
  16
+
  17
+		invert = False
  18
+		try:
  19
+			s = getattr(pads, "data0")
  20
+		except AttributeError:
  21
+			s = getattr(pads, "data0_n")
  22
+			invert = True
  23
+		self.submodules.data0_cap = DataCapture(8, invert)
  24
+		self.comb += [
  25
+			self.data0_cap.pad.eq(s),
  26
+			self.data0_cap.serdesstrobe.eq(self.clocking.serdesstrobe)
  27
+		]
  28
+
  29
+		fifo = AsyncFIFO(10, 256)
  30
+		self.add_submodule(fifo, {"write": "pix", "read": "sys"})
  31
+		self.comb += [
  32
+			fifo.din.eq(self.data0_cap.d),
  33
+			fifo.we.eq(1)
  34
+		]
  35
+
  36
+		pack_factor = asmiport.hub.dw//16
  37
+		self.submodules.packer = structuring.Pack([("word", 10), ("pad", 6)], pack_factor)
  38
+		self.submodules.cast = structuring.Cast(self.packer.source.payload.layout, asmiport.hub.dw)
  39
+		self.submodules.dma = spi.DMAWriteController(dma_asmi.Writer(asmiport), spi.MODE_SINGLE_SHOT, free_flow=True)
  40
+		self.comb += [
  41
+			self.packer.sink.stb.eq(fifo.readable),
  42
+			fifo.re.eq(self.packer.sink.ack),
  43
+			self.packer.sink.payload.word.eq(fifo.dout),
  44
+			self.packer.source.connect(self.cast.sink, match_by_position=True),
  45
+			self.cast.source.connect(self.dma.data, match_by_position=True)
  46
+		]
48  milkymist/dvisampler/dma.py
... ...
@@ -0,0 +1,48 @@
  1
+from migen.fhdl.structure import *
  2
+from migen.fhdl.module import Module
  3
+from migen.bank.description import *
  4
+from migen.flow.actor import *
  5
+from migen.actorlib import structuring, dma_asmi, spi
  6
+
  7
+from milkymist.dvisampler.common import frame_layout
  8
+
  9
+class DMA(Module):
  10
+	def __init__(self, asmiport):
  11
+		self.frame = Sink(frame_layout)
  12
+		self.shoot = CSR()
  13
+
  14
+		###
  15
+
  16
+		sof = Signal()
  17
+		parity_r = Signal()
  18
+		self.comb += sof.eq(self.frame.stb & (parity_r ^ self.frame.payload.parity))
  19
+		self.sync += If(self.frame.stb & self.frame.ack, parity_r.eq(self.frame.payload.parity))
  20
+
  21
+		pending = Signal()
  22
+		frame_en = Signal()
  23
+		self.sync += [
  24
+			If(sof,
  25
+				frame_en.eq(0),
  26
+				If(pending, frame_en.eq(1)),
  27
+				pending.eq(0)
  28
+			),
  29
+			If(self.shoot.re, pending.eq(1))
  30
+		]
  31
+
  32
+		pack_factor = asmiport.hub.dw//32
  33
+		self.submodules.packer = structuring.Pack(list(reversed([("pad", 2), ("r", 10), ("g", 10), ("b", 10)])), pack_factor)
  34
+		self.submodules.cast = structuring.Cast(self.packer.source.payload.layout, asmiport.hub.dw, reverse_from=False)
  35
+		self.submodules.dma = spi.DMAWriteController(dma_asmi.Writer(asmiport), spi.MODE_EXTERNAL)
  36
+		self.comb += [
  37
+			self.dma.generator.trigger.eq(self.shoot.re),
  38
+			self.packer.sink.stb.eq(self.frame.stb & frame_en),
  39
+			self.frame.ack.eq(self.packer.sink.ack | (~frame_en & ~(pending & sof))),
  40
+			self.packer.sink.payload.r.eq(self.frame.payload.r << 2),
  41
+			self.packer.sink.payload.g.eq(self.frame.payload.g << 2),
  42
+			self.packer.sink.payload.b.eq(self.frame.payload.b << 2),
  43
+			self.packer.source.connect(self.cast.sink, match_by_position=True),
  44
+			self.cast.source.connect(self.dma.data, match_by_position=True)
  45
+		]
  46
+
  47
+	def get_csrs(self):
  48
+		return [self.shoot] + self.dma.get_csrs()
49  milkymist/dvisampler/resdetection.py
... ...
@@ -1,49 +0,0 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
3  
-from migen.genlib.cdc import MultiReg
4  
-from migen.bank.description import *
5  
-
6  
-class ResolutionDetection(Module, AutoCSR):
7  
-	def __init__(self, nbits=11):
8  
-		self.vsync = Signal()
9  
-		self.de = Signal()
10  
-
11  
-		self._hres = CSRStatus(nbits)
12  
-		self._vres = CSRStatus(nbits)
13  
-
14  
-		###
15  
-
16  
-		# Detect DE transitions
17  
-		de_r = Signal()
18  
-		pn_de = Signal()
19  
-		self.sync.pix += de_r.eq(self.de)
20  
-		self.comb += pn_de.eq(~self.de & de_r)
21  
-
22  
-		# HRES
23  
-		hcounter = Signal(nbits)
24  
-		self.sync.pix += If(self.de,
25  
-				hcounter.eq(hcounter + 1)
26  
-			).Else(
27  
-				hcounter.eq(0)
28  
-			)
29  
-
30  
-		hcounter_st = Signal(nbits)
31  
-		self.sync.pix += If(pn_de, hcounter_st.eq(hcounter))
32  
-		self.specials += MultiReg(hcounter_st, self._hres.status)
33  
-
34  
-		# VRES
35  
-		vsync_r = Signal()
36  
-		p_vsync = Signal()
37  
-		self.sync.pix += vsync_r.eq(self.vsync),
38  
-		self.comb += p_vsync.eq(self.vsync & ~vsync_r)
39  
-
40  
-		vcounter = Signal(nbits)
41  
-		self.sync.pix += If(p_vsync,
42  
-				vcounter.eq(0)
43  
-			).Elif(pn_de,
44  
-				vcounter.eq(vcounter + 1)
45  
-			)
46  
-
47  
-		vcounter_st = Signal(nbits)
48  
-		self.sync.pix += If(p_vsync, vcounter_st.eq(vcounter))
49  
-		self.specials += MultiReg(vcounter_st, self._vres.status)
49  milkymist/dvisampler/syncpol.py
... ...
@@ -1,49 +0,0 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
3  
-from migen.genlib.record import Record
4  
-
5  
-from milkymist.dvisampler.common import channel_layout
6  
-
7  
-class SyncPolarity(Module):
8  
-	def __init__(self):
9  
-		self.valid_i = Signal()
10  
-		self.data_in0 = Record(channel_layout)
11  
-		self.data_in1 = Record(channel_layout)
12  
-		self.data_in2 = Record(channel_layout)
13  
-
14  
-		self.valid_o = Signal()
15  
-		self.de = Signal()
16  
-		self.hsync = Signal()
17  
-		self.vsync = Signal()
18  
-		self.r = Signal(8)
19  
-		self.g = Signal(8)
20  
-		self.b = Signal(8)
21  
-
22  
-		###
23  
-
24  
-		de = self.data_in0.de
25  
-		de_r = Signal()
26  
-		c = self.data_in0.c
27  
-		c_polarity = Signal(2)
28  
-		c_out = Signal(2)
29  
-
30  
-		self.comb += [
31  
-			self.de.eq(de_r),
32  
-			self.hsync.eq(c_out[0]),
33  
-			self.vsync.eq(c_out[1])
34  
-		]
35  
-
36  
-		self.sync.pix += [
37  
-			self.valid_o.eq(self.valid_i),
38  
-			self.r.eq(self.data_in2.d),
39  
-			self.g.eq(self.data_in1.d),
40  
-			self.b.eq(self.data_in0.d),
41  
-
42  
-			de_r.eq(de),
43  
-			If(de_r & ~de,
44  
-				c_polarity.eq(c),
45  
-				c_out.eq(0)
46  
-			).Else(
47  
-				c_out.eq(c ^ c_polarity)
48  
-			)
49  
-		]
17  software/videomixer/main.c
@@ -3,10 +3,12 @@
3 3
 
4 4
 #include <irq.h>
5 5
 #include <uart.h>
  6
+#include <console.h>
6 7
 #include <hw/csr.h>
7 8
 #include <hw/flags.h>
8 9
 
9 10
 static int d0, d1, d2;
  11
+static unsigned int framebuffer[640*480] __attribute__((aligned(16)));
10 12
 
11 13
 static void print_status(void)
12 14
 {
@@ -22,6 +24,17 @@ static void print_status(void)
22 24
 		dvisampler0_resdetection_vres_read());
23 25
 }
24 26
 
  27
+static void capture_fb(void)
  28
+{
  29
+	dvisampler0_dma_base_write((unsigned int)framebuffer);
  30
+	dvisampler0_dma_length_write(sizeof(framebuffer));
  31
+	dvisampler0_dma_shoot_write(1);
  32
+
  33
+	printf("waiting for DMA...");
  34
+	while(dvisampler0_dma_busy_read());
  35
+	printf("done\n");
  36
+}
  37
+
25 38
 static void calibrate_delays(void)
26 39
 {
27 40
 	dvisampler0_data0_cap_dly_ctl_write(DVISAMPLER_DELAY_CAL);
@@ -119,6 +132,8 @@ static void vmix(void)
119 132
 				adjust_phase();
120 133
 				counter = 0;
121 134
 			}
  135
+			if(readchar_nonblock() && (readchar() == 'c'))
  136
+				capture_fb();
122 137
 		}
123 138
 		printf("PLL unlocked\n");
124 139
 	}
@@ -132,6 +147,8 @@ int main(void)
132 147
 	
133 148
 	puts("Minimal video mixer software built "__DATE__" "__TIME__"\n");
134 149
 	
  150
+	fb_base_write((unsigned int)framebuffer);
  151
+	fb_enable_write(1);
135 152
 	vmix();
136 153
 	
137 154
 	return 0;
5  top.py
@@ -92,6 +92,7 @@ def __init__(self, platform):
92 92
 		self.submodules.asmicon = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing)
93 93
 		asmiport_wb = self.asmicon.hub.get_port()
94 94
 		asmiport_fb = self.asmicon.hub.get_port(3)
  95
+		asmiport_dvi0 = self.asmicon.hub.get_port(2)
95 96
 		self.asmicon.finalize()
96 97
 		
97 98
 		#
@@ -141,8 +142,8 @@ def __init__(self, platform):
141 142
 		self.submodules.timer0 = timer.Timer()
142 143
 		self.submodules.fb = framebuffer.Framebuffer(platform.request("vga"), asmiport_fb)
143 144
 		self.submodules.asmiprobe = asmiprobe.ASMIprobe(self.asmicon.hub)
144  
-		self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0))
145  
-		self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1))
  145
+		self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0), asmiport_dvi0)
  146
+		#self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1))
146 147
 
147 148
 		self.submodules.csrbankarray = csrgen.BankArray(self,
148 149
 			lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
10  verilog/m1crg/m1crg.v
@@ -209,6 +209,12 @@ BUFG bufg_x1(
209 209
 	.O(sys_clk)
210 210
 );
211 211
 
  212
+wire clk50g;
  213
+BUFG bufg_50(
  214
+	.I(pllout4),
  215
+	.O(clk50g)
  216
+);
  217
+
212 218
 wire clk2x_off;
213 219
 BUFG bufg_x2_offclk(
214 220
 	.I(pllout5),
@@ -253,7 +259,7 @@ ODDR2 #(
253 259
  * Ethernet PHY 
254 260
  */
255 261
 
256  
-always @(posedge pllout4)
  262
+always @(posedge clk50g)
257 263
 	eth_phy_clk_pad <= ~eth_phy_clk_pad;
258 264
 
259 265
 /* Let the synthesizer insert the appropriate buffers */
@@ -277,7 +283,7 @@ DCM_CLKGEN #(
277 283
 	.CLKFX180(),
278 284
 	.CLKFXDV(),
279 285
 	.STATUS(),
280  
-	.CLKIN(pllout4),
  286
+	.CLKIN(clk50g),
281 287
 	.FREEZEDCM(1'b0),
282 288
 	.PROGCLK(vga_progclk),
283 289
 	.PROGDATA(vga_progdata),

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