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29  milkymist/sram/__init__.py
... ...
@@ -1,29 +0,0 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.bus import wishbone
3  
-
4  
-class SRAM:
5  
-	def __init__(self, depth):
6  
-		self.bus = wishbone.Interface()
7  
-		self.depth = depth
8  
-	
9  
-	def get_fragment(self):
10  
-		# memory
11  
-		mem = Memory(32, self.depth)
12  
-		port = mem.get_port(write_capable=True, we_granularity=8)
13  
-		# generate write enable signal
14  
-		comb = [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
15  
-			for i in range(4)]
16  
-		# address and data
17  
-		comb += [
18  
-			port.adr.eq(self.bus.adr[:len(port.adr)]),
19  
-			port.dat_w.eq(self.bus.dat_w),
20  
-			self.bus.dat_r.eq(port.dat_r)
21  
-		]
22  
-		# generate ack
23  
-		sync = [
24  
-			self.bus.ack.eq(0),
25  
-			If(self.bus.cyc & self.bus.stb & ~self.bus.ack,
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-				self.bus.ack.eq(1)
27  
-			)
28  
-		]
29  
-		return Fragment(comb, sync, memories=[mem])
4  top.py
@@ -5,7 +5,7 @@
5 5
 from migen.fhdl import verilog, autofragment
6 6
 from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
7 7
 
8  
-from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, \
  8
+from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, asmicon, \
9 9
 	identifier, timer, minimac3, framebuffer, asmiprobe
10 10
 from cmacros import get_macros
11 11
 from constraints import Constraints
@@ -81,7 +81,7 @@ def get():
81 81
 	#
82 82
 	cpu0 = lm32.LM32()
83 83
 	norflash0 = norflash.NorFlash(25, 12)
84  
-	sram0 = sram.SRAM(sram_size//4)
  84
+	sram0 = wishbone.SRAM(sram_size)
85 85
 	minimac0 = minimac3.MiniMAC(csr_offset("MINIMAC"))
86 86
 	wishbone2asmi0 = wishbone2asmi.WB2ASMI(l2_size//4, asmiport_wb)
87 87
 	wishbone2csr0 = wishbone2csr.WB2CSR()

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