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  • 2 commits
  • 2 files changed
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  • 1 contributor
Showing with 2 additions and 31 deletions.
  1. +0 −29 milkymist/sram/__init__.py
  2. +2 −2 top.py
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29 milkymist/sram/__init__.py
@@ -1,29 +0,0 @@
-from migen.fhdl.structure import *
-from migen.bus import wishbone
-
-class SRAM:
- def __init__(self, depth):
- self.bus = wishbone.Interface()
- self.depth = depth
-
- def get_fragment(self):
- # memory
- mem = Memory(32, self.depth)
- port = mem.get_port(write_capable=True, we_granularity=8)
- # generate write enable signal
- comb = [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
- for i in range(4)]
- # address and data
- comb += [
- port.adr.eq(self.bus.adr[:len(port.adr)]),
- port.dat_w.eq(self.bus.dat_w),
- self.bus.dat_r.eq(port.dat_r)
- ]
- # generate ack
- sync = [
- self.bus.ack.eq(0),
- If(self.bus.cyc & self.bus.stb & ~self.bus.ack,
- self.bus.ack.eq(1)
- )
- ]
- return Fragment(comb, sync, memories=[mem])
View
4 top.py
@@ -5,7 +5,7 @@
from migen.fhdl import verilog, autofragment
from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
-from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, \
+from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, asmicon, \
identifier, timer, minimac3, framebuffer, asmiprobe
from cmacros import get_macros
from constraints import Constraints
@@ -81,7 +81,7 @@ def get():
#
cpu0 = lm32.LM32()
norflash0 = norflash.NorFlash(25, 12)
- sram0 = sram.SRAM(sram_size//4)
+ sram0 = wishbone.SRAM(sram_size)
minimac0 = minimac3.MiniMAC(csr_offset("MINIMAC"))
wishbone2asmi0 = wishbone2asmi.WB2ASMI(l2_size//4, asmiport_wb)
wishbone2csr0 = wishbone2csr.WB2CSR()

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