Skip to content
This repository

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP
  • 2 commits
  • 5 files changed
  • 0 comments
  • 1 contributor
48  milkymist/dvisampler/dma.py
... ...
@@ -1,9 +1,8 @@
1 1
 from migen.fhdl.std import *
2  
-from migen.genlib.fsm import FSM
  2
+from migen.genlib.fsm import FSM, NextState
3 3
 from migen.bank.description import *
4 4
 from migen.bank.eventmanager import *
5 5
 from migen.flow.actor import *
6  
-from migen.genlib.fifo import SyncFIFO
7 6
 from migen.actorlib import dma_lasmi
8 7
 
9 8
 from milkymist.dvisampler.common import frame_layout
@@ -55,27 +54,6 @@ def __init__(self, nslots, addr_bits, alignment_bits):
55 54
 		]
56 55
 		self.comb += [slot.address_done.eq(self.address_done & (current_slot == n)) for n, slot in enumerate(slots)]
57 56
 
58  
-class _BufferedWriter(Module):
59  
-	def __init__(self, lasmim, depth=4):
60  
-		self.address_data = Sink([("a", lasmim.aw), ("d", lasmim.dw)])
61  
-		self.busy = Signal()
62  
-
63  
-		###
64  
-
65  
-		self.submodules.writer = dma_lasmi.Writer(lasmim)
66  
-		self.submodules.fifo = SyncFIFO(lasmim.aw + lasmim.dw, depth)
67  
-		self.comb += [
68  
-			self.fifo.din.eq(self.address_data.payload.raw_bits()),
69  
-			self.fifo.we.eq(self.address_data.stb),
70  
-			self.address_data.ack.eq(self.fifo.writable),
71  
-
72  
-			self.writer.address_data.payload.raw_bits().eq(self.fifo.dout),
73  
-			self.fifo.re.eq(self.writer.address_data.ack),
74  
-			self.writer.address_data.stb.eq(self.fifo.readable),
75  
-			
76  
-			self.busy.eq(self.writer.busy | self.fifo.readable)
77  
-		]
78  
-
79 57
 class DMA(Module):
80 58
 	def __init__(self, lasmim, nslots):
81 59
 		bus_aw = lasmim.aw
@@ -134,45 +112,43 @@ def __init__(self, lasmim, nslots):
134 112
 			)
135 113
 
136 114
 		# bus accessor
137  
-		self.submodules._bus_accessor = _BufferedWriter(lasmim)
  115
+		self.submodules._bus_accessor = dma_lasmi.Writer(lasmim)
138 116
 		self.comb += [
139 117
 			self._bus_accessor.address_data.payload.a.eq(current_address),
140 118
 			self._bus_accessor.address_data.payload.d.eq(cur_memory_word)
141 119
 		]
142 120
 
143 121
 		# control FSM
144  
-		fsm = FSM("WAIT_SOF", "TRANSFER_PIXEL", "TO_MEMORY", "EOF")
  122
+		fsm = FSM()
145 123
 		self.submodules += fsm
146 124
 
147  
-		fsm.act(fsm.WAIT_SOF,
  125
+		fsm.act("WAIT_SOF",
148 126
 			reset_words.eq(1),
149 127
 			self.frame.ack.eq(~self._slot_array.address_valid | ~sof),
150  
-			If(self._slot_array.address_valid & sof & self.frame.stb, fsm.next_state(fsm.TRANSFER_PIXEL))
  128
+			If(self._slot_array.address_valid & sof & self.frame.stb, NextState("TRANSFER_PIXEL"))
151 129
 		)
152  
-		fsm.act(fsm.TRANSFER_PIXEL,
  130
+		fsm.act("TRANSFER_PIXEL",
153 131
 			self.frame.ack.eq(1),
154 132
 			If(self.frame.stb,
155 133
 				write_pixel.eq(1),
156  
-				If(last_pixel,
157  
-					fsm.next_state(fsm.TO_MEMORY)
158  
-				)
  134
+				If(last_pixel, NextState("TO_MEMORY"))
159 135
 			)
160 136
 		)
161  
-		fsm.act(fsm.TO_MEMORY,
  137
+		fsm.act("TO_MEMORY",
162 138
 			self._bus_accessor.address_data.stb.eq(1),
163 139
 			If(self._bus_accessor.address_data.ack,
164 140
 				count_word.eq(1),
165 141
 				If(last_word,
166  
-					fsm.next_state(fsm.EOF)
  142
+					NextState("EOF")
167 143
 				).Else(
168  
-					fsm.next_state(fsm.TRANSFER_PIXEL)
  144
+					NextState("TRANSFER_PIXEL")
169 145
 				)
170 146
 			)
171 147
 		)
172  
-		fsm.act(fsm.EOF,
  148
+		fsm.act("EOF",
173 149
 			If(~self._bus_accessor.busy,
174 150
 				self._slot_array.address_done.eq(1),
175  
-				fsm.next_state(fsm.WAIT_SOF)
  151
+				NextState("WAIT_SOF")
176 152
 			)
177 153
 		)
178 154
 
59  milkymist/dvisampler/edid.py
... ...
@@ -1,7 +1,7 @@
1 1
 from migen.fhdl.std import *
2 2
 from migen.fhdl.specials import Tristate
3 3
 from migen.genlib.cdc import MultiReg
4  
-from migen.genlib.fsm import FSM
  4
+from migen.genlib.fsm import FSM, NextState
5 5
 from migen.genlib.misc import chooser
6 6
 from migen.bank.description import AutoCSR
7 7
 
@@ -102,79 +102,76 @@ def __init__(self, pads, default=_default_edid):
102 102
 		self.sync += If(data_drv_en, data_drv.eq(1)).Elif(data_drv_stop, data_drv.eq(0))
103 103
 		self.sync += If(data_drv_en, chooser(rdport.dat_r, counter, data_bit, 8, reverse=True))
104 104
 
105  
-		states = ["WAIT_START",
106  
-			"RCV_ADDRESS", "ACK_ADDRESS0", "ACK_ADDRESS1", "ACK_ADDRESS2",
107  
-			"RCV_OFFSET", "ACK_OFFSET0", "ACK_OFFSET1", "ACK_OFFSET2",
108  
-			"READ", "ACK_READ"]
109  
-		fsm = FSM(*states)
  105
+		fsm = FSM()
110 106
 		self.submodules += fsm
111 107
 	
112  
-		fsm.act(fsm.RCV_ADDRESS,
  108
+		fsm.act("WAIT_START")
  109
+		fsm.act("RCV_ADDRESS",
113 110
 			If(counter == 8,
114 111
 				If(din[1:] == 0x50,
115 112
 					update_is_read.eq(1),
116  
-					fsm.next_state(fsm.ACK_ADDRESS0)
  113
+					NextState("ACK_ADDRESS0")
117 114
 				).Else(
118  
-					fsm.next_state(fsm.WAIT_START)
  115
+					NextState("WAIT_START")
119 116
 				)
120 117
 			)
121 118
 		)
122  
-		fsm.act(fsm.ACK_ADDRESS0,
123  
-			If(~scl_i, fsm.next_state(fsm.ACK_ADDRESS1))
  119
+		fsm.act("ACK_ADDRESS0",
  120
+			If(~scl_i, NextState("ACK_ADDRESS1"))
124 121
 		)
125  
-		fsm.act(fsm.ACK_ADDRESS1,
  122
+		fsm.act("ACK_ADDRESS1",
126 123
 			zero_drv.eq(1),
127  
-			If(scl_i, fsm.next_state(fsm.ACK_ADDRESS2))
  124
+			If(scl_i, NextState("ACK_ADDRESS2"))
128 125
 		)
129  
-		fsm.act(fsm.ACK_ADDRESS2,
  126
+		fsm.act("ACK_ADDRESS2",
130 127
 			zero_drv.eq(1),
131 128
 			If(~scl_i,
132 129
 				If(is_read,
133  
-					fsm.next_state(fsm.READ)
  130
+					NextState("READ")
134 131
 				).Else(
135  
-					fsm.next_state(fsm.RCV_OFFSET)
  132
+					NextState("RCV_OFFSET")
136 133
 				)
137 134
 			)
138 135
 		)
139 136
 
140  
-		fsm.act(fsm.RCV_OFFSET,
  137
+		fsm.act("RCV_OFFSET",
141 138
 			If(counter == 8,
142 139
 				oc_load.eq(1),
143  
-				fsm.next_state(fsm.ACK_OFFSET0)
  140
+				NextState("ACK_OFFSET0")
144 141
 			)
145 142
 		)
146  
-		fsm.act(fsm.ACK_OFFSET0,
147  
-			If(~scl_i, fsm.next_state(fsm.ACK_OFFSET1))
  143
+		fsm.act("ACK_OFFSET0",
  144
+			If(~scl_i, NextState("ACK_OFFSET1"))
148 145
 		)
149  
-		fsm.act(fsm.ACK_OFFSET1,
  146
+		fsm.act("ACK_OFFSET1",
150 147
 			zero_drv.eq(1),
151  
-			If(scl_i, fsm.next_state(fsm.ACK_OFFSET2))
  148
+			If(scl_i, NextState("ACK_OFFSET2"))
152 149
 		)
153  
-		fsm.act(fsm.ACK_OFFSET2,
  150
+		fsm.act("ACK_OFFSET2",
154 151
 			zero_drv.eq(1),
155  
-			If(~scl_i, fsm.next_state(fsm.RCV_ADDRESS))
  152
+			If(~scl_i, NextState("RCV_ADDRESS"))
156 153
 		)
157 154
 
158  
-		fsm.act(fsm.READ,
  155
+		fsm.act("READ",
159 156
 			If(~scl_i,
160 157
 				If(counter == 8,
161 158
 					data_drv_stop.eq(1),
162  
-					fsm.next_state(fsm.ACK_READ)
  159
+					NextState("ACK_READ")
163 160
 				).Else(
164 161
 					data_drv_en.eq(1)
165 162
 				)
166 163
 			)
167 164
 		)
168  
-		fsm.act(fsm.ACK_READ,
  165
+		fsm.act("ACK_READ",
169 166
 			If(scl_rising,
170 167
 				oc_inc.eq(1),
171 168
 				If(sda_i,
172  
-					fsm.next_state(fsm.WAIT_START)
  169
+					NextState("WAIT_START")
173 170
 				).Else(
174  
-					fsm.next_state(fsm.READ)
  171
+					NextState("READ")
175 172
 				)
176 173
 			)
177 174
 		)
178 175
 
179  
-		for state in states:
180  
-			fsm.act(getattr(fsm, state), If(start, fsm.next_state(fsm.RCV_ADDRESS)))
  176
+		for state in fsm.actions.keys():
  177
+			fsm.act(state, If(start, NextState("RCV_ADDRESS")))
29  milkymist/lasmicon/bankmachine.py
... ...
@@ -1,7 +1,7 @@
1 1
 from migen.fhdl.std import *
2 2
 from migen.bus.asmibus import *
3 3
 from migen.genlib.roundrobin import *
4  
-from migen.genlib.fsm import FSM
  4
+from migen.genlib.fsm import FSM, NextState
5 5
 from migen.genlib.misc import optree
6 6
 from migen.genlib.fifo import SyncFIFO
7 7
 
@@ -91,14 +91,13 @@ def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
91 91
 		]
92 92
 		
93 93
 		# Control and command generation FSM
94  
-		fsm = FSM("REGULAR", "PRECHARGE", "ACTIVATE", "REFRESH", delayed_enters=[
95  
-			("TRP", "ACTIVATE", timing_settings.tRP-1),
96  
-			("TRCD", "REGULAR", timing_settings.tRCD-1)
97  
-		])
  94
+		fsm = FSM()
98 95
 		self.submodules += fsm
99  
-		fsm.act(fsm.REGULAR,
  96
+		fsm.delayed_enter("TRP", "ACTIVATE", timing_settings.tRP-1)
  97
+		fsm.delayed_enter("TRCD", "REGULAR", timing_settings.tRCD-1)
  98
+		fsm.act("REGULAR",
100 99
 			If(self.refresh_req,
101  
-				fsm.next_state(fsm.REFRESH)
  100
+				NextState("REFRESH")
102 101
 			).Elif(self.req_fifo.readable,
103 102
 				If(has_openrow,
104 103
 					If(hit,
@@ -110,34 +109,34 @@ def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
110 109
 						self.cmd.cas_n.eq(0),
111 110
 						self.cmd.we_n.eq(~reqf.we)
112 111
 					).Else(
113  
-						fsm.next_state(fsm.PRECHARGE)
  112
+						NextState("PRECHARGE")
114 113
 					)
115 114
 				).Else(
116  
-					fsm.next_state(fsm.ACTIVATE)
  115
+					NextState("ACTIVATE")
117 116
 				)
118 117
 			)
119 118
 		)
120  
-		fsm.act(fsm.PRECHARGE,
  119
+		fsm.act("PRECHARGE",
121 120
 			# Notes:
122 121
 			# 1. we are presenting the column address, A10 is always low
123 122
 			# 2. since we always go to the ACTIVATE state, we do not need
124 123
 			# to assert track_close.
125 124
 			If(precharge_ok,
126 125
 				self.cmd.stb.eq(1),
127  
-				If(self.cmd.ack, fsm.next_state(fsm.TRP)),
  126
+				If(self.cmd.ack, NextState("TRP")),
128 127
 				self.cmd.ras_n.eq(0),
129 128
 				self.cmd.we_n.eq(0)
130 129
 			)
131 130
 		)
132  
-		fsm.act(fsm.ACTIVATE,
  131
+		fsm.act("ACTIVATE",
133 132
 			s_row_adr.eq(1),
134 133
 			track_open.eq(1),
135 134
 			self.cmd.stb.eq(1),
136  
-			If(self.cmd.ack, fsm.next_state(fsm.TRCD)),
  135
+			If(self.cmd.ack, NextState("TRCD")),
137 136
 			self.cmd.ras_n.eq(0)
138 137
 		)
139  
-		fsm.act(fsm.REFRESH,
  138
+		fsm.act("REFRESH",
140 139
 			self.refresh_gnt.eq(precharge_ok),
141 140
 			track_close.eq(1),
142  
-			If(~self.refresh_req, fsm.next_state(fsm.REGULAR))
  141
+			If(~self.refresh_req, NextState("REGULAR"))
143 142
 		)
28  milkymist/lasmicon/multiplexer.py
... ...
@@ -1,7 +1,7 @@
1 1
 from migen.fhdl.std import *
2 2
 from migen.genlib.roundrobin import *
3 3
 from migen.genlib.misc import optree
4  
-from migen.genlib.fsm import FSM
  4
+from migen.genlib.fsm import FSM, NextState
5 5
 from migen.bank.description import AutoCSR
6 6
 
7 7
 from milkymist.lasmicon.perf import Bandwidth
@@ -147,12 +147,11 @@ def anti_starvation(timeout):
147 147
 		]
148 148
 		
149 149
 		# Control FSM
150  
-		fsm = FSM("READ", "WRITE", "REFRESH", delayed_enters=[
151  
-			("RTW", "WRITE", timing_settings.read_latency-1),
152  
-			("WTR", "READ", timing_settings.tWTR-1)
153  
-		])
  150
+		fsm = FSM()
154 151
 		self.submodules += fsm
155  
-		fsm.act(fsm.READ,
  152
+		fsm.delayed_enter("RTW", "WRITE", timing_settings.read_latency-1)
  153
+		fsm.delayed_enter("WTR", "READ", timing_settings.tWTR-1)
  154
+		fsm.act("READ",
156 155
 			read_time_en.eq(1),
157 156
 			choose_req.want_reads.eq(1),
158 157
 			choose_cmd.cmd.ack.eq(1),
@@ -161,11 +160,11 @@ def anti_starvation(timeout):
161 160
 			steerer.sel[phy_settings.rdphase].eq(STEER_REQ),
162 161
 			If(write_available,
163 162
 				# TODO: switch only after several cycles of ~read_available?
164  
-				If(~read_available | max_read_time, fsm.next_state(fsm.RTW))
  163
+				If(~read_available | max_read_time, NextState("RTW"))
165 164
 			),
166  
-			If(go_to_refresh, fsm.next_state(fsm.REFRESH))
  165
+			If(go_to_refresh, NextState("REFRESH"))
167 166
 		)
168  
-		fsm.act(fsm.WRITE,
  167
+		fsm.act("WRITE",
169 168
 			write_time_en.eq(1),
170 169
 			choose_req.want_writes.eq(1),
171 170
 			choose_cmd.cmd.ack.eq(1),
@@ -173,15 +172,16 @@ def anti_starvation(timeout):
173 172
 			steerer.sel[1-phy_settings.wrphase].eq(STEER_CMD),
174 173
 			steerer.sel[phy_settings.wrphase].eq(STEER_REQ),
175 174
 			If(read_available,
176  
-				If(~write_available | max_write_time, fsm.next_state(fsm.WTR))
  175
+				If(~write_available | max_write_time, NextState("WTR"))
177 176
 			),
178  
-			If(go_to_refresh, fsm.next_state(fsm.REFRESH))
  177
+			If(go_to_refresh, NextState("REFRESH"))
179 178
 		)
180  
-		fsm.act(fsm.REFRESH,
  179
+		fsm.act("REFRESH",
181 180
 			steerer.sel[0].eq(STEER_REFRESH),
182  
-			If(~refresher.req, fsm.next_state(fsm.READ))
  181
+			If(~refresher.req, NextState("READ"))
183 182
 		)
184 183
 		# FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
185  
-		self.comb += refresher.ack.eq(fsm._state == fsm.REFRESH)
  184
+		fsm.finalize()
  185
+		self.comb += refresher.ack.eq(fsm.state == fsm.encoding["REFRESH"])
186 186
 
187 187
 		self.submodules.bandwidth = Bandwidth(choose_req.cmd)
12  milkymist/lasmicon/refresher.py
@@ -52,17 +52,17 @@ def __init__(self, a, ba, tRP, tREFI, tRFC):
52 52
 		]
53 53
 		
54 54
 		# Control FSM
55  
-		fsm = FSM("IDLE", "WAIT_GRANT", "WAIT_SEQ")
  55
+		fsm = FSM()
56 56
 		self.submodules += fsm
57  
-		fsm.act(fsm.IDLE, If(start, fsm.next_state(fsm.WAIT_GRANT)))
58  
-		fsm.act(fsm.WAIT_GRANT,
  57
+		fsm.act("IDLE", If(start, NextState("WAIT_GRANT")))
  58
+		fsm.act("WAIT_GRANT",
59 59
 			self.req.eq(1),
60 60
 			If(self.ack,
61 61
 				seq_start.eq(1),
62  
-				fsm.next_state(fsm.WAIT_SEQ)
  62
+				NextState("WAIT_SEQ")
63 63
 			)
64 64
 		)
65  
-		fsm.act(fsm.WAIT_SEQ,
  65
+		fsm.act("WAIT_SEQ",
66 66
 			self.req.eq(1),
67  
-			If(seq_done, fsm.next_state(fsm.IDLE))
  67
+			If(seq_done, NextState("IDLE"))
68 68
 		)

No commit comments for this range

Something went wrong with that request. Please try again.