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67  milkymist/framebuffer/__init__.py
... ...
@@ -1,45 +1,54 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.fhdl.specials import Instance
3 3
 from migen.fhdl.module import Module
  4
+from migen.genlib.record import Record
4 5
 from migen.flow.actor import *
5 6
 from migen.flow.network import *
6 7
 from migen.flow.transactions import *
7 8
 from migen.flow import plumbing
8 9
 from migen.actorlib import misc, dma_asmi, structuring, sim, spi
9 10
 
10  
-_hbits = 11
  11
+_hbits = 10
11 12
 _vbits = 11
12 13
 
13 14
 _bpp = 32
14 15
 _bpc = 10
15  
-_pixel_layout = [
  16
+_pixel_layout_s = [
16 17
 	("pad", _bpp-3*_bpc),
17 18
 	("r", _bpc),
18 19
 	("g", _bpc),
19 20
 	("b", _bpc)
20 21
 ]
  22
+_pixel_layout = [
  23
+	("p0", _pixel_layout_s),
  24
+	("p1", _pixel_layout_s)
  25
+]
21 26
 
22 27
 _bpc_dac = 8
  28
+_dac_layout_s = [
  29
+	("r", _bpc_dac),
  30
+	("g", _bpc_dac),
  31
+	("b", _bpc_dac)
  32
+]
23 33
 _dac_layout = [
24 34
 	("hsync", 1),
25 35
 	("vsync", 1),
26  
-	("r", _bpc_dac),
27  
-	("g", _bpc_dac),
28  
-	("b", _bpc_dac)	
  36
+	("p0", _dac_layout_s),
  37
+	("p1", _dac_layout_s)
29 38
 ]
30 39
 
31 40
 class _FrameInitiator(spi.SingleGenerator):
32 41
 	def __init__(self, asmi_bits, length_bits, alignment_bits):
33 42
 		layout = [
34  
-			("hres", _hbits, 640),
35  
-			("hsync_start", _hbits, 656),
36  
-			("hsync_end", _hbits, 752),
37  
-			("hscan", _hbits, 799),
  43
+			("hres", _hbits, 640, 1),
  44
+			("hsync_start", _hbits, 656, 1),
  45
+			("hsync_end", _hbits, 752, 1),
  46
+			("hscan", _hbits, 800, 1),
38 47
 			
39 48
 			("vres", _vbits, 480),
40 49
 			("vsync_start", _vbits, 492),
41 50
 			("vsync_end", _vbits, 494),
42  
-			("vscan", _vbits, 524),
  51
+			("vscan", _vbits, 525),
43 52
 			
44 53
 			("base", asmi_bits, 0, alignment_bits),
45 54
 			("length", length_bits, 640*480*4, alignment_bits)
@@ -74,9 +83,8 @@ def __init__(self):
74 83
 		self.comb += [
75 84
 			active.eq(hactive & vactive),
76 85
 			If(active,
77  
-				self.token("dac").r.eq(self.token("pixels").r[skip:]),
78  
-				self.token("dac").g.eq(self.token("pixels").g[skip:]),
79  
-				self.token("dac").b.eq(self.token("pixels").b[skip:])
  86
+				[getattr(getattr(self.token("dac"), p), c).eq(getattr(getattr(self.token("pixels"), p), c)[skip:])
  87
+					for p in ["p0", "p1"] for c in ["r", "g", "b"]]
80 88
 			),
81 89
 			
82 90
 			generate_en.eq(self.endpoints["timing"].stb & (~active | self.endpoints["pixels"].stb)),
@@ -122,9 +130,10 @@ def __init__(self):
122 130
 	
123 131
 		###
124 132
 
125  
-		data_width = 2+3*_bpc_dac
  133
+		data_width = 2+2*3*_bpc_dac
126 134
 		fifo_full = Signal()
127 135
 		fifo_write_en = Signal()
  136
+		fifo_read_en = Signal()
128 137
 		fifo_data_out = Signal(data_width)
129 138
 		fifo_data_in = Signal(data_width)
130 139
 		self.specials += Instance("asfifo",
@@ -133,7 +142,7 @@ def __init__(self):
133 142
 	
134 143
 			Instance.Output("data_out", fifo_data_out),
135 144
 			Instance.Output("empty"),
136  
-			Instance.Input("read_en", 1),
  145
+			Instance.Input("read_en", fifo_read_en),
137 146
 			Instance.Input("clk_read", ClockSignal("vga")),
138 147
 
139 148
 			Instance.Input("data_in", fifo_data_in),
@@ -142,17 +151,33 @@ def __init__(self):
142 151
 			Instance.Input("clk_write", ClockSignal()),
143 152
 			
144 153
 			Instance.Input("rst", 0))
145  
-		t = self.token("dac")
  154
+		fifo_in = self.token("dac")
  155
+		fifo_out = Record(_dac_layout)
146 156
 		self.comb += [
147  
-			Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(fifo_data_out),
148  
-			
149 157
 			self.endpoints["dac"].ack.eq(~fifo_full),
150 158
 			fifo_write_en.eq(self.endpoints["dac"].stb),
151  
-			fifo_data_in.eq(Cat(~t.hsync, ~t.vsync, t.r, t.g, t.b)),
152  
-			
  159
+			fifo_data_in.eq(Cat(*fifo_in.flatten())),
  160
+			Cat(*fifo_out.flatten()).eq(fifo_data_out),
153 161
 			self.busy.eq(0)
154 162
 		]
155 163
 
  164
+		pix_parity = Signal()
  165
+		self.sync.vga += [
  166
+			pix_parity.eq(~pix_parity),
  167
+			self.vga_hsync_n.eq(~fifo_out.hsync),
  168
+			self.vga_vsync_n.eq(~fifo_out.vsync),
  169
+			If(pix_parity,
  170
+				self.vga_r.eq(fifo_out.p1.r),
  171
+				self.vga_g.eq(fifo_out.p1.g),
  172
+				self.vga_b.eq(fifo_out.p1.b)
  173
+			).Else(
  174
+				self.vga_r.eq(fifo_out.p0.r),
  175
+				self.vga_g.eq(fifo_out.p0.g),
  176
+				self.vga_b.eq(fifo_out.p0.b)
  177
+			)
  178
+		]
  179
+		self.comb += fifo_read_en.eq(pix_parity)
  180
+
156 181
 def sim_fifo_gen():
157 182
 	while True:
158 183
 		t = Token("dac")
@@ -165,7 +190,7 @@ def __init__(self, pads, asmiport, simulation=False):
165 190
 		asmi_bits = asmiport.hub.aw
166 191
 		alignment_bits = bits_for(asmiport.hub.dw//8) - 1
167 192
 		length_bits = _hbits + _vbits + 2 - alignment_bits
168  
-		pack_factor = asmiport.hub.dw//_bpp
  193
+		pack_factor = asmiport.hub.dw//(2*_bpp)
169 194
 		packed_pixels = structuring.pack_layout(_pixel_layout, pack_factor)
170 195
 		
171 196
 		fi = _FrameInitiator(asmi_bits, length_bits, alignment_bits)
2  top.py
@@ -91,7 +91,7 @@ def __init__(self, platform):
91 91
 		#
92 92
 		self.submodules.asmicon = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing)
93 93
 		asmiport_wb = self.asmicon.hub.get_port()
94  
-		asmiport_fb = self.asmicon.hub.get_port(2)
  94
+		asmiport_fb = self.asmicon.hub.get_port(3)
95 95
 		self.asmicon.finalize()
96 96
 		
97 97
 		#
2  verilog/m1crg/m1crg.v
@@ -267,7 +267,7 @@ assign eth_tx_clk = eth_tx_clk_pad;
267 267
 DCM_CLKGEN #(
268 268
 	.CLKFXDV_DIVIDE(2),
269 269
 	.CLKFX_DIVIDE(4),
270  
-	.CLKFX_MD_MAX(2.0),
  270
+	.CLKFX_MD_MAX(3.0),
271 271
 	.CLKFX_MULTIPLY(2),
272 272
 	.CLKIN_PERIOD(20.0),
273 273
 	.SPREAD_SPECTRUM("NONE"),

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