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8  milkymist/dfii/__init__.py
@@ -13,7 +13,6 @@ def __init__(self, phase):
13 13
 	
14 14
 		###
15 15
 
16  
-		wrdata_en_adv = Signal()
17 16
 		self.comb += [
18 17
 			If(self._command_issue.re,
19 18
 				phase.cs_n.eq(~self._command.storage[0]),
@@ -28,15 +27,12 @@ def __init__(self, phase):
28 27
 			),
29 28
 			phase.address.eq(self._address.storage),
30 29
 			phase.bank.eq(self._baddress.storage),
31  
-			wrdata_en_adv.eq(self._command_issue.re & self._command.storage[4]),
  30
+			phase.wrdata_en.eq(self._command_issue.re & self._command.storage[4]),
32 31
 			phase.rddata_en.eq(self._command_issue.re & self._command.storage[5]),
33 32
 			phase.wrdata.eq(self._wrdata.storage),
34 33
 			phase.wrdata_mask.eq(0)
35 34
 		]
36  
-		self.sync += [
37  
-			phase.wrdata_en.eq(wrdata_en_adv),
38  
-			If(phase.rddata_valid, self._rddata.status.eq(phase.rddata))
39  
-		]
  35
+		self.sync += If(phase.rddata_valid, self._rddata.status.eq(phase.rddata))
40 36
 
41 37
 class DFIInjector(Module, AutoCSR):
42 38
 	def __init__(self, a, ba, d, nphases=1):
4  milkymist/lasmicon/__init__.py
@@ -48,8 +48,8 @@ def __init__(self, phy_settings, geom_settings, timing_settings):
48 48
 			aw=geom_settings.row_a + geom_settings.col_a - address_align,
49 49
 			dw=phy_settings.dfi_d*phy_settings.nphases,
50 50
 			nbanks=2**geom_settings.bank_a,
51  
-			read_latency=timing_settings.read_latency,
52  
-			write_latency=timing_settings.write_latency)
  51
+			read_latency=timing_settings.read_latency+1,
  52
+			write_latency=timing_settings.write_latency+1)
53 53
 		self.nrowbits = geom_settings.col_a - address_align
54 54
 	
55 55
 		###
4  milkymist/lasmicon/multiplexer.py
@@ -65,7 +65,6 @@ def stb_and(cmd, attr):
65 65
 			else:
66 66
 				return cmd.stb & getattr(cmd, attr)
67 67
 		for phase, sel in zip(dfi.phases, self.sel):
68  
-			wrdata_en_adv = Signal()
69 68
 			self.comb += [
70 69
 				phase.cke.eq(1),
71 70
 				phase.cs_n.eq(0)
@@ -77,8 +76,7 @@ def stb_and(cmd, attr):
77 76
 				phase.ras_n.eq(Array(cmd.ras_n for cmd in commands)[sel]),
78 77
 				phase.we_n.eq(Array(cmd.we_n for cmd in commands)[sel]),
79 78
 				phase.rddata_en.eq(Array(stb_and(cmd, "is_read") for cmd in commands)[sel]),
80  
-				wrdata_en_adv.eq(Array(stb_and(cmd, "is_write") for cmd in commands)[sel]),
81  
-				phase.wrdata_en.eq(wrdata_en_adv)
  79
+				phase.wrdata_en.eq(Array(stb_and(cmd, "is_write") for cmd in commands)[sel])
82 80
 			]
83 81
 
84 82
 class Multiplexer(Module):
4  top.py
@@ -44,8 +44,8 @@ def ns(t, margin=True):
44 44
 	tRFC=ns(70),
45 45
 	
46 46
 	CL=3,
47  
-	read_latency=5,
48  
-	write_latency=1,
  47
+	read_latency=4,
  48
+	write_latency=0,
49 49
 
50 50
 	read_time=32,
51 51
 	write_time=16
71  verilog/s6ddrphy/s6ddrphy.v
@@ -2,12 +2,12 @@
2 2
  * 1:2 frequency-ratio DDR PHY for Spartan-6
3 3
  *
4 4
  * Assert dfi_wrdata_en and present the data 
5  
- * on dfi_wrdata_mask/dfi_wrdata in the cycle
6  
- * immediately following the write command.
  5
+ * on dfi_wrdata_mask/dfi_wrdata in the same
  6
+ * cycle as the write command.
7 7
  *
8 8
  * Assert dfi_rddata_en in the same cycle as the read
9 9
  * command. The data will come back on dfi_rddata
10  
- * 5 cycles later, along with the assertion of
  10
+ * 4 cycles later, along with the assertion of
11 11
  * dfi_rddata_valid.
12 12
  *
13 13
  * This PHY only supports CAS Latency 3.
@@ -75,39 +75,6 @@ module s6ddrphy #(
75 75
  * Command/address
76 76
  */
77 77
 
78  
-reg [NUM_AD-1:0] r0_dfi_address_p0;
79  
-reg [NUM_BA-1:0] r0_dfi_bank_p0;
80  
-reg r0_dfi_cs_n_p0;
81  
-reg r0_dfi_cke_p0;
82  
-reg r0_dfi_ras_n_p0;
83  
-reg r0_dfi_cas_n_p0;
84  
-reg r0_dfi_we_n_p0;
85  
-reg [NUM_AD-1:0] r0_dfi_address_p1;
86  
-reg [NUM_BA-1:0] r0_dfi_bank_p1;
87  
-reg r0_dfi_cs_n_p1;
88  
-reg r0_dfi_cke_p1;
89  
-reg r0_dfi_ras_n_p1;
90  
-reg r0_dfi_cas_n_p1;
91  
-reg r0_dfi_we_n_p1;
92  
-	
93  
-always @(posedge sys_clk) begin
94  
-	r0_dfi_address_p0 <= dfi_address_p0;
95  
-	r0_dfi_bank_p0 <= dfi_bank_p0;
96  
-	r0_dfi_cs_n_p0 <= dfi_cs_n_p0;
97  
-	r0_dfi_cke_p0 <= dfi_cke_p0;
98  
-	r0_dfi_ras_n_p0 <= dfi_ras_n_p0;
99  
-	r0_dfi_cas_n_p0 <= dfi_cas_n_p0;
100  
-	r0_dfi_we_n_p0 <= dfi_we_n_p0;
101  
-	
102  
-	r0_dfi_address_p1 <= dfi_address_p1;
103  
-	r0_dfi_bank_p1 <= dfi_bank_p1;
104  
-	r0_dfi_cs_n_p1 <= dfi_cs_n_p1;
105  
-	r0_dfi_cke_p1 <= dfi_cke_p1;
106  
-	r0_dfi_ras_n_p1 <= dfi_ras_n_p1;
107  
-	r0_dfi_cas_n_p1 <= dfi_cas_n_p1;
108  
-	r0_dfi_we_n_p1 <= dfi_we_n_p1;
109  
-end
110  
-
111 78
 reg phase_sel;
112 79
 always @(posedge clk2x_270)
113 80
 	phase_sel <= sys_clk;
@@ -128,21 +95,21 @@ reg r_dfi_cas_n_p1;
128 95
 reg r_dfi_we_n_p1;
129 96
 	
130 97
 always @(posedge clk2x_270) begin
131  
-	r_dfi_address_p0 <= r0_dfi_address_p0;
132  
-	r_dfi_bank_p0 <= r0_dfi_bank_p0;
133  
-	r_dfi_cs_n_p0 <= r0_dfi_cs_n_p0;
134  
-	r_dfi_cke_p0 <= r0_dfi_cke_p0;
135  
-	r_dfi_ras_n_p0 <= r0_dfi_ras_n_p0;
136  
-	r_dfi_cas_n_p0 <= r0_dfi_cas_n_p0;
137  
-	r_dfi_we_n_p0 <= r0_dfi_we_n_p0;
  98
+	r_dfi_address_p0 <= dfi_address_p0;
  99
+	r_dfi_bank_p0 <= dfi_bank_p0;
  100
+	r_dfi_cs_n_p0 <= dfi_cs_n_p0;
  101
+	r_dfi_cke_p0 <= dfi_cke_p0;
  102
+	r_dfi_ras_n_p0 <= dfi_ras_n_p0;
  103
+	r_dfi_cas_n_p0 <= dfi_cas_n_p0;
  104
+	r_dfi_we_n_p0 <= dfi_we_n_p0;
138 105
 	
139  
-	r_dfi_address_p1 <= r0_dfi_address_p1;
140  
-	r_dfi_bank_p1 <= r0_dfi_bank_p1;
141  
-	r_dfi_cs_n_p1 <= r0_dfi_cs_n_p1;
142  
-	r_dfi_cke_p1 <= r0_dfi_cke_p1;
143  
-	r_dfi_ras_n_p1 <= r0_dfi_ras_n_p1;
144  
-	r_dfi_cas_n_p1 <= r0_dfi_cas_n_p1;
145  
-	r_dfi_we_n_p1 <= r0_dfi_we_n_p1;
  106
+	r_dfi_address_p1 <= dfi_address_p1;
  107
+	r_dfi_bank_p1 <= dfi_bank_p1;
  108
+	r_dfi_cs_n_p1 <= dfi_cs_n_p1;
  109
+	r_dfi_cke_p1 <= dfi_cke_p1;
  110
+	r_dfi_ras_n_p1 <= dfi_ras_n_p1;
  111
+	r_dfi_cas_n_p1 <= dfi_cas_n_p1;
  112
+	r_dfi_we_n_p1 <= dfi_we_n_p1;
146 113
 end
147 114
 
148 115
 always @(posedge clk2x_270) begin
@@ -367,10 +334,10 @@ end
367 334
 assign drive_dqs = r2_dfi_wrdata_en;
368 335
 
369 336
 wire rddata_valid;
370  
-reg [5:0] rddata_sr;
  337
+reg [4:0] rddata_sr;
371 338
 assign dfi_rddata_valid_w0 = rddata_sr[0];
372 339
 assign dfi_rddata_valid_w1 = rddata_sr[0];
373 340
 always @(posedge sys_clk)
374  
-	rddata_sr <= {dfi_rddata_en_p0, rddata_sr[5:1]};
  341
+	rddata_sr <= {dfi_rddata_en_p0, rddata_sr[4:1]};
375 342
 
376 343
 endmodule

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