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  • 2 commits
  • 5 files changed
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  • 1 contributor
View
8 milkymist/dfii/__init__.py
@@ -13,7 +13,6 @@ def __init__(self, phase):
###
- wrdata_en_adv = Signal()
self.comb += [
If(self._command_issue.re,
phase.cs_n.eq(~self._command.storage[0]),
@@ -28,15 +27,12 @@ def __init__(self, phase):
),
phase.address.eq(self._address.storage),
phase.bank.eq(self._baddress.storage),
- wrdata_en_adv.eq(self._command_issue.re & self._command.storage[4]),
+ phase.wrdata_en.eq(self._command_issue.re & self._command.storage[4]),
phase.rddata_en.eq(self._command_issue.re & self._command.storage[5]),
phase.wrdata.eq(self._wrdata.storage),
phase.wrdata_mask.eq(0)
]
- self.sync += [
- phase.wrdata_en.eq(wrdata_en_adv),
- If(phase.rddata_valid, self._rddata.status.eq(phase.rddata))
- ]
+ self.sync += If(phase.rddata_valid, self._rddata.status.eq(phase.rddata))
class DFIInjector(Module, AutoCSR):
def __init__(self, a, ba, d, nphases=1):
View
4 milkymist/lasmicon/__init__.py
@@ -48,8 +48,8 @@ def __init__(self, phy_settings, geom_settings, timing_settings):
aw=geom_settings.row_a + geom_settings.col_a - address_align,
dw=phy_settings.dfi_d*phy_settings.nphases,
nbanks=2**geom_settings.bank_a,
- read_latency=timing_settings.read_latency,
- write_latency=timing_settings.write_latency)
+ read_latency=timing_settings.read_latency+1,
+ write_latency=timing_settings.write_latency+1)
self.nrowbits = geom_settings.col_a - address_align
###
View
4 milkymist/lasmicon/multiplexer.py
@@ -65,7 +65,6 @@ def stb_and(cmd, attr):
else:
return cmd.stb & getattr(cmd, attr)
for phase, sel in zip(dfi.phases, self.sel):
- wrdata_en_adv = Signal()
self.comb += [
phase.cke.eq(1),
phase.cs_n.eq(0)
@@ -77,8 +76,7 @@ def stb_and(cmd, attr):
phase.ras_n.eq(Array(cmd.ras_n for cmd in commands)[sel]),
phase.we_n.eq(Array(cmd.we_n for cmd in commands)[sel]),
phase.rddata_en.eq(Array(stb_and(cmd, "is_read") for cmd in commands)[sel]),
- wrdata_en_adv.eq(Array(stb_and(cmd, "is_write") for cmd in commands)[sel]),
- phase.wrdata_en.eq(wrdata_en_adv)
+ phase.wrdata_en.eq(Array(stb_and(cmd, "is_write") for cmd in commands)[sel])
]
class Multiplexer(Module):
View
4 top.py
@@ -44,8 +44,8 @@ def ns(t, margin=True):
tRFC=ns(70),
CL=3,
- read_latency=5,
- write_latency=1,
+ read_latency=4,
+ write_latency=0,
read_time=32,
write_time=16
View
71 verilog/s6ddrphy/s6ddrphy.v
@@ -2,12 +2,12 @@
* 1:2 frequency-ratio DDR PHY for Spartan-6
*
* Assert dfi_wrdata_en and present the data
- * on dfi_wrdata_mask/dfi_wrdata in the cycle
- * immediately following the write command.
+ * on dfi_wrdata_mask/dfi_wrdata in the same
+ * cycle as the write command.
*
* Assert dfi_rddata_en in the same cycle as the read
* command. The data will come back on dfi_rddata
- * 5 cycles later, along with the assertion of
+ * 4 cycles later, along with the assertion of
* dfi_rddata_valid.
*
* This PHY only supports CAS Latency 3.
@@ -75,39 +75,6 @@ module s6ddrphy #(
* Command/address
*/
-reg [NUM_AD-1:0] r0_dfi_address_p0;
-reg [NUM_BA-1:0] r0_dfi_bank_p0;
-reg r0_dfi_cs_n_p0;
-reg r0_dfi_cke_p0;
-reg r0_dfi_ras_n_p0;
-reg r0_dfi_cas_n_p0;
-reg r0_dfi_we_n_p0;
-reg [NUM_AD-1:0] r0_dfi_address_p1;
-reg [NUM_BA-1:0] r0_dfi_bank_p1;
-reg r0_dfi_cs_n_p1;
-reg r0_dfi_cke_p1;
-reg r0_dfi_ras_n_p1;
-reg r0_dfi_cas_n_p1;
-reg r0_dfi_we_n_p1;
-
-always @(posedge sys_clk) begin
- r0_dfi_address_p0 <= dfi_address_p0;
- r0_dfi_bank_p0 <= dfi_bank_p0;
- r0_dfi_cs_n_p0 <= dfi_cs_n_p0;
- r0_dfi_cke_p0 <= dfi_cke_p0;
- r0_dfi_ras_n_p0 <= dfi_ras_n_p0;
- r0_dfi_cas_n_p0 <= dfi_cas_n_p0;
- r0_dfi_we_n_p0 <= dfi_we_n_p0;
-
- r0_dfi_address_p1 <= dfi_address_p1;
- r0_dfi_bank_p1 <= dfi_bank_p1;
- r0_dfi_cs_n_p1 <= dfi_cs_n_p1;
- r0_dfi_cke_p1 <= dfi_cke_p1;
- r0_dfi_ras_n_p1 <= dfi_ras_n_p1;
- r0_dfi_cas_n_p1 <= dfi_cas_n_p1;
- r0_dfi_we_n_p1 <= dfi_we_n_p1;
-end
-
reg phase_sel;
always @(posedge clk2x_270)
phase_sel <= sys_clk;
@@ -128,21 +95,21 @@ reg r_dfi_cas_n_p1;
reg r_dfi_we_n_p1;
always @(posedge clk2x_270) begin
- r_dfi_address_p0 <= r0_dfi_address_p0;
- r_dfi_bank_p0 <= r0_dfi_bank_p0;
- r_dfi_cs_n_p0 <= r0_dfi_cs_n_p0;
- r_dfi_cke_p0 <= r0_dfi_cke_p0;
- r_dfi_ras_n_p0 <= r0_dfi_ras_n_p0;
- r_dfi_cas_n_p0 <= r0_dfi_cas_n_p0;
- r_dfi_we_n_p0 <= r0_dfi_we_n_p0;
+ r_dfi_address_p0 <= dfi_address_p0;
+ r_dfi_bank_p0 <= dfi_bank_p0;
+ r_dfi_cs_n_p0 <= dfi_cs_n_p0;
+ r_dfi_cke_p0 <= dfi_cke_p0;
+ r_dfi_ras_n_p0 <= dfi_ras_n_p0;
+ r_dfi_cas_n_p0 <= dfi_cas_n_p0;
+ r_dfi_we_n_p0 <= dfi_we_n_p0;
- r_dfi_address_p1 <= r0_dfi_address_p1;
- r_dfi_bank_p1 <= r0_dfi_bank_p1;
- r_dfi_cs_n_p1 <= r0_dfi_cs_n_p1;
- r_dfi_cke_p1 <= r0_dfi_cke_p1;
- r_dfi_ras_n_p1 <= r0_dfi_ras_n_p1;
- r_dfi_cas_n_p1 <= r0_dfi_cas_n_p1;
- r_dfi_we_n_p1 <= r0_dfi_we_n_p1;
+ r_dfi_address_p1 <= dfi_address_p1;
+ r_dfi_bank_p1 <= dfi_bank_p1;
+ r_dfi_cs_n_p1 <= dfi_cs_n_p1;
+ r_dfi_cke_p1 <= dfi_cke_p1;
+ r_dfi_ras_n_p1 <= dfi_ras_n_p1;
+ r_dfi_cas_n_p1 <= dfi_cas_n_p1;
+ r_dfi_we_n_p1 <= dfi_we_n_p1;
end
always @(posedge clk2x_270) begin
@@ -367,10 +334,10 @@ end
assign drive_dqs = r2_dfi_wrdata_en;
wire rddata_valid;
-reg [5:0] rddata_sr;
+reg [4:0] rddata_sr;
assign dfi_rddata_valid_w0 = rddata_sr[0];
assign dfi_rddata_valid_w1 = rddata_sr[0];
always @(posedge sys_clk)
- rddata_sr <= {dfi_rddata_en_p0, rddata_sr[5:1]};
+ rddata_sr <= {dfi_rddata_en_p0, rddata_sr[4:1]};
endmodule

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