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  • 5 commits
  • 7 files changed
  • 0 commit comments
  • 1 contributor
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20 milkymist/dvisampler/clocking.py
@@ -13,9 +13,9 @@ def __init__(self):
self.locked = Signal()
self.serdesstrobe = Signal()
- self._cd_pix = ClockDomain()
- self._cd_pix5x = ClockDomain()
- self._cd_pix20x = ClockDomain()
+ self.clock_domains._cd_pix = ClockDomain()
+ self.clock_domains._cd_pix5x = ClockDomain()
+ self.clock_domains._cd_pix20x = ClockDomain()
###
@@ -27,9 +27,9 @@ def __init__(self):
self.specials += Instance("PLL_BASE",
Instance.Parameter("CLKIN_PERIOD", 22.0),
Instance.Parameter("CLKFBOUT_MULT", 20),
- Instance.Parameter("CLKOUT0_DIVIDE", 20), # pix
+ Instance.Parameter("CLKOUT0_DIVIDE", 1), # pix20x
Instance.Parameter("CLKOUT1_DIVIDE", 4), # pix5x
- Instance.Parameter("CLKOUT2_DIVIDE", 1), # pix20x
+ Instance.Parameter("CLKOUT2_DIVIDE", 20), # pix
Instance.Parameter("COMPENSATION", "INTERNAL"),
Instance.Output("CLKFBOUT", clkfbout),
@@ -42,14 +42,10 @@ def __init__(self):
Instance.Input("RST", self._r_pll_reset.field.r)
)
- self.specials += Instance("BUFG",
- Instance.Input("I", pll_clk0), Instance.Output("O", self._cd_pix.clk))
- self.specials += Instance("BUFG",
- Instance.Input("I", pll_clk1), Instance.Output("O", self._cd_pix5x.clk))
locked_async = Signal()
self.specials += Instance("BUFPLL",
Instance.Parameter("DIVIDE", 4),
- Instance.Input("PLLIN", pll_clk2),
+ Instance.Input("PLLIN", pll_clk0),
Instance.ClockPort("GCLK", "pix5x"),
Instance.Input("LOCKED", pll_locked),
Instance.Output("IOCLK", self._cd_pix20x.clk),
@@ -58,3 +54,7 @@ def __init__(self):
)
self.specials += MultiReg(locked_async, self.locked, "sys")
self.comb += self._r_locked.field.w.eq(self.locked)
+ self.specials += Instance("BUFG",
+ Instance.Input("I", pll_clk1), Instance.Output("O", self._cd_pix5x.clk))
+ self.specials += Instance("BUFG",
+ Instance.Input("I", pll_clk2), Instance.Output("O", self._cd_pix.clk))
View
8 milkymist/dvisampler/datacapture.py
@@ -24,16 +24,18 @@ def __init__(self, ntbits, debug=False):
delay_ce = Signal()
delay_rst = Signal()
delay_init = Signal()
- self.specials += Instance("IDELAY2",
+ self.specials += Instance("IODELAY2",
Instance.Parameter("DELAY_SRC", "IDATAIN"),
Instance.Parameter("IDELAY_TYPE", "VARIABLE_FROM_ZERO"),
- Instance.Parameter("COUNTER_WRAP_AROUND", "STAY_AT_LIMIT"),
+ Instance.Parameter("COUNTER_WRAPAROUND", "STAY_AT_LIMIT"),
+ Instance.Parameter("DATA_RATE", "SDR"),
Instance.Input("IDATAIN", self.pad),
Instance.Output("DATAOUT", pad_delayed),
Instance.Input("INC", delay_inc | delay_init),
Instance.Input("CE", delay_ce | delay_init),
Instance.Input("RST", delay_rst),
Instance.ClockPort("CLK"),
+ Instance.ClockPort("IOCLK0", "pix20x"),
Instance.Input("CAL", 0),
Instance.Input("T", 1)
)
@@ -119,7 +121,7 @@ def __init__(self, ntbits, debug=False):
if debug:
self.comb += delay_rst.eq(self.delay_rst | self._r_delay_rst.re)
current_tap = self._r_current_tap.field.w
- If(delay_rst,
+ self.sync += If(delay_rst,
current_tap.eq(0)
).Elif(delay_ce,
If(delay_inc,
View
4 milkymist/framebuffer/__init__.py
@@ -134,12 +134,12 @@ def __init__(self):
Instance.Output("data_out", fifo_data_out),
Instance.Output("empty"),
Instance.Input("read_en", 1),
- Instance.ClockPort("clk_read", "vga"),
+ Instance.Input("clk_read", ClockSignal("vga")),
Instance.Input("data_in", fifo_data_in),
Instance.Output("full", fifo_full),
Instance.Input("write_en", fifo_write_en),
- Instance.ClockPort("clk_write"),
+ Instance.Input("clk_write", ClockSignal()),
Instance.Input("rst", 0))
t = self.token("dac")
View
4 milkymist/lm32/__init__.py
@@ -15,8 +15,8 @@ def __init__(self):
i_adr_o = Signal(32)
d_adr_o = Signal(32)
self.specials += Instance("lm32_top",
- Instance.ClockPort("clk_i"),
- Instance.ResetPort("rst_i"),
+ Instance.Input("clk_i", ClockSignal()),
+ Instance.Input("rst_i", ResetSignal()),
Instance.Input("interrupt", self.interrupt),
#Instance.Input("ext_break", self.ext_break),
View
8 milkymist/minimac3/__init__.py
@@ -61,8 +61,8 @@ def __init__(self):
rx_pending_1_r.eq(rx_pending_1)
]
self.specials += Instance("minimac3",
- Instance.ClockPort("sys_clk"),
- Instance.ResetPort("sys_rst"),
+ Instance.Input("sys_clk", ClockSignal()),
+ Instance.Input("sys_rst", ResetSignal()),
Instance.Output("rx_done_0", self.ev.rx0.trigger),
Instance.Output("rx_count_0", self._rx_count_0.field.w),
@@ -84,11 +84,11 @@ def __init__(self):
Instance.Output("wb_dat_o", self.membus.dat_r),
Instance.Output("wb_ack_o", self.membus.ack),
- Instance.ClockPort("phy_tx_clk", "eth_tx"),
+ Instance.Input("phy_tx_clk", ClockSignal("eth_tx")),
Instance.Output("phy_tx_data", self.phy_tx_data),
Instance.Output("phy_tx_en", self.phy_tx_en),
Instance.Output("phy_tx_er", self.phy_tx_er),
- Instance.ClockPort("phy_rx_clk", "eth_rx"),
+ Instance.Input("phy_rx_clk", ClockSignal("eth_rx")),
Instance.Input("phy_rx_data", self.phy_rx_data),
Instance.Input("phy_dv", self.phy_dv),
Instance.Input("phy_rx_er", self.phy_rx_er),
View
8 milkymist/s6ddrphy/__init__.py
@@ -9,10 +9,10 @@ def __init__(self, a, ba, d):
Instance.Parameter("NUM_AD", a),
Instance.Parameter("NUM_BA", ba),
Instance.Parameter("NUM_D", d),
- Instance.ClockPort("sys_clk"),
- Instance.ClockPort("clk2x_270", "sys2x_270"),
- Instance.ClockPort("clk4x_wr", "sys4x_wr"),
- Instance.ClockPort("clk4x_rd", "sys4x_rd")
+ Instance.Input("sys_clk", ClockSignal()),
+ Instance.Input("clk2x_270", ClockSignal("sys2x_270")),
+ Instance.Input("clk4x_wr", ClockSignal("sys4x_wr")),
+ Instance.Input("clk4x_rd", ClockSignal("sys4x_rd"))
]
for name, width, cl in [
("clk4x_wr_strb", 1, Instance.Input),
View
2  verilog/m1crg/m1crg.v
@@ -263,7 +263,7 @@ DCM_CLKGEN #(
.CLKFX_DIVIDE(4),
.CLKFX_MD_MAX(2.0),
.CLKFX_MULTIPLY(2),
- .CLKIN_PERIOD(0.0),
+ .CLKIN_PERIOD(20.0),
.SPREAD_SPECTRUM("NONE"),
.STARTUP_WAIT("FALSE")
) vga_clock_gen (

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