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  • 7 files changed
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20  milkymist/dvisampler/clocking.py
@@ -13,9 +13,9 @@ def __init__(self):
13 13
 
14 14
 		self.locked = Signal()
15 15
 		self.serdesstrobe = Signal()
16  
-		self._cd_pix = ClockDomain()
17  
-		self._cd_pix5x = ClockDomain()
18  
-		self._cd_pix20x = ClockDomain()
  16
+		self.clock_domains._cd_pix = ClockDomain()
  17
+		self.clock_domains._cd_pix5x = ClockDomain()
  18
+		self.clock_domains._cd_pix20x = ClockDomain()
19 19
 
20 20
 		###
21 21
 
@@ -27,9 +27,9 @@ def __init__(self):
27 27
 		self.specials += Instance("PLL_BASE",
28 28
 			Instance.Parameter("CLKIN_PERIOD", 22.0),
29 29
 			Instance.Parameter("CLKFBOUT_MULT", 20),
30  
-			Instance.Parameter("CLKOUT0_DIVIDE", 20), # pix
  30
+			Instance.Parameter("CLKOUT0_DIVIDE", 1),  # pix20x
31 31
 			Instance.Parameter("CLKOUT1_DIVIDE", 4),  # pix5x
32  
-			Instance.Parameter("CLKOUT2_DIVIDE", 1),  # pix20x
  32
+			Instance.Parameter("CLKOUT2_DIVIDE", 20), # pix
33 33
 			Instance.Parameter("COMPENSATION", "INTERNAL"),
34 34
 
35 35
 			Instance.Output("CLKFBOUT", clkfbout),
@@ -42,14 +42,10 @@ def __init__(self):
42 42
 			Instance.Input("RST", self._r_pll_reset.field.r)
43 43
 		)
44 44
 
45  
-		self.specials += Instance("BUFG",
46  
-			Instance.Input("I", pll_clk0), Instance.Output("O", self._cd_pix.clk))
47  
-		self.specials += Instance("BUFG",
48  
-			Instance.Input("I", pll_clk1), Instance.Output("O", self._cd_pix5x.clk))
49 45
 		locked_async = Signal()
50 46
 		self.specials += Instance("BUFPLL",
51 47
 			Instance.Parameter("DIVIDE", 4),
52  
-			Instance.Input("PLLIN", pll_clk2),
  48
+			Instance.Input("PLLIN", pll_clk0),
53 49
 			Instance.ClockPort("GCLK", "pix5x"),
54 50
 			Instance.Input("LOCKED", pll_locked),
55 51
 			Instance.Output("IOCLK", self._cd_pix20x.clk),
@@ -58,3 +54,7 @@ def __init__(self):
58 54
 		)
59 55
 		self.specials += MultiReg(locked_async, self.locked, "sys")
60 56
 		self.comb += self._r_locked.field.w.eq(self.locked)
  57
+		self.specials += Instance("BUFG",
  58
+			Instance.Input("I", pll_clk1), Instance.Output("O", self._cd_pix5x.clk))
  59
+		self.specials += Instance("BUFG",
  60
+			Instance.Input("I", pll_clk2), Instance.Output("O", self._cd_pix.clk))
8  milkymist/dvisampler/datacapture.py
@@ -24,16 +24,18 @@ def __init__(self, ntbits, debug=False):
24 24
 		delay_ce = Signal()
25 25
 		delay_rst = Signal()
26 26
 		delay_init = Signal()
27  
-		self.specials += Instance("IDELAY2",
  27
+		self.specials += Instance("IODELAY2",
28 28
 			Instance.Parameter("DELAY_SRC", "IDATAIN"),
29 29
 			Instance.Parameter("IDELAY_TYPE", "VARIABLE_FROM_ZERO"),
30  
-			Instance.Parameter("COUNTER_WRAP_AROUND", "STAY_AT_LIMIT"),
  30
+			Instance.Parameter("COUNTER_WRAPAROUND", "STAY_AT_LIMIT"),
  31
+			Instance.Parameter("DATA_RATE", "SDR"),
31 32
 			Instance.Input("IDATAIN", self.pad),
32 33
 			Instance.Output("DATAOUT", pad_delayed),
33 34
 			Instance.Input("INC", delay_inc | delay_init),
34 35
 			Instance.Input("CE", delay_ce | delay_init),
35 36
 			Instance.Input("RST", delay_rst),
36 37
 			Instance.ClockPort("CLK"),
  38
+			Instance.ClockPort("IOCLK0", "pix20x"),
37 39
 			Instance.Input("CAL", 0),
38 40
 			Instance.Input("T", 1)
39 41
 		)
@@ -119,7 +121,7 @@ def __init__(self, ntbits, debug=False):
119 121
 		if debug:
120 122
 			self.comb += delay_rst.eq(self.delay_rst | self._r_delay_rst.re)
121 123
 			current_tap = self._r_current_tap.field.w
122  
-			If(delay_rst,
  124
+			self.sync += If(delay_rst,
123 125
 				current_tap.eq(0)
124 126
 			).Elif(delay_ce,
125 127
 				If(delay_inc,
4  milkymist/framebuffer/__init__.py
@@ -134,12 +134,12 @@ def __init__(self):
134 134
 			Instance.Output("data_out", fifo_data_out),
135 135
 			Instance.Output("empty"),
136 136
 			Instance.Input("read_en", 1),
137  
-			Instance.ClockPort("clk_read", "vga"),
  137
+			Instance.Input("clk_read", ClockSignal("vga")),
138 138
 
139 139
 			Instance.Input("data_in", fifo_data_in),
140 140
 			Instance.Output("full", fifo_full),
141 141
 			Instance.Input("write_en", fifo_write_en),
142  
-			Instance.ClockPort("clk_write"),
  142
+			Instance.Input("clk_write", ClockSignal()),
143 143
 			
144 144
 			Instance.Input("rst", 0))
145 145
 		t = self.token("dac")
4  milkymist/lm32/__init__.py
@@ -15,8 +15,8 @@ def __init__(self):
15 15
 		i_adr_o = Signal(32)
16 16
 		d_adr_o = Signal(32)
17 17
 		self.specials += Instance("lm32_top",
18  
-			Instance.ClockPort("clk_i"),
19  
-			Instance.ResetPort("rst_i"),
  18
+			Instance.Input("clk_i", ClockSignal()),
  19
+			Instance.Input("rst_i", ResetSignal()),
20 20
 			
21 21
 			Instance.Input("interrupt", self.interrupt),
22 22
 			#Instance.Input("ext_break", self.ext_break),
8  milkymist/minimac3/__init__.py
@@ -61,8 +61,8 @@ def __init__(self):
61 61
 			rx_pending_1_r.eq(rx_pending_1)
62 62
 		]
63 63
 		self.specials += Instance("minimac3",
64  
-				Instance.ClockPort("sys_clk"),
65  
-				Instance.ResetPort("sys_rst"),
  64
+				Instance.Input("sys_clk", ClockSignal()),
  65
+				Instance.Input("sys_rst", ResetSignal()),
66 66
 
67 67
 				Instance.Output("rx_done_0", self.ev.rx0.trigger),
68 68
 				Instance.Output("rx_count_0", self._rx_count_0.field.w),
@@ -84,11 +84,11 @@ def __init__(self):
84 84
 				Instance.Output("wb_dat_o", self.membus.dat_r),
85 85
 				Instance.Output("wb_ack_o", self.membus.ack),
86 86
 				
87  
-				Instance.ClockPort("phy_tx_clk", "eth_tx"),
  87
+				Instance.Input("phy_tx_clk", ClockSignal("eth_tx")),
88 88
 				Instance.Output("phy_tx_data", self.phy_tx_data),
89 89
 				Instance.Output("phy_tx_en", self.phy_tx_en),
90 90
 				Instance.Output("phy_tx_er", self.phy_tx_er),
91  
-				Instance.ClockPort("phy_rx_clk", "eth_rx"),
  91
+				Instance.Input("phy_rx_clk", ClockSignal("eth_rx")),
92 92
 				Instance.Input("phy_rx_data", self.phy_rx_data),
93 93
 				Instance.Input("phy_dv", self.phy_dv),
94 94
 				Instance.Input("phy_rx_er", self.phy_rx_er),
8  milkymist/s6ddrphy/__init__.py
@@ -9,10 +9,10 @@ def __init__(self, a, ba, d):
9 9
 			Instance.Parameter("NUM_AD", a),
10 10
 			Instance.Parameter("NUM_BA", ba),
11 11
 			Instance.Parameter("NUM_D", d),
12  
-			Instance.ClockPort("sys_clk"),
13  
-			Instance.ClockPort("clk2x_270", "sys2x_270"),
14  
-			Instance.ClockPort("clk4x_wr", "sys4x_wr"),
15  
-			Instance.ClockPort("clk4x_rd", "sys4x_rd")
  12
+			Instance.Input("sys_clk", ClockSignal()),
  13
+			Instance.Input("clk2x_270", ClockSignal("sys2x_270")),
  14
+			Instance.Input("clk4x_wr", ClockSignal("sys4x_wr")),
  15
+			Instance.Input("clk4x_rd", ClockSignal("sys4x_rd"))
16 16
 		]
17 17
 		for name, width, cl in [
18 18
 			("clk4x_wr_strb", 1, Instance.Input),
2  verilog/m1crg/m1crg.v
@@ -263,7 +263,7 @@ DCM_CLKGEN #(
263 263
 	.CLKFX_DIVIDE(4),
264 264
 	.CLKFX_MD_MAX(2.0),
265 265
 	.CLKFX_MULTIPLY(2),
266  
-	.CLKIN_PERIOD(0.0),
  266
+	.CLKIN_PERIOD(20.0),
267 267
 	.SPREAD_SPECTRUM("NONE"),
268 268
 	.STARTUP_WAIT("FALSE")
269 269
 ) vga_clock_gen (

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