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41  tb/asmicon/common.py
... ...
@@ -0,0 +1,41 @@
  1
+from migen.fhdl.structure import *
  2
+from migen.sim.generic import Proxy
  3
+
  4
+class CommandLogger:
  5
+	def __init__(self, cmd):
  6
+		self.cmd = cmd
  7
+	
  8
+	def do_simulation(self, s):
  9
+		elts = ["@" + str(s.cycle_counter)]
  10
+		
  11
+		cmdp = Proxy(s, self.cmd)
  12
+		if not cmdp.ras_n and cmdp.cas_n and cmdp.we_n:
  13
+			elts.append("ACTIVATE")
  14
+			elts.append("BANK " + str(cmdp.ba))
  15
+			elts.append("ROW " + str(cmdp.a))
  16
+		elif cmdp.ras_n and not cmdp.cas_n and cmdp.we_n:
  17
+			elts.append("READ\t")
  18
+			elts.append("BANK " + str(cmdp.ba))
  19
+			elts.append("COL " + str(cmdp.a))
  20
+		elif cmdp.ras_n and not cmdp.cas_n and not cmdp.we_n:
  21
+			elts.append("WRITE\t")
  22
+			elts.append("BANK " + str(cmdp.ba))
  23
+			elts.append("COL " + str(cmdp.a))
  24
+		elif cmdp.ras_n and cmdp.cas_n and not cmdp.we_n:
  25
+			elts.append("BST")
  26
+		elif not cmdp.ras_n and not cmdp.cas_n and cmdp.we_n:
  27
+			elts.append("AUTO REFRESH")
  28
+		elif not cmdp.ras_n and cmdp.cas_n and not cmdp.we_n:
  29
+			elts.append("PRECHARGE")
  30
+			if cmdp.a & 2**10:
  31
+				elts.append("ALL")
  32
+			else:
  33
+				elts.append("BANK " + str(cmdp.ba))
  34
+		elif not cmdp.ras_n and not cmdp.cas_n and not cmdp.we_n:
  35
+			elts.append("LMR")
  36
+		
  37
+		if len(elts) > 1:
  38
+			print("\t".join(elts))
  39
+	
  40
+	def get_fragment(self):
  41
+		return Fragment(sim=[self.do_simulation])
50  tb/asmicon/refresher.py
... ...
@@ -0,0 +1,50 @@
  1
+from random import Random
  2
+
  3
+from migen.fhdl.structure import *
  4
+from migen.sim.generic import Simulator, TopLevel
  5
+from migen.sim.icarus import Runner
  6
+
  7
+from milkymist.asmicon.refresher import *
  8
+
  9
+from common import CommandLogger
  10
+
  11
+class Granter:
  12
+	def __init__(self, req, ack):
  13
+		self.req = req
  14
+		self.ack = ack
  15
+		self.state = 0
  16
+		self.prng = Random(92837)
  17
+	
  18
+	def do_simulation(self, s):
  19
+		elts = ["@" + str(s.cycle_counter)]
  20
+		
  21
+		if self.state == 0:
  22
+			if s.rd(self.req):
  23
+				elts.append("Refresher requested access")
  24
+				self.state = 1
  25
+		elif self.state == 1:
  26
+			if self.prng.randrange(0, 5) == 0:
  27
+				elts.append("Granted access to refresher")
  28
+				s.wr(self.ack, 1)
  29
+				self.state = 2
  30
+		elif self.state == 2:
  31
+			if not s.rd(self.req):
  32
+				elts.append("Refresher released access")
  33
+				s.wr(self.ack, 0)
  34
+				self.state = 0
  35
+			
  36
+		if len(elts) > 1:
  37
+			print("\t".join(elts))
  38
+	
  39
+	def get_fragment(self):
  40
+		return Fragment(sim=[self.do_simulation])
  41
+
  42
+def main():
  43
+	dut = Refresher(13, 2, tRP=3, tREFI=100, tRFC=5)
  44
+	logger = CommandLogger(dut.cmd)
  45
+	granter = Granter(dut.req, dut.ack)
  46
+	fragment = dut.get_fragment() + logger.get_fragment() + granter.get_fragment()
  47
+	sim = Simulator(fragment, Runner())
  48
+	sim.run(400)
  49
+
  50
+main()
20  tb/norflash/Makefile
... ...
@@ -1,20 +0,0 @@
1  
-SOURCES=tb_norflash.v norflash.v
2  
-
3  
-all: tb_norflash
4  
-
5  
-isim: tb_norflash
6  
-	./tb_norflash
7  
-
8  
-cversim: $(SOURCES)
9  
-	cver $(SOURCES)
10  
-
11  
-norflash.v: norflash_conv.py
12  
-	python3 norflash_conv.py > norflash.v
13  
-
14  
-clean:
15  
-	rm -f tb_norflash verilog.log norflash.vcd norflash.v
16  
-
17  
-tb_norflash: $(SOURCES)
18  
-	iverilog -o tb_norflash $(SOURCES)
19  
-
20  
-.PHONY: clean sim cversim
10  tb/norflash/norflash_conv.py
... ...
@@ -1,10 +0,0 @@
1  
-from migen.fhdl import verilog
2  
-from migen.bus import wishbone
3  
-
4  
-from milkymist import norflash
5  
-
6  
-norflash0 = norflash.Inst(25, 12)
7  
-frag = norflash0.get_fragment()
8  
-v = verilog.convert(frag, name="norflash",
9  
-	ios={norflash0.bus.cyc_i, norflash0.bus.stb_i, norflash0.bus.we_i, norflash0.bus.adr_i, norflash0.bus.sel_i, norflash0.bus.dat_i, norflash0.bus.dat_o, norflash0.bus.ack_o})
10  
-print(v)
129  tb/norflash/tb_norflash.v
... ...
@@ -1,129 +0,0 @@
1  
-/*
2  
- * Milkymist SoC
3  
- * Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
4  
- *
5  
- * This program is free software: you can redistribute it and/or modify
6  
- * it under the terms of the GNU General Public License as published by
7  
- * the Free Software Foundation, version 3 of the License.
8  
- *
9  
- * This program is distributed in the hope that it will be useful,
10  
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  
- * GNU General Public License for more details.
13  
- *
14  
- * You should have received a copy of the GNU General Public License
15  
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16  
- */
17  
-
18  
-`timescale 1ns / 1ps
19  
-
20  
-module tb_norflash();
21  
-
22  
-reg sys_clk;
23  
-reg sys_rst;
24  
-
25  
-reg [31:0] wb_adr_i;
26  
-wire [31:0] wb_dat_o;
27  
-reg wb_cyc_i;
28  
-reg wb_stb_i;
29  
-wire wb_ack_o;
30  
-reg [3:0] wb_sel_i;
31  
-
32  
-wire [23:0] flash_adr;
33  
-wire [15:0] flash_d;
34  
-reg [15:0] flash_do;
35  
-
36  
-always @(flash_adr) #110 flash_do <= flash_adr[15:0] + 16'b1;
37  
-
38  
-norflash dut(
39  
-	.sys_clk(sys_clk),
40  
-	.sys_rst(sys_rst),
41  
-
42  
-	.wishbone_norflash_adr_i(wb_adr_i),
43  
-	.wishbone_norflash_dat_o(wb_dat_o),
44  
-	.wishbone_norflash_cyc_i(wb_cyc_i),
45  
-	.wishbone_norflash_stb_i(wb_stb_i),
46  
-	.wishbone_norflash_ack_o(wb_ack_o),
47  
-	.wishbone_norflash_sel_i(wb_sel_i),
48  
-
49  
-	.norflash_adr(flash_adr),
50  
-	.norflash_d(flash_d),
51  
-	.norflash_oe_n(flash_oe_n),
52  
-	.norflash_we_n(flash_we_n)
53  
-);
54  
-
55  
-//assign flash_d = flash_oe_n ? 16'bz : flash_do;
56  
-assign flash_d = flash_do;
57  
-
58  
-task wbread;
59  
-	input [31:0] address;
60  
-	integer i;
61  
-	begin
62  
-		wb_adr_i <= address;
63  
-		wb_cyc_i <= 1'b1;
64  
-		wb_stb_i <= 1'b1;
65  
-		
66  
-		i = 1;
67  
-		while(~wb_ack_o) begin
68  
-			#5 sys_clk <= 1'b1;
69  
-			#5 sys_clk <= 1'b0;
70  
-			i = i + 1;
71  
-		end
72  
-		
73  
-		$display("Read address %h completed in %d cycles, result %h", address, i, wb_dat_o);
74  
-		
75  
-		wb_cyc_i <= 1'b0;
76  
-		wb_stb_i <= 1'b0;
77  
-		
78  
-		/* Let the core release its ack */
79  
-		#5 sys_clk <= 1'b1;
80  
-		#5 sys_clk <= 1'b0;
81  
-	end
82  
-endtask
83  
-
84  
-initial begin
85  
-	$dumpfile("norflash.vcd");
86  
-	$dumpvars(1, dut);
87  
-
88  
-	sys_rst <= 1'b1;
89  
-	sys_clk <= 1'b0;
90  
-	
91  
-	wb_adr_i <= 32'h00000000;
92  
-	wb_cyc_i <= 1'b0;
93  
-	wb_stb_i <= 1'b0;
94  
-	wb_sel_i <= 4'b1111;
95  
-
96  
-	#5 sys_clk <= 1'b1;
97  
-	#5 sys_clk <= 1'b0;
98  
-	
99  
-	sys_rst <= 1'b0;
100  
-	#5 sys_clk <= 1'b1;
101  
-	#5 sys_clk <= 1'b0;
102  
-	
103  
-	wbread(32'h00000000);
104  
-	wbread(32'h00000004);
105  
-
106  
-	wb_sel_i = 4'b0010;
107  
-	wbread(32'h0000fff1);
108  
-
109  
-	wb_sel_i = 4'b0100;
110  
-	wbread(32'h0000fff2);
111  
-
112  
-	wb_sel_i = 4'b1000;
113  
-	wbread(32'h0000fff3);
114  
-
115  
-	wb_sel_i = 4'b0100;
116  
-	wbread(32'h0000fff0);
117  
-
118  
-	wb_sel_i = 4'b1111;
119  
-	wbread(32'h00000010);
120  
-	#5 sys_clk = 1'b1;
121  
-	#5 sys_clk = 1'b0;
122  
-	#5 sys_clk = 1'b1;
123  
-	#5 sys_clk = 1'b0;
124  
-	wbread(32'h00000040);
125  
-	
126  
-	$finish;
127  
-end
128  
-
129  
-endmodule

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