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41 tb/asmicon/common.py
@@ -0,0 +1,41 @@
+from migen.fhdl.structure import *
+from migen.sim.generic import Proxy
+
+class CommandLogger:
+ def __init__(self, cmd):
+ self.cmd = cmd
+
+ def do_simulation(self, s):
+ elts = ["@" + str(s.cycle_counter)]
+
+ cmdp = Proxy(s, self.cmd)
+ if not cmdp.ras_n and cmdp.cas_n and cmdp.we_n:
+ elts.append("ACTIVATE")
+ elts.append("BANK " + str(cmdp.ba))
+ elts.append("ROW " + str(cmdp.a))
+ elif cmdp.ras_n and not cmdp.cas_n and cmdp.we_n:
+ elts.append("READ\t")
+ elts.append("BANK " + str(cmdp.ba))
+ elts.append("COL " + str(cmdp.a))
+ elif cmdp.ras_n and not cmdp.cas_n and not cmdp.we_n:
+ elts.append("WRITE\t")
+ elts.append("BANK " + str(cmdp.ba))
+ elts.append("COL " + str(cmdp.a))
+ elif cmdp.ras_n and cmdp.cas_n and not cmdp.we_n:
+ elts.append("BST")
+ elif not cmdp.ras_n and not cmdp.cas_n and cmdp.we_n:
+ elts.append("AUTO REFRESH")
+ elif not cmdp.ras_n and cmdp.cas_n and not cmdp.we_n:
+ elts.append("PRECHARGE")
+ if cmdp.a & 2**10:
+ elts.append("ALL")
+ else:
+ elts.append("BANK " + str(cmdp.ba))
+ elif not cmdp.ras_n and not cmdp.cas_n and not cmdp.we_n:
+ elts.append("LMR")
+
+ if len(elts) > 1:
+ print("\t".join(elts))
+
+ def get_fragment(self):
+ return Fragment(sim=[self.do_simulation])
View
50 tb/asmicon/refresher.py
@@ -0,0 +1,50 @@
+from random import Random
+
+from migen.fhdl.structure import *
+from migen.sim.generic import Simulator, TopLevel
+from migen.sim.icarus import Runner
+
+from milkymist.asmicon.refresher import *
+
+from common import CommandLogger
+
+class Granter:
+ def __init__(self, req, ack):
+ self.req = req
+ self.ack = ack
+ self.state = 0
+ self.prng = Random(92837)
+
+ def do_simulation(self, s):
+ elts = ["@" + str(s.cycle_counter)]
+
+ if self.state == 0:
+ if s.rd(self.req):
+ elts.append("Refresher requested access")
+ self.state = 1
+ elif self.state == 1:
+ if self.prng.randrange(0, 5) == 0:
+ elts.append("Granted access to refresher")
+ s.wr(self.ack, 1)
+ self.state = 2
+ elif self.state == 2:
+ if not s.rd(self.req):
+ elts.append("Refresher released access")
+ s.wr(self.ack, 0)
+ self.state = 0
+
+ if len(elts) > 1:
+ print("\t".join(elts))
+
+ def get_fragment(self):
+ return Fragment(sim=[self.do_simulation])
+
+def main():
+ dut = Refresher(13, 2, tRP=3, tREFI=100, tRFC=5)
+ logger = CommandLogger(dut.cmd)
+ granter = Granter(dut.req, dut.ack)
+ fragment = dut.get_fragment() + logger.get_fragment() + granter.get_fragment()
+ sim = Simulator(fragment, Runner())
+ sim.run(400)
+
+main()
View
20 tb/norflash/Makefile
@@ -1,20 +0,0 @@
-SOURCES=tb_norflash.v norflash.v
-
-all: tb_norflash
-
-isim: tb_norflash
- ./tb_norflash
-
-cversim: $(SOURCES)
- cver $(SOURCES)
-
-norflash.v: norflash_conv.py
- python3 norflash_conv.py > norflash.v
-
-clean:
- rm -f tb_norflash verilog.log norflash.vcd norflash.v
-
-tb_norflash: $(SOURCES)
- iverilog -o tb_norflash $(SOURCES)
-
-.PHONY: clean sim cversim
View
10 tb/norflash/norflash_conv.py
@@ -1,10 +0,0 @@
-from migen.fhdl import verilog
-from migen.bus import wishbone
-
-from milkymist import norflash
-
-norflash0 = norflash.Inst(25, 12)
-frag = norflash0.get_fragment()
-v = verilog.convert(frag, name="norflash",
- ios={norflash0.bus.cyc_i, norflash0.bus.stb_i, norflash0.bus.we_i, norflash0.bus.adr_i, norflash0.bus.sel_i, norflash0.bus.dat_i, norflash0.bus.dat_o, norflash0.bus.ack_o})
-print(v)
View
129 tb/norflash/tb_norflash.v
@@ -1,129 +0,0 @@
-/*
- * Milkymist SoC
- * Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-`timescale 1ns / 1ps
-
-module tb_norflash();
-
-reg sys_clk;
-reg sys_rst;
-
-reg [31:0] wb_adr_i;
-wire [31:0] wb_dat_o;
-reg wb_cyc_i;
-reg wb_stb_i;
-wire wb_ack_o;
-reg [3:0] wb_sel_i;
-
-wire [23:0] flash_adr;
-wire [15:0] flash_d;
-reg [15:0] flash_do;
-
-always @(flash_adr) #110 flash_do <= flash_adr[15:0] + 16'b1;
-
-norflash dut(
- .sys_clk(sys_clk),
- .sys_rst(sys_rst),
-
- .wishbone_norflash_adr_i(wb_adr_i),
- .wishbone_norflash_dat_o(wb_dat_o),
- .wishbone_norflash_cyc_i(wb_cyc_i),
- .wishbone_norflash_stb_i(wb_stb_i),
- .wishbone_norflash_ack_o(wb_ack_o),
- .wishbone_norflash_sel_i(wb_sel_i),
-
- .norflash_adr(flash_adr),
- .norflash_d(flash_d),
- .norflash_oe_n(flash_oe_n),
- .norflash_we_n(flash_we_n)
-);
-
-//assign flash_d = flash_oe_n ? 16'bz : flash_do;
-assign flash_d = flash_do;
-
-task wbread;
- input [31:0] address;
- integer i;
- begin
- wb_adr_i <= address;
- wb_cyc_i <= 1'b1;
- wb_stb_i <= 1'b1;
-
- i = 1;
- while(~wb_ack_o) begin
- #5 sys_clk <= 1'b1;
- #5 sys_clk <= 1'b0;
- i = i + 1;
- end
-
- $display("Read address %h completed in %d cycles, result %h", address, i, wb_dat_o);
-
- wb_cyc_i <= 1'b0;
- wb_stb_i <= 1'b0;
-
- /* Let the core release its ack */
- #5 sys_clk <= 1'b1;
- #5 sys_clk <= 1'b0;
- end
-endtask
-
-initial begin
- $dumpfile("norflash.vcd");
- $dumpvars(1, dut);
-
- sys_rst <= 1'b1;
- sys_clk <= 1'b0;
-
- wb_adr_i <= 32'h00000000;
- wb_cyc_i <= 1'b0;
- wb_stb_i <= 1'b0;
- wb_sel_i <= 4'b1111;
-
- #5 sys_clk <= 1'b1;
- #5 sys_clk <= 1'b0;
-
- sys_rst <= 1'b0;
- #5 sys_clk <= 1'b1;
- #5 sys_clk <= 1'b0;
-
- wbread(32'h00000000);
- wbread(32'h00000004);
-
- wb_sel_i = 4'b0010;
- wbread(32'h0000fff1);
-
- wb_sel_i = 4'b0100;
- wbread(32'h0000fff2);
-
- wb_sel_i = 4'b1000;
- wbread(32'h0000fff3);
-
- wb_sel_i = 4'b0100;
- wbread(32'h0000fff0);
-
- wb_sel_i = 4'b1111;
- wbread(32'h00000010);
- #5 sys_clk = 1'b1;
- #5 sys_clk = 1'b0;
- #5 sys_clk = 1'b1;
- #5 sys_clk = 1'b0;
- wbread(32'h00000040);
-
- $finish;
-end
-
-endmodule

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