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  1. 3  build.py
3  build.py
@@ -18,6 +18,8 @@ def main():
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 """, clk50=platform.lookup_request("clk50"))
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 	platform.add_platform_command("""
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+INST "m1crg/pll" LOC="PLL_ADV_X0Y1";
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+INST "m1crg/vga_clock_gen" LOC="DCM_X0Y6";
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 INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
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 INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
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@@ -50,6 +52,7 @@ def main():
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 NET "{dviclk0}" CLOCK_DEDICATED_ROUTE = FALSE;
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 TIMESPEC "TSdviclk0" = PERIOD "GRPdviclk0" 26.7 ns HIGH 50%;
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 """, dviclk0=platform.lookup_request("dvi_in", 0).clk)
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+	if hasattr(soc, "dvisampler1"):
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 		platform.add_platform_command("""
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 NET "{dviclk1}" TNM_NET = "GRPdviclk1";
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 NET "{dviclk1}" CLOCK_DEDICATED_ROUTE = FALSE;

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