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25  milkymist/dvisampler/__init__.py
@@ -6,6 +6,7 @@
6 6
 from milkymist.dvisampler.clocking import Clocking
7 7
 from milkymist.dvisampler.datacapture import DataCapture
8 8
 from milkymist.dvisampler.charsync import CharSync
  9
+from milkymist.dvisampler.decoding import Decoding
9 10
 from milkymist.dvisampler.chansync import ChanSync
10 11
 
11 12
 class DVISampler(Module, AutoReg):
@@ -36,11 +37,25 @@ def __init__(self, inversions=""):
36 37
 			setattr(self.submodules, name + "_charsync", charsync)
37 38
 			self.comb += charsync.raw_data.eq(cap.d)
38 39
 
  40
+			decoding = Decoding()
  41
+			setattr(self.submodules, name + "_decod", decoding)
  42
+			self.comb += [
  43
+				decoding.valid_i.eq(charsync.synced),
  44
+				decoding.input.eq(charsync.data)
  45
+			]
  46
+
39 47
 		self.submodules.chansync = ChanSync()
40 48
 		self.comb += [
41  
-			self.chansync.char_synced.eq(self.data0_charsync.synced & \
42  
-			  self.data1_charsync.synced & self.data2_charsync.synced),
43  
-			self.chansync.data_in0.eq(self.data0_charsync.data),
44  
-			self.chansync.data_in1.eq(self.data1_charsync.data),
45  
-			self.chansync.data_in2.eq(self.data2_charsync.data),
  49
+			self.chansync.valid_i.eq(self.data0_decod.valid_o & \
  50
+			  self.data1_decod.valid_o & self.data2_decod.valid_o),
  51
+			self.chansync.data_in0.eq(self.data0_decod.output),
  52
+			self.chansync.data_in1.eq(self.data1_decod.output),
  53
+			self.chansync.data_in2.eq(self.data2_decod.output),
46 54
 		]
  55
+
  56
+		de = self.chansync.data_out0.de
  57
+		r = self.chansync.data_out2.d
  58
+		g = self.chansync.data_out1.d
  59
+		b = self.chansync.data_out0.d
  60
+		hsync = self.chansync.data_out0.c[0]
  61
+		vsync = self.chansync.data_out0.c[1]
21  milkymist/dvisampler/chansync.py
@@ -2,14 +2,15 @@
2 2
 from migen.fhdl.module import Module
3 3
 from migen.genlib.cdc import MultiReg
4 4
 from migen.genlib.fifo import SyncFIFO
  5
+from migen.genlib.record import Record
5 6
 from migen.genlib.misc import optree
6 7
 from migen.bank.description import *
7 8
 
8  
-_control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011]
  9
+from milkymist.dvisampler.common import channel_layout
9 10
 
10 11
 class ChanSync(Module, AutoReg):
11 12
 	def __init__(self, nchan=3, depth=8):
12  
-		self.char_synced = Signal()
  13
+		self.valid_i = Signal()
13 14
 		self.chan_synced = Signal()
14 15
 
15 16
 		self._r_channels_synced = RegisterField(1, READ_ONLY, WRITE_ONLY)
@@ -18,10 +19,10 @@ def __init__(self, nchan=3, depth=8):
18 19
 		all_control_starts = Signal()
19 20
 		for i in range(nchan):
20 21
 			name = "data_in" + str(i)
21  
-			data_in = Signal(10, name=name)
  22
+			data_in = Record(channel_layout, name=name)
22 23
 			setattr(self, name, data_in)
23 24
 			name = "data_out" + str(i)
24  
-			data_out = Signal(10, name=name)
  25
+			data_out = Record(channel_layout, name=name)
25 26
 			setattr(self, name, data_out)
26 27
 
27 28
 			###
@@ -29,23 +30,23 @@ def __init__(self, nchan=3, depth=8):
29 30
 			fifo = SyncFIFO(10, depth)
30 31
 			self.add_submodule(fifo, "pix")
31 32
 			self.comb += [
32  
-				fifo.we.eq(self.char_synced),
33  
-				fifo.din.eq(data_in),
34  
-				data_out.eq(fifo.dout)
  33
+				fifo.we.eq(self.valid_i),
  34
+				fifo.din.eq(Cat(*data_in.flatten())),
  35
+				Cat(*data_out.flatten()).eq(fifo.dout)
35 36
 			]
36 37
 			is_control = Signal()
37 38
 			is_control_r = Signal()
38  
-			self.sync.pix += If(fifo.re, is_control_r.eq(is_control))
  39
+			self.sync.pix += If(fifo.readable & fifo.re, is_control_r.eq(is_control))
39 40
 			control_starts = Signal()
40 41
 			self.comb += [
41  
-				is_control.eq(optree("|", [data_out == t for t in _control_tokens])),
  42
+				is_control.eq(~data_out.de),
42 43
 				control_starts.eq(is_control & ~is_control_r),
43 44
 				fifo.re.eq(~is_control | all_control_starts)
44 45
 			]
45 46
 			lst_control_starts.append(control_starts)
46 47
 
47 48
 		self.comb += all_control_starts.eq(optree("&", lst_control_starts))
48  
-		self.sync.pix += If(~self.char_synced,
  49
+		self.sync.pix += If(~self.valid_i,
49 50
 				self.chan_synced.eq(0)
50 51
 			).Elif(all_control_starts, self.chan_synced.eq(1))
51 52
 		self.specials += MultiReg(self.chan_synced, self._r_channels_synced.field.w)
4  milkymist/dvisampler/charsync.py
@@ -4,7 +4,7 @@
4 4
 from migen.genlib.misc import optree
5 5
 from migen.bank.description import *
6 6
 
7  
-_control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011]
  7
+from milkymist.dvisampler.common import control_tokens
8 8
 
9 9
 class CharSync(Module, AutoReg):
10 10
 	def __init__(self, required_controls=8):
@@ -24,7 +24,7 @@ def __init__(self, required_controls=8):
24 24
 		found_control = Signal()
25 25
 		control_position = Signal(max=10)
26 26
 		for i in range(10):
27  
-			self.sync.pix += If(optree("|", [raw[i:i+10] == t for t in _control_tokens]),
  27
+			self.sync.pix += If(optree("|", [raw[i:i+10] == t for t in control_tokens]),
28 28
 			  	found_control.eq(1),
29 29
 			  	control_position.eq(i)
30 30
 			)
2  milkymist/dvisampler/common.py
... ...
@@ -0,0 +1,2 @@
  1
+control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011]
  2
+channel_layout = [("d", 8), ("c", 2), ("de", 1)]
25  milkymist/dvisampler/decoding.py
... ...
@@ -0,0 +1,25 @@
  1
+from migen.fhdl.structure import *
  2
+from migen.fhdl.module import Module
  3
+from migen.genlib.record import Record
  4
+
  5
+from milkymist.dvisampler.common import control_tokens, channel_layout
  6
+
  7
+class Decoding(Module):
  8
+	def __init__(self):
  9
+		self.valid_i = Signal()
  10
+		self.input = Signal(10)
  11
+		self.valid_o = Signal()
  12
+		self.output = Record(channel_layout)
  13
+
  14
+		###
  15
+
  16
+		self.sync.pix += self.output.de.eq(1)
  17
+		for i, t in enumerate(control_tokens):
  18
+			self.sync.pix += If(self.input == t,
  19
+				self.output.de.eq(0),
  20
+				self.output.c.eq(i)
  21
+			)
  22
+		self.sync.pix += self.output.d[0].eq(self.input[0] ^ self.input[9])
  23
+		for i in range(1, 8):
  24
+			self.sync.pix += self.output.d[i].eq(self.input[i] ^ self.input[i-1] ^ ~self.input[8])
  25
+		self.sync.pix += self.valid_o.eq(self.valid_i)

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