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1  milkymist/lasmicon/bankmachine.py
... ...
@@ -1,5 +1,4 @@
1 1
 from migen.fhdl.std import *
2  
-from migen.bus.asmibus import *
3 2
 from migen.genlib.roundrobin import *
4 3
 from migen.genlib.fsm import FSM, NextState
5 4
 from migen.genlib.misc import optree
38  tb/asmicon/asmicon.py
... ...
@@ -1,38 +0,0 @@
1  
-from migen.fhdl.std import *
2  
-from migen.bus.asmibus import *
3  
-from migen.sim.generic import Simulator, TopLevel
4  
-
5  
-from milkymist.asmicon import *
6  
-
7  
-from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
8  
-
9  
-def my_generator_r():
10  
-	for x in range(50):
11  
-		t = TRead(x)
12  
-		yield t
13  
-	print("reads done")
14  
-
15  
-def my_generator_w():
16  
-	for x in range(50):
17  
-		t = TWrite(x, x)
18  
-		yield t
19  
-	print("writes done")
20  
-
21  
-def main():
22  
-	dut = ASMIcon(sdram_phy, sdram_geom, sdram_timing)
23  
-	initiator1 = Initiator(my_generator_r(), dut.hub.get_port())
24  
-	initiator2 = Initiator(my_generator_w(), dut.hub.get_port())
25  
-	dut.finalize()
26  
-	
27  
-	logger = DFILogger(dut.dfi)
28  
-	
29  
-	def end_simulation(s):
30  
-		s.interrupt = initiator1.done and initiator2.done
31  
-	
32  
-	fragment = dut.get_fragment() + initiator1.get_fragment() + initiator2.get_fragment() + \
33  
-		logger.get_fragment() + \
34  
-		Fragment(sim=[end_simulation])
35  
-	sim = Simulator(fragment, TopLevel("my.vcd"))
36  
-	sim.run(700)
37  
-
38  
-main()
46  tb/asmicon/asmicon_wb.py
... ...
@@ -1,46 +0,0 @@
1  
-from migen.fhdl.std import *
2  
-from migen.bus import wishbone, wishbone2asmi, asmibus
3  
-from migen.sim.generic import Simulator, TopLevel
4  
-
5  
-from milkymist.asmicon import *
6  
-
7  
-from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
8  
-
9  
-l2_size = 8192 # in bytes
10  
-
11  
-def my_generator():
12  
-	for x in range(20):
13  
-		t = TWrite(x, x)
14  
-		yield t
15  
-		print(str(t) + " delay=" + str(t.latency))
16  
-	for x in range(20):
17  
-		t = TRead(x)
18  
-		yield t
19  
-		print(str(t) + " delay=" + str(t.latency))
20  
-	for x in range(20):
21  
-		t = TRead(x+l2_size//4)
22  
-		yield t
23  
-		print(str(t) + " delay=" + str(t.latency))
24  
-
25  
-def main():
26  
-	controller = ASMIcon(sdram_phy, sdram_geom, sdram_timing)
27  
-	bridge = wishbone2asmi.WB2ASMI(l2_size//4, controller.hub.get_port())
28  
-	controller.finalize()
29  
-	initiator = wishbone.Initiator(my_generator())
30  
-	conn = wishbone.InterconnectPointToPoint(initiator.bus, bridge.wishbone)
31  
-	
32  
-	logger = DFILogger(controller.dfi)
33  
-	
34  
-	def end_simulation(s):
35  
-		s.interrupt = initiator.done
36  
-	
37  
-	fragment = controller.get_fragment() + \
38  
-		bridge.get_fragment() + \
39  
-		initiator.get_fragment() + \
40  
-		conn.get_fragment() + \
41  
-		logger.get_fragment() + \
42  
-		Fragment(sim=[end_simulation])
43  
-	sim = Simulator(fragment, TopLevel("my.vcd"))
44  
-	sim.run()
45  
-
46  
-main()
47  tb/asmicon/bankmachine.py
... ...
@@ -1,47 +0,0 @@
1  
-from migen.fhdl.std import *
2  
-from migen.bus.asmibus import *
3  
-from migen.sim.generic import Simulator, TopLevel
4  
-
5  
-from milkymist.asmicon.bankmachine import *
6  
-
7  
-from common import sdram_geom, sdram_timing, CommandLogger
8  
-
9  
-def my_generator():
10  
-	for x in range(10):
11  
-		t = TWrite(x)
12  
-		yield t
13  
-	for x in range(10):
14  
-		t = TWrite(x + 2200)
15  
-		yield t
16  
-
17  
-class Completer:
18  
-	def __init__(self, hub, cmd):
19  
-		self.hub = hub
20  
-		self.cmd = cmd
21  
-		
22  
-	def get_fragment(self):
23  
-		sync = [
24  
-			self.hub.call.eq(self.cmd.stb & self.cmd.ack & (self.cmd.is_read | self.cmd.is_write)),
25  
-			self.hub.tag_call.eq(self.cmd.tag)
26  
-		]
27  
-		return Fragment(sync=sync)
28  
-
29  
-def main():
30  
-	hub = Hub(12, 128, 2)
31  
-	initiator = Initiator(hub.get_port(), my_generator())
32  
-	hub.finalize()
33  
-	
34  
-	dut = BankMachine(sdram_geom, sdram_timing, 2, 0, hub.get_slots())
35  
-	logger = CommandLogger(dut.cmd, True)
36  
-	completer = Completer(hub, dut.cmd)
37  
-	
38  
-	def end_simulation(s):
39  
-		s.interrupt = initiator.done
40  
-	
41  
-	fragment = hub.get_fragment() + initiator.get_fragment() + \
42  
-		dut.get_fragment() + logger.get_fragment() + completer.get_fragment() + \
43  
-		Fragment(sim=[end_simulation])
44  
-	sim = Simulator(fragment, TopLevel("my.vcd"))
45  
-	sim.run()
46  
-
47  
-main()
76  tb/asmicon/selector.py
... ...
@@ -1,76 +0,0 @@
1  
-from random import Random
2  
-
3  
-from migen.fhdl.std import *
4  
-from migen.bus.asmibus import *
5  
-from migen.sim.generic import Simulator, TopLevel
6  
-
7  
-from milkymist.asmicon.bankmachine import _AddressSlicer, _SimpleSelector
8  
-
9  
-from common import SlotsLogger, sdram_geom
10  
-
11  
-def my_generator(dt, offset):
12  
-	for t in range(dt):
13  
-		yield None
14  
-	for x in range(10):
15  
-		t = TRead(x + offset)
16  
-		yield t
17  
-
18  
-class Selector:
19  
-	def __init__(self, slicer, bankn, slots):
20  
-		self.selector = _SimpleSelector(slicer, bankn, slots)
21  
-		self.queue = []
22  
-		self.prng = Random(876)
23  
-	
24  
-	def do_simulation(self, s):
25  
-		if self.prng.randrange(0, 5):
26  
-			s.wr(self.selector.ack, 1)
27  
-		else:
28  
-			s.wr(self.selector.ack, 0)
29  
-		if s.rd(self.selector.stb) and s.rd(self.selector.ack):
30  
-			tag = s.rd(self.selector.tag)
31  
-			self.queue.append(tag)
32  
-			print("==> SELECTED: " + str(tag))
33  
-		print("")
34  
-	
35  
-	def get_fragment(self):
36  
-		return self.selector.get_fragment() + \
37  
-			Fragment(sim=[self.do_simulation])
38  
-
39  
-class Completer:
40  
-	def __init__(self, hub, queue):
41  
-		self.hub = hub
42  
-		self.queue = queue
43  
-	
44  
-	def do_simulation(self, s):
45  
-		if self.queue:
46  
-			tag = self.queue.pop()
47  
-			s.wr(self.hub.call, 1)
48  
-			s.wr(self.hub.tag_call, tag)
49  
-		else:
50  
-			s.wr(self.hub.call, 0)
51  
-		
52  
-	def get_fragment(self):
53  
-		return Fragment(sim=[self.do_simulation])
54  
-
55  
-def main():
56  
-	hub = Hub(12, 128, 8)
57  
-	initiators = [Initiator(hub.get_port(), my_generator(0, 2200*(i//6)+i*10))
58  
-		for i in range(8)]
59  
-	hub.finalize()
60  
-	
61  
-	slots = hub.get_slots()
62  
-	slicer = _AddressSlicer(sdram_geom, 2)
63  
-	logger = SlotsLogger(slicer, slots)
64  
-	selector = Selector(slicer, 0, slots)
65  
-	completer = Completer(hub, selector.queue)
66  
-	
67  
-	def end_simulation(s):
68  
-		s.interrupt = all([i.done for i in initiators])
69  
-	
70  
-	fragment = hub.get_fragment() + sum([i.get_fragment() for i in initiators], Fragment()) + \
71  
-		logger.get_fragment() + selector.get_fragment() + completer.get_fragment() + \
72  
-		Fragment(sim=[end_simulation])
73  
-	sim = Simulator(fragment, TopLevel("my.vcd"))
74  
-	sim.run()
75  
-
76  
-main()
44  tb/lasmicon/bankmachine.py
... ...
@@ -0,0 +1,44 @@
  1
+from migen.fhdl.std import *
  2
+from migen.bus.lasmibus import *
  3
+from migen.sim.generic import Simulator, TopLevel
  4
+
  5
+from milkymist.lasmicon.bankmachine import *
  6
+
  7
+from common import sdram_geom, sdram_timing, CommandLogger
  8
+
  9
+def my_generator():
  10
+	for x in range(10):
  11
+		yield True, x
  12
+	for x in range(10):
  13
+		yield False, 128*x
  14
+
  15
+class TB(Module):
  16
+	def __init__(self):
  17
+		self.req = Interface(32, 32, 1,
  18
+			sdram_timing.req_queue_size, sdram_timing.read_latency, sdram_timing.write_latency)
  19
+		self.submodules.dut = BankMachine(sdram_geom, sdram_timing, 2, 0, self.req)
  20
+		self.submodules.logger = CommandLogger(self.dut.cmd, True)
  21
+		self.generator = my_generator()
  22
+		self.dat_ack_cnt = 0
  23
+
  24
+	def do_simulation(self, s):
  25
+		if s.rd(self.req.dat_ack):
  26
+			self.dat_ack_cnt += 1
  27
+		if s.rd(self.req.req_ack):
  28
+			try:
  29
+				we, adr = next(self.generator)
  30
+			except StopIteration:
  31
+				s.wr(self.req.stb, 0)
  32
+				if not s.rd(self.req.lock):
  33
+					s.interrupt = True
  34
+					print("data ack count: {0}".format(self.dat_ack_cnt))
  35
+				return
  36
+			s.wr(self.req.adr, adr)
  37
+			s.wr(self.req.we, we)
  38
+			s.wr(self.req.stb, 1)
  39
+
  40
+def main():	
  41
+	sim = Simulator(TB(), TopLevel("my.vcd"))
  42
+	sim.run()
  43
+
  44
+main()
63  tb/asmicon/common.py → tb/lasmicon/common.py
@@ -4,7 +4,7 @@
4 4
 from migen.fhdl.std import *
5 5
 from migen.sim.generic import Proxy
6 6
 
7  
-from milkymist import asmicon
  7
+from milkymist import lasmicon
8 8
 
9 9
 MHz = 1000000
10 10
 clk_freq = (83 + Fraction(1, 3))*MHz
@@ -15,28 +15,31 @@ def ns(t, margin=True):
15 15
 		t += clk_period_ns/2
16 16
 	return ceil(t/clk_period_ns)
17 17
 
18  
-sdram_phy = asmicon.PhySettings(
  18
+sdram_phy = lasmicon.PhySettings(
  19
+	type="DDR",
19 20
 	dfi_d=64, 
20 21
 	nphases=2,
21 22
 	rdphase=0,
22  
-	wrphase=1
  23
+	wrphase=1,
  24
+	cl=3
23 25
 )
24  
-sdram_geom = asmicon.GeomSettings(
  26
+sdram_geom = lasmicon.GeomSettings(
25 27
 	bank_a=2,
26 28
 	row_a=13,
27 29
 	col_a=10
28 30
 )
29  
-sdram_timing = asmicon.TimingSettings(
  31
+sdram_timing = lasmicon.TimingSettings(
30 32
 	tRP=ns(15),
31 33
 	tRCD=ns(15),
32 34
 	tWR=ns(15),
  35
+	tWTR=2,
33 36
 	tREFI=ns(7800, False),
34 37
 	tRFC=ns(70),
35 38
 	
36  
-	CL=3,
37  
-	rd_delay=4,
  39
+	read_latency=5,
  40
+	write_latency=0,
38 41
 
39  
-	slot_time=16,
  42
+	req_queue_size=8,
40 43
 	read_time=32,
41 44
 	write_time=16
42 45
 )
@@ -69,10 +72,11 @@ def decode_sdram(ras_n, cas_n, we_n, bank, address):
69 72
 		elts.append("LMR")
70 73
 	return elts
71 74
 
72  
-class CommandLogger:
  75
+class CommandLogger(Module):
73 76
 	def __init__(self, cmd, rw=False):
74 77
 		self.cmd = cmd
75  
-		self.rw = rw
  78
+		if rw:
  79
+			self.comb += self.cmd.ack.eq(1)
76 80
 	
77 81
 	def do_simulation(self, s):
78 82
 		elts = ["@" + str(s.cycle_counter)]
@@ -80,15 +84,8 @@ def do_simulation(self, s):
80 84
 		elts += decode_sdram(cmdp.ras_n, cmdp.cas_n, cmdp.we_n, cmdp.ba, cmdp.a)
81 85
 		if len(elts) > 1:
82 86
 			print("\t".join(elts))
83  
-	
84  
-	def get_fragment(self):
85  
-		if self.rw:
86  
-			comb = [self.cmd.ack.eq(1)]
87  
-		else:
88  
-			comb = []
89  
-		return Fragment(comb, sim=[self.do_simulation])
90 87
 
91  
-class DFILogger:
  88
+class DFILogger(Module):
92 89
 	def __init__(self, dfi):
93 90
 		self.dfi = dfi
94 91
 	
@@ -96,35 +93,7 @@ def do_simulation(self, s):
96 93
 		dfip = Proxy(s, self.dfi)
97 94
 		
98 95
 		for i, p in enumerate(dfip.phases):
99  
-			elts = ["PH=" + str(i) + "\t @" + str(s.cycle_counter)]
  96
+			elts = ["@" + str(s.cycle_counter) + ":" + str(i)]
100 97
 			elts += decode_sdram(p.ras_n, p.cas_n, p.we_n, p.bank, p.address)
101 98
 			if len(elts) > 1:
102 99
 				print("\t".join(elts))
103  
-	
104  
-	def get_fragment(self):
105  
-		return Fragment(sim=[self.do_simulation])
106  
-		
107  
-class SlotsLogger:
108  
-	def __init__(self, slicer, slots):
109  
-		self.slicer = slicer
110  
-		self.slots = slots
111  
-		
112  
-	def do_simulation(self, sim):
113  
-		state_strs = ["EMPTY", "PEND", "PRCESS"]
114  
-		rw_strs = ["RD", "WR"]
115  
-		print("\t" + "\t".join([str(x) for x in range(len(self.slots))]))
116  
-		print("State:\t" + "\t".join([state_strs[sim.rd(s.state)] for s in self.slots]))
117  
-		print("RW:\t" + "\t".join([rw_strs[sim.rd(s.we)] for s in self.slots]))
118  
-		print("Row:\t" + "\t".join([str(self.slicer.row(sim.rd(s.adr))) for s in self.slots]))
119  
-		print("Bank:\t" + "\t".join([str(self.slicer.bank(sim.rd(s.adr))) for s in self.slots]))
120  
-		print("Col:\t" + "\t".join([str(self.slicer.col(sim.rd(s.adr))) for s in self.slots]))
121  
-		times = []
122  
-		for s in self.slots:
123  
-			if s.time:
124  
-				times.append(str(sim.rd(s._counter)) + "/" + str(s.time))
125  
-			else:
126  
-				times.append("N/A")
127  
-		print("Time:\t" + "\t".join(times))
128  
-
129  
-	def get_fragment(self):
130  
-		return Fragment(sim=[self.do_simulation])
45  tb/lasmicon/lasmicon.py
... ...
@@ -0,0 +1,45 @@
  1
+from migen.fhdl.std import *
  2
+from migen.bus.lasmibus import *
  3
+from migen.sim.generic import Simulator, TopLevel
  4
+
  5
+from milkymist.lasmicon import *
  6
+
  7
+from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
  8
+
  9
+def my_generator_r(n):
  10
+	for x in range(10):
  11
+		t = TRead(128*n + 48*n*x)
  12
+		yield t
  13
+	print("{0:3}: reads done".format(n))
  14
+
  15
+def my_generator_w(n):
  16
+	for x in range(10):
  17
+		t = TWrite(128*n + 48*n*x, x)
  18
+		yield t
  19
+	print("{0:3}: writes done".format(n))
  20
+
  21
+def my_generator(n):
  22
+	if n % 2:
  23
+		return my_generator_w(n // 2)
  24
+	else:
  25
+		return my_generator_r(n // 2)
  26
+
  27
+class TB(Module):
  28
+	def __init__(self):
  29
+		self.submodules.dut = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
  30
+		self.submodules.xbar = lasmibus.Crossbar([self.dut.lasmic], 6, self.dut.nrowbits)
  31
+		self.submodules.logger = DFILogger(self.dut.dfi)
  32
+
  33
+		self.initiators = [Initiator(my_generator(n), master)
  34
+			for n, master in enumerate(self.xbar.masters)]
  35
+		self.submodules += self.initiators
  36
+
  37
+	def do_simulation(self, s):
  38
+		s.interrupt = all(initiator.done for initiator in self.initiators)
  39
+
  40
+
  41
+def main():
  42
+	sim = Simulator(TB(), TopLevel("my.vcd"))
  43
+	sim.run()
  44
+
  45
+main()
43  tb/lasmicon/lasmicon_wb.py
... ...
@@ -0,0 +1,43 @@
  1
+from migen.fhdl.std import *
  2
+from migen.bus import wishbone, wishbone2lasmi, lasmibus
  3
+from migen.bus.transactions import *
  4
+from migen.sim.generic import Simulator, TopLevel
  5
+
  6
+from milkymist.lasmicon import *
  7
+
  8
+from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
  9
+
  10
+l2_size = 8192 # in bytes
  11
+
  12
+def my_generator():
  13
+	for x in range(20):
  14
+		t = TWrite(x, x)
  15
+		yield t
  16
+		print(str(t) + " delay=" + str(t.latency))
  17
+	for x in range(20):
  18
+		t = TRead(x)
  19
+		yield t
  20
+		print(str(t) + " delay=" + str(t.latency))
  21
+	for x in range(20):
  22
+		t = TRead(x+l2_size//4)
  23
+		yield t
  24
+		print(str(t) + " delay=" + str(t.latency))
  25
+
  26
+class TB(Module):
  27
+	def __init__(self):
  28
+		self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
  29
+		# FIXME: remove dummy master
  30
+		self.submodules.xbar = lasmibus.Crossbar([self.ctler.lasmic], 2, self.ctler.nrowbits)
  31
+		self.submodules.logger = DFILogger(self.ctler.dfi)
  32
+		self.submodules.bridge = wishbone2lasmi.WB2LASMI(l2_size//4, self.xbar.masters[0])
  33
+		self.submodules.initiator = wishbone.Initiator(my_generator())
  34
+		self.submodules.conn = wishbone.InterconnectPointToPoint(self.initiator.bus, self.bridge.wishbone)
  35
+
  36
+	def do_simulation(self, s):
  37
+		s.interrupt = self.initiator.done
  38
+
  39
+def main():
  40
+	sim = Simulator(TB(), TopLevel("my.vcd"))
  41
+	sim.run()
  42
+
  43
+main()
20  tb/asmicon/refresher.py → tb/lasmicon/refresher.py
@@ -3,11 +3,11 @@
3 3
 from migen.fhdl.std import *
4 4
 from migen.sim.generic import Simulator, TopLevel
5 5
 
6  
-from milkymist.asmicon.refresher import *
  6
+from milkymist.lasmicon.refresher import *
7 7
 
8 8
 from common import CommandLogger
9 9
 
10  
-class Granter:
  10
+class Granter(Module):
11 11
 	def __init__(self, req, ack):
12 12
 		self.req = req
13 13
 		self.ack = ack
@@ -34,16 +34,14 @@ def do_simulation(self, s):
34 34
 			
35 35
 		if len(elts) > 1:
36 36
 			print("\t".join(elts))
37  
-	
38  
-	def get_fragment(self):
39  
-		return Fragment(sim=[self.do_simulation])
  37
+
  38
+class TB(Module):
  39
+	def __init__(self):
  40
+		self.submodules.dut = Refresher(13, 2, tRP=3, tREFI=100, tRFC=5)
  41
+		self.submodules.logger = CommandLogger(self.dut.cmd)
  42
+		self.submodules.granter = Granter(self.dut.req, self.dut.ack)
40 43
 
41 44
 def main():
42  
-	dut = Refresher(13, 2, tRP=3, tREFI=100, tRFC=5)
43  
-	logger = CommandLogger(dut.cmd)
44  
-	granter = Granter(dut.req, dut.ack)
45  
-	fragment = dut.get_fragment() + logger.get_fragment() + granter.get_fragment()
46  
-	sim = Simulator(fragment)
47  
-	sim.run(400)
  45
+	Simulator(TB()).run(400)
48 46
 
49 47
 main()

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