Skip to content
This repository

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP
  • 2 commits
  • 2 files changed
  • 0 comments
  • 1 contributor
12  milkymist/cif.py
@@ -180,19 +180,27 @@ def gen_cmd(comment, a, ba, cmd, delay):
180 180
 
181 181
 	elif sdram_phy.phy_settings.memtype == "DDR2":
182 182
 		bl = 2*sdram_phy.phy_settings.nphases
183  
-		mr  = log2_int(bl) + (cl << 4)
  183
+		wr = 2
  184
+		mr  = log2_int(bl) + (cl << 4) + (wr << 9)
184 185
 		emr = 0
  186
+		emr2 = 0
  187
+		emr3 = 0
185 188
 		reset_dll = 1 << 8
  189
+		ocd = 7 << 7
186 190
 
187 191
 		init_sequence = [
188 192
 			("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
189 193
 			("Precharge All",  0x0400, 0, cmds["PRECHARGE_ALL"], 0),
  194
+			("Load Extended Mode Register 3", emr3, 3, cmds["MODE_REGISTER"], 0),
  195
+			("Load Extended Mode Register 2", emr2, 2, cmds["MODE_REGISTER"], 0),
190 196
 			("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
191 197
 			("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
192 198
 			("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
193 199
 			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
194 200
 			("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
195  
-			("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
  201
+			("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200),
  202
+			("Load Extended Mode Register / OCD Default", emr+ocd, 1, cmds["MODE_REGISTER"], 0),
  203
+			("Load Extended Mode Register / OCD Exit", emr, 1, cmds["MODE_REGISTER"], 0),
196 204
 		]
197 205
 
198 206
 	for comment, a, ba, cmd, delay in init_sequence:
25  milkymist/s6ddrphy/__init__.py
@@ -101,13 +101,13 @@ def __init__(self, pads, memtype, nphases, cl, bitslip):
101 101
 		sd_sdram_half += [
102 102
 			pads.a.eq(r_dfi[phase_sel].address),
103 103
 			pads.ba.eq(r_dfi[phase_sel].bank),
104  
-			pads.cs_n.eq(r_dfi[phase_sel].cs_n),
105 104
 			pads.cke.eq(r_dfi[phase_sel].cke),
106 105
 			pads.ras_n.eq(r_dfi[phase_sel].ras_n),
107 106
 			pads.cas_n.eq(r_dfi[phase_sel].cas_n),
108 107
 			pads.we_n.eq(r_dfi[phase_sel].we_n)
109 108
 		]
110  
-
  109
+		if hasattr(pads, "cs_n"):
  110
+			sd_sdram_half += pads.cs_n.eq(r_dfi[phase_sel].cs_n)
111 111
 
112 112
 		# 
113 113
 		# Bitslip
@@ -181,12 +181,21 @@ def __init__(self, pads, memtype, nphases, cl, bitslip):
181 181
 			)
182 182
 
183 183
 			# DQS tristate buffer
184  
-			self.specials += Instance("OBUFT",
185  
-				Instance.Input("I", dqs_o[i]),
186  
-				Instance.Input("T", dqs_t[i]),
187  
-
188  
-				Instance.Output("O", pads.dqs[i])
189  
-			)
  184
+			if hasattr(pads, "dqs_n"):
  185
+				self.specials += Instance("OBUFTDS",
  186
+					Instance.Input("I", dqs_o[i]),
  187
+					Instance.Input("T", dqs_t[i]),
  188
+
  189
+					Instance.Output("O", pads.dqs[i]),
  190
+					Instance.Output("OB", pads.dqs_n[i]),
  191
+				)
  192
+			else:
  193
+				self.specials += Instance("OBUFT",
  194
+					Instance.Input("I", dqs_o[i]),
  195
+					Instance.Input("T", dqs_t[i]),
  196
+
  197
+					Instance.Output("O", pads.dqs[i])
  198
+				)
190 199
 
191 200
 		sd_sdram_half += postamble.eq(drive_dqs)
192 201
 

No commit comments for this range

Something went wrong with that request. Please try again.