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  • 2 commits
  • 2 files changed
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  • 1 contributor
Showing with 27 additions and 10 deletions.
  1. +10 −2 milkymist/cif.py
  2. +17 −8 milkymist/s6ddrphy/__init__.py
View
12 milkymist/cif.py
@@ -180,19 +180,27 @@ def gen_cmd(comment, a, ba, cmd, delay):
elif sdram_phy.phy_settings.memtype == "DDR2":
bl = 2*sdram_phy.phy_settings.nphases
- mr = log2_int(bl) + (cl << 4)
+ wr = 2
+ mr = log2_int(bl) + (cl << 4) + (wr << 9)
emr = 0
+ emr2 = 0
+ emr3 = 0
reset_dll = 1 << 8
+ ocd = 7 << 7
init_sequence = [
("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
+ ("Load Extended Mode Register 3", emr3, 3, cmds["MODE_REGISTER"], 0),
+ ("Load Extended Mode Register 2", emr2, 2, cmds["MODE_REGISTER"], 0),
("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
- ("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
+ ("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200),
+ ("Load Extended Mode Register / OCD Default", emr+ocd, 1, cmds["MODE_REGISTER"], 0),
+ ("Load Extended Mode Register / OCD Exit", emr, 1, cmds["MODE_REGISTER"], 0),
]
for comment, a, ba, cmd, delay in init_sequence:
View
25 milkymist/s6ddrphy/__init__.py
@@ -101,13 +101,13 @@ def __init__(self, pads, memtype, nphases, cl, bitslip):
sd_sdram_half += [
pads.a.eq(r_dfi[phase_sel].address),
pads.ba.eq(r_dfi[phase_sel].bank),
- pads.cs_n.eq(r_dfi[phase_sel].cs_n),
pads.cke.eq(r_dfi[phase_sel].cke),
pads.ras_n.eq(r_dfi[phase_sel].ras_n),
pads.cas_n.eq(r_dfi[phase_sel].cas_n),
pads.we_n.eq(r_dfi[phase_sel].we_n)
]
-
+ if hasattr(pads, "cs_n"):
+ sd_sdram_half += pads.cs_n.eq(r_dfi[phase_sel].cs_n)
#
# Bitslip
@@ -181,12 +181,21 @@ def __init__(self, pads, memtype, nphases, cl, bitslip):
)
# DQS tristate buffer
- self.specials += Instance("OBUFT",
- Instance.Input("I", dqs_o[i]),
- Instance.Input("T", dqs_t[i]),
-
- Instance.Output("O", pads.dqs[i])
- )
+ if hasattr(pads, "dqs_n"):
+ self.specials += Instance("OBUFTDS",
+ Instance.Input("I", dqs_o[i]),
+ Instance.Input("T", dqs_t[i]),
+
+ Instance.Output("O", pads.dqs[i]),
+ Instance.Output("OB", pads.dqs_n[i]),
+ )
+ else:
+ self.specials += Instance("OBUFT",
+ Instance.Input("I", dqs_o[i]),
+ Instance.Input("T", dqs_t[i]),
+
+ Instance.Output("O", pads.dqs[i])
+ )
sd_sdram_half += postamble.eq(drive_dqs)

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