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agg_test: 1024x768 demo

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commit 9a7c3d9da7911e86902f2137632b7ac0fdf8efb6 1 parent db94788
Sébastien Bourdeauducq authored March 28, 2013

Showing 1 changed file with 86 additions and 2 deletions. Show diff stats Hide diff stats

  1. 88  agg_test.cpp
88  agg_test.cpp
@@ -2,12 +2,13 @@
2 2
 #include <stdio.h>
3 3
 #include <math.h>
4 4
 #include <hw/csr.h>
  5
+#include <hw/flags.h>
5 6
 #include "agg.h"
6 7
 
7 8
 enum
8 9
 {
9  
-    width  = 640,
10  
-    height = 480
  10
+    width  = 1024,
  11
+    height = 768
11 12
 };
12 13
 
13 14
 
@@ -54,8 +55,91 @@ void draw_line(agg::rasterizer& ras,
54 55
     ras.line_to_d(x1 + dx,  y1 - dy);
55 56
 }
56 57
 
  58
+enum {
  59
+    VGA_MODE_640_480,
  60
+    VGA_MODE_800_600,
  61
+    VGA_MODE_1024_768
  62
+};
  63
+
  64
+static void vga_clkgen_write(int cmd, int data)
  65
+{
  66
+    int word;
  67
+
  68
+    word = (data << 2) | cmd;
  69
+    crg_cmd_data_write(word);
  70
+    crg_send_cmd_data_write(1);
  71
+    while(crg_status_read() & CLKGEN_STATUS_BUSY);
  72
+}
  73
+
  74
+/* http://web.mit.edu/6.111/www/s2004/NEWKIT/vga.shtml */
  75
+static void vga_set_mode(int mode)
  76
+{
  77
+    int vga_hres, vga_vres;
  78
+    int clock_m, clock_d;
  79
+
  80
+    switch(mode) {
  81
+        default:
  82
+        case VGA_MODE_640_480: // Pixel clock: 25MHz
  83
+            vga_hres = 640;
  84
+            vga_vres = 480;
  85
+            clock_m = 2;
  86
+            clock_d = 4;
  87
+            fb_hres_write(640);
  88
+            fb_hsync_start_write(656);
  89
+            fb_hsync_end_write(752);
  90
+            fb_hscan_write(799);
  91
+            fb_vres_write(480);
  92
+            fb_vsync_start_write(492);
  93
+            fb_vsync_end_write(494);
  94
+            fb_vscan_write(524);
  95
+            break;
  96
+        case VGA_MODE_800_600: // Pixel clock: 50MHz
  97
+            vga_hres = 800;
  98
+            vga_vres = 600;
  99
+            clock_m = 2;
  100
+            clock_d = 2;
  101
+            fb_hres_write(800);
  102
+            fb_hsync_start_write(848);
  103
+            fb_hsync_end_write(976);
  104
+            fb_hscan_write(1040);
  105
+            fb_vres_write(600);
  106
+            fb_vsync_start_write(636);
  107
+            fb_vsync_end_write(642);
  108
+            fb_vscan_write(665);
  109
+            break;
  110
+        case VGA_MODE_1024_768: // Pixel clock: 65MHz
  111
+            vga_hres = 1024;
  112
+            vga_vres = 768;
  113
+            clock_m = 13;
  114
+            clock_d = 10;
  115
+            fb_hres_write(1024);
  116
+            fb_hsync_start_write(1048);
  117
+            fb_hsync_end_write(1184);
  118
+            fb_hscan_write(1344);
  119
+            fb_vres_write(768);
  120
+            fb_vsync_start_write(772);
  121
+            fb_vsync_end_write(778);
  122
+            fb_vscan_write(807);
  123
+            break;
  124
+    }
  125
+    fb_length_write(vga_hres*vga_vres*4);
  126
+
  127
+    vga_clkgen_write(0x1, clock_d-1);
  128
+    vga_clkgen_write(0x3, clock_m-1);
  129
+    crg_send_go_write(1);
  130
+    printf("waiting for PROGDONE...");
  131
+    while(!(crg_status_read() & CLKGEN_STATUS_PROGDONE));
  132
+    printf("ok\n");
  133
+    printf("waiting for LOCKED...");
  134
+    while(!(crg_status_read() & CLKGEN_STATUS_LOCKED));
  135
+    printf("ok\n");
  136
+
  137
+    printf("VGA: mode set to %dx%d\n", vga_hres, vga_vres);
  138
+}
  139
+
57 140
 static void start_fb(unsigned char *addr)
58 141
 {
  142
+    vga_set_mode(VGA_MODE_1024_768);
59 143
     fb_base_write((unsigned int)addr);
60 144
     fb_enable_write(1);
61 145
 }

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