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Added CAN support for STM32F0xx.
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8046 35acf78f-673a-0410-8e92-d51de3d6d3f4
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gdisirio committed Jun 18, 2015
1 parent c78395f commit 53dde81
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82 changes: 82 additions & 0 deletions os/hal/ports/STM32/LLD/can_lld.c
Expand Up @@ -252,6 +252,38 @@ static void can_lld_sce_handler(CANDriver *canp) {
/*===========================================================================*/

#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__)
#if defined(STM32_CAN1_UNIFIED_HANDLER)
/**
* @brief CAN1 unified interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_CAN1_UNIFIED_HANDLER) {

OSAL_IRQ_PROLOGUE();

can_lld_tx_handler(&CAND1);
can_lld_rx0_handler(&CAND1);
can_lld_rx1_handler(&CAND1);
can_lld_sce_handler(&CAND1);

OSAL_IRQ_EPILOGUE();
}
#else /* !defined(STM32_CAN1_UNIFIED_HANDLER) */

#if !defined(STM32_CAN1_TX_HANDLER)
#error "STM32_CAN1_TX_HANDLER not defined"
#endif
#if !defined(STM32_CAN1_RX0_HANDLER)
#error "STM32_CAN1_RX0_HANDLER not defined"
#endif
#if !defined(STM32_CAN1_RX1_HANDLER)
#error "STM32_CAN1_RX1_HANDLER not defined"
#endif
#if !defined(STM32_CAN1_SCE_HANDLER)
#error "STM32_CAN1_SCE_HANDLER not defined"
#endif

/**
* @brief CAN1 TX interrupt handler.
*
Expand Down Expand Up @@ -307,9 +339,42 @@ OSAL_IRQ_HANDLER(STM32_CAN1_SCE_HANDLER) {

OSAL_IRQ_EPILOGUE();
}
#endif /* !defined(STM32_CAN1_UNIFIED_HANDLER) */
#endif /* STM32_CAN_USE_CAN1 */

#if STM32_CAN_USE_CAN2 || defined(__DOXYGEN__)
#if defined(STM32_CAN2_UNIFIED_HANDLER)
/**
* @brief CAN1 unified interrupt handler.
*
* @isr
*/
OSAL_IRQ_HANDLER(STM32_CAN2_UNIFIED_HANDLER) {

OSAL_IRQ_PROLOGUE();

can_lld_tx_handler(&CAND2);
can_lld_rx0_handler(&CAND2);
can_lld_rx1_handler(&CAND2);
can_lld_sce_handler(&CAND2);

OSAL_IRQ_EPILOGUE();
}
#else /* !defined(STM32_CAN2_UNIFIED_HANDLER) */

#if !defined(STM32_CAN1_TX_HANDLER)
#error "STM32_CAN1_TX_HANDLER not defined"
#endif
#if !defined(STM32_CAN1_RX0_HANDLER)
#error "STM32_CAN1_RX0_HANDLER not defined"
#endif
#if !defined(STM32_CAN1_RX1_HANDLER)
#error "STM32_CAN1_RX1_HANDLER not defined"
#endif
#if !defined(STM32_CAN1_SCE_HANDLER)
#error "STM32_CAN1_SCE_HANDLER not defined"
#endif

/**
* @brief CAN2 TX interrupt handler.
*
Expand Down Expand Up @@ -365,6 +430,7 @@ OSAL_IRQ_HANDLER(STM32_CAN2_SCE_HANDLER) {

OSAL_IRQ_EPILOGUE();
}
#endif /* !defined(STM32_CAN2_UNIFIED_HANDLER) */
#endif /* STM32_CAN_USE_CAN2 */

/*===========================================================================*/
Expand Down Expand Up @@ -409,10 +475,14 @@ void can_lld_start(CANDriver *canp) {
/* Clock activation.*/
#if STM32_CAN_USE_CAN1
if (&CAND1 == canp) {
#if defined(STM32_CAN1_UNIFIED_NUMBER)
nvicEnableVector(STM32_CAN1_UNIFIED_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
#else
nvicEnableVector(STM32_CAN1_TX_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
nvicEnableVector(STM32_CAN1_RX0_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
nvicEnableVector(STM32_CAN1_RX1_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
nvicEnableVector(STM32_CAN1_SCE_NUMBER, STM32_CAN_CAN1_IRQ_PRIORITY);
#endif
rccEnableCAN1(FALSE);
}
#endif
Expand All @@ -421,10 +491,14 @@ void can_lld_start(CANDriver *canp) {

osalDbgAssert(CAND1.state != CAN_STOP, "CAN1 must be started");

#if defined(STM32_CAN2_UNIFIED_NUMBER)
nvicEnableVector(STM32_CAN2_UNIFIED_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
#else
nvicEnableVector(STM32_CAN2_TX_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
nvicEnableVector(STM32_CAN2_RX0_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
nvicEnableVector(STM32_CAN2_RX1_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
nvicEnableVector(STM32_CAN2_SCE_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
#endif
rccEnableCAN2(FALSE);
}
#endif
Expand Down Expand Up @@ -463,21 +537,29 @@ void can_lld_stop(CANDriver *canp) {

CAN1->MCR = 0x00010002; /* Register reset value. */
CAN1->IER = 0x00000000; /* All sources disabled. */
#if defined(STM32_CAN1_UNIFIED_NUMBER)
nvicDisableVector(STM32_CAN1_UNIFIED_NUMBER);
#else
nvicDisableVector(STM32_CAN1_TX_NUMBER);
nvicDisableVector(STM32_CAN1_RX0_NUMBER);
nvicDisableVector(STM32_CAN1_RX1_NUMBER);
nvicDisableVector(STM32_CAN1_SCE_NUMBER);
#endif
rccDisableCAN1(FALSE);
}
#endif
#if STM32_CAN_USE_CAN2
if (&CAND2 == canp) {
CAN2->MCR = 0x00010002; /* Register reset value. */
CAN2->IER = 0x00000000; /* All sources disabled. */
#if defined(STM32_CAN2_UNIFIED_NUMBER)
nvicDisableVector(STM32_CAN2_UNIFIED_NUMBER);
#else
nvicDisableVector(STM32_CAN2_TX_NUMBER);
nvicDisableVector(STM32_CAN2_RX0_NUMBER);
nvicDisableVector(STM32_CAN2_RX1_NUMBER);
nvicDisableVector(STM32_CAN2_SCE_NUMBER);
#endif
rccDisableCAN2(FALSE);
}
#endif
Expand Down
4 changes: 4 additions & 0 deletions os/hal/ports/STM32/STM32F0xx/platform.mk
Expand Up @@ -13,6 +13,9 @@ ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/ext_lld.c
endif
ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/can_lld.c
endif
ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c
endif
Expand Down Expand Up @@ -52,6 +55,7 @@ PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/hal_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/adc_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/can_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/ext_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \
Expand Down
5 changes: 5 additions & 0 deletions os/hal/ports/STM32/STM32F0xx/stm32_isr.h
Expand Up @@ -33,6 +33,11 @@
* @name ISR names and numbers remapping
* @{
*/
/*
* CAN units.
*/
#define STM32_CAN1_UNIFIED_HANDLER VectorB8
#define STM32_CAN1_UNIFIED_NUMBER 30

/*
* I2C units.
Expand Down
32 changes: 32 additions & 0 deletions os/hal/ports/STM32/STM32F0xx/stm32_rcc.h
Expand Up @@ -198,6 +198,38 @@
#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
/** @} */

/**
* @name CAN peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the CAN1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CANEN, lp)

/**
* @brief Disables the CAN1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CANEN, lp)

/**
* @brief Resets the CAN1 peripheral.
*
* @api
*/
#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CANRST)
/** @} */

/**
* @name DAC peripheral specific RCC operations
* @{
Expand Down
6 changes: 6 additions & 0 deletions os/hal/ports/STM32/STM32F0xx/stm32_registry.h
Expand Up @@ -203,7 +203,12 @@
#define STM32_HAS_ADC4 FALSE

/* CAN attributes.*/
#if defined(STM32F072xB)
#define STM32_HAS_CAN1 TRUE
#define STM32_CAN_MAX_FILTERS 14
#else
#define STM32_HAS_CAN1 FALSE
#endif
#define STM32_HAS_CAN2 FALSE

/* DAC attributes.*/
Expand Down Expand Up @@ -655,6 +660,7 @@
/* CAN attributes.*/
#define STM32_HAS_CAN1 TRUE
#define STM32_HAS_CAN2 FALSE
#define STM32_CAN_MAX_FILTERS 14

/* DAC attributes.*/
#define STM32_HAS_DAC1_CH1 FALSE
Expand Down
2 changes: 2 additions & 0 deletions readme.txt
Expand Up @@ -79,7 +79,9 @@
common error cases.
- NIL: Added INTC priorities check to the e200z port.
- RT: Added INTC priorities check to the e200z port.
- HAL: Added support for CAN in STM32F042/72 devices.
- HAL: Added support for extra DMA channels in STM32F072 devices.
- HAL: Modified the STM32 CAN driver to support unified IRQs.
- RT: SPE-related issue in e200z ports (bug #607).
- NIL: SPE-related issue in e200z ports (bug #607).
- HAL: Fixed dependency between STM32 MAC driver and RT (bug #606).
Expand Down
52 changes: 52 additions & 0 deletions testhal/STM32/STM32F0xx/CAN/.cproject
@@ -0,0 +1,52 @@
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90 changes: 90 additions & 0 deletions testhal/STM32/STM32F0xx/CAN/.project
@@ -0,0 +1,90 @@
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