diff --git a/HW/QuartusProjects/Common/adc_ltc2308.v b/HW/QuartusProjects/Common/adc_ltc2308.v index bf859478..22bdb3eb 100644 --- a/HW/QuartusProjects/Common/adc_ltc2308.v +++ b/HW/QuartusProjects/Common/adc_ltc2308.v @@ -1,37 +1,37 @@ module adc_ltc2308( - clk, // max 40mhz - - // start measure - measure_start, // posedge triggle - measure_ch, - measure_done, - measure_dataread, - - // adc interface - ADC_CONVST, - ADC_SCK, - ADC_SDI, - ADC_SDO + clk, // max 40mhz + + // start measure + measure_start, // posedge triggle + measure_ch, + measure_done, + measured_data, + + // adc interface + ADC_CONVST, + ADC_SCK, + ADC_SDI, + ADC_SDO ); -input clk; +input clk; // start measure -input measure_start; -input [2:0] measure_ch; -output reg measure_done; -output [11:0] measure_dataread; +input measure_start; +input [2:0] measure_ch; +output reg measure_done; +output reg [11:0] measured_data; -output ADC_CONVST; -output ADC_SCK; -output reg ADC_SDI; -input ADC_SDO; +output ADC_CONVST; +output ADC_SCK; +output reg ADC_SDI; +input ADC_SDO; ///////////////////////////////// -// Timing definition +// Timing definition // using 40MHz clock // to acheive fsample = 500KHz @@ -39,68 +39,68 @@ input ADC_SDO; -`define DATA_BITS_NUM 12 -`define CMD_BITS_NUM 6 -`define CH_NUM 8 +`define DATA_BITS_NUM 12 +`define CMD_BITS_NUM 6 +`define CH_NUM 8 -`define tWHCONV 1 // CONVST High Time, min 20 ns -`define tCONV 64 //52 // tCONV: type 1.3 us, MAX 1.6 us, 1600/25(assumed clk is 40mhz)=64 -> 1.3us/25ns = 52 - // set 64 for suite for 1.6 us max -// +12 //data +`define tWHCONV 1 // CONVST High Time, min 20 ns +`define tCONV 64 //52 // tCONV: type 1.3 us, MAX 1.6 us, 1600/25(assumed clk is 40mhz)=64 -> 1.3us/25ns = 52 + // set 64 for suite for 1.6 us max +// +12 //data -`define tHCONVST 320 // 12 // here set 320（ fsample = 100KHz） for if ADC input impedance is high, see below +`define tHCONVST 320 // 12 // here set 320（ fsample = 100KHz） for if ADC input impedance is high, see below // If the source impedance of the driving circuit is low, the ADC inputs can be driven directly. //Otherwise, more acquisition time should be allowed for a source with higher impedance. - // for acheiving 500KHz fmax. set n cyc = 80. -`define tCONVST_HIGH_START 0 -`define tCONVST_HIGH_END (`tCONVST_HIGH_START+`tWHCONV) + // for acheiving 500KHz fmax. set n cyc = 80. +`define tCONVST_HIGH_START 0 +`define tCONVST_HIGH_END (`tCONVST_HIGH_START+`tWHCONV) -`define tCONFIG_START (`tCONVST_HIGH_END) -`define tCONFIG_END (`tCLK_START+`CMD_BITS_NUM - 1) +`define tCONFIG_START (`tCONVST_HIGH_END) +`define tCONFIG_END (`tCLK_START+`CMD_BITS_NUM - 1) -`define tCLK_START (`tCONVST_HIGH_START+`tCONV) -`define tCLK_END (`tCLK_START+`DATA_BITS_NUM) +`define tCLK_START (`tCONVST_HIGH_START+`tCONV) +`define tCLK_END (`tCLK_START+`DATA_BITS_NUM) -`define tDONE (`tCLK_END+`tHCONVST) +`define tDONE (`tCLK_END+`tHCONVST) // create triggle message: reset_n reg pre_measure_start; -always @ (posedge clk) +always @ (posedge clk) begin - pre_measure_start <= measure_start; + pre_measure_start <= measure_start; end wire reset_n; assign reset_n = (!pre_measure_start & measure_start)?1'b0:1'b1; // tick -reg [15:0] tick; -always @ (posedge clk or negedge reset_n) +reg [15:0] tick; +always @ (posedge clk or negedge reset_n) begin - if (!reset_n) - tick <= 0; - else if (tick < `tDONE) - tick <= tick + 1; + if (!reset_n) + tick <= 0; + else if (tick < `tDONE) + tick <= tick + 1; end ///////////////////////////////// -// ADC_CONVST +// ADC_CONVST assign ADC_CONVST = (tick >= `tCONVST_HIGH_START && tick < `tCONVST_HIGH_END)?1'b1:1'b0; ///////////////////////////////// -// ADC_SCK +// ADC_SCK reg clk_enable; // must sync to clk in clk low -always @ (negedge clk or negedge reset_n) +always @ (negedge clk or negedge reset_n) begin - if (!reset_n) - clk_enable <= 1'b0; - else if ((tick >= `tCLK_START && tick < `tCLK_END)) - clk_enable <= 1'b1; - else - clk_enable <= 1'b0; + if (!reset_n) + clk_enable <= 1'b0; + else if ((tick >= `tCLK_START && tick < `tCLK_END)) + clk_enable <= 1'b1; + else + clk_enable <= 1'b0; end assign ADC_SCK = clk_enable?clk:1'b0; @@ -108,25 +108,25 @@ assign ADC_SCK = clk_enable?clk:1'b0; /////////////////////////////// // read data -reg [(`DATA_BITS_NUM-1):0] read_data; +//reg [(`DATA_BITS_NUM-1):0] measured_data; reg [3:0] write_pos; -assign measure_dataread = read_data; +assign measured_data = measured_data; -always @ (negedge clk or negedge reset_n) +always @ (negedge clk or negedge reset_n) begin - if (!reset_n) - begin - read_data <= 0; - write_pos <= `DATA_BITS_NUM-1; - end - else if (clk_enable) - begin - read_data[write_pos] <= ADC_SDO; - write_pos <= write_pos - 1; - end + if (!reset_n) + begin + measured_data <= 0; + write_pos <= `DATA_BITS_NUM-1; + end + else if (clk_enable) + begin + measured_data[write_pos] <= ADC_SDO; + write_pos <= write_pos - 1; + end end /////////////////////////////// @@ -135,12 +135,12 @@ wire read_ch_done; assign read_ch_done = (tick == `tDONE)?1'b1:1'b0; -always @ (posedge clk or negedge reset_n) +always @ (posedge clk or negedge reset_n) begin - if (!reset_n) - measure_done <= 1'b0; - else if (read_ch_done) - measure_done <= 1'b1; + if (!reset_n) + measure_done <= 1'b0; + else if (read_ch_done) + measure_done <= 1'b1; end /////////////////////////////// @@ -150,25 +150,25 @@ end reg [(`CMD_BITS_NUM-1):0] config_cmd; -`define UNI_MODE 1'b1 //1: Unipolar, 0:Bipolar -`define SLP_MODE 1'b0 //1: enable sleep +`define UNI_MODE 1'b1 //1: Unipolar, 0:Bipolar +`define SLP_MODE 1'b0 //1: enable sleep always @(negedge reset_n) begin - if (!reset_n) - begin - case (measure_ch) - 0 : config_cmd <= {4'h8, `UNI_MODE, `SLP_MODE}; - 1 : config_cmd <= {4'hC, `UNI_MODE, `SLP_MODE}; - 2 : config_cmd <= {4'h9, `UNI_MODE, `SLP_MODE}; - 3 : config_cmd <= {4'hD, `UNI_MODE, `SLP_MODE}; - 4 : config_cmd <= {4'hA, `UNI_MODE, `SLP_MODE}; - 5 : config_cmd <= {4'hE, `UNI_MODE, `SLP_MODE}; - 6 : config_cmd <= {4'hB, `UNI_MODE, `SLP_MODE}; - 7 : config_cmd <= {4'hF, `UNI_MODE, `SLP_MODE}; - default : config_cmd <= {4'hF, 2'b00}; - endcase - end + if (!reset_n) + begin + case (measure_ch) + 0 : config_cmd <= {4'h8, `UNI_MODE, `SLP_MODE}; + 1 : config_cmd <= {4'hC, `UNI_MODE, `SLP_MODE}; + 2 : config_cmd <= {4'h9, `UNI_MODE, `SLP_MODE}; + 3 : config_cmd <= {4'hD, `UNI_MODE, `SLP_MODE}; + 4 : config_cmd <= {4'hA, `UNI_MODE, `SLP_MODE}; + 5 : config_cmd <= {4'hE, `UNI_MODE, `SLP_MODE}; + 6 : config_cmd <= {4'hB, `UNI_MODE, `SLP_MODE}; + 7 : config_cmd <= {4'hF, `UNI_MODE, `SLP_MODE}; + default : config_cmd <= {4'hF, 2'b00}; + endcase + end end // serial config command to adc chip @@ -177,27 +177,24 @@ wire config_enable; wire config_done; reg [2:0] sdi_index; -assign config_init = (tick == `tCONFIG_START)?1'b1:1'b0; +assign config_init = (tick == `tCONFIG_START)?1'b1:1'b0; assign config_enable = (tick > `tCLK_START && tick <= `tCONFIG_END)?1'b1:1'b0; // > because this is negative edge triggle -assign config_done = (tick > `tCONFIG_END)?1'b1:1'b0; -always @(negedge clk) +assign config_done = (tick > `tCONFIG_END)?1'b1:1'b0; +always @(negedge clk) begin - if (config_init) - begin - ADC_SDI <= config_cmd[`CMD_BITS_NUM-1]; - sdi_index <= `CMD_BITS_NUM-2; - end - else if (config_enable) - begin - ADC_SDI <= config_cmd[sdi_index]; - sdi_index <= sdi_index - 1; - end - else if (config_done) - ADC_SDI <= 1'b0; // + if (config_init) + begin + ADC_SDI <= config_cmd[`CMD_BITS_NUM-1]; + sdi_index <= `CMD_BITS_NUM-2; + end + else if (config_enable) + begin + ADC_SDI <= config_cmd[sdi_index]; + sdi_index <= sdi_index - 1; + end + else if (config_done) + ADC_SDI <= 1'b0; // end - - - endmodule diff --git a/HW/QuartusProjects/Common/adc_ltc2308_fifo.sv b/HW/QuartusProjects/Common/adc_ltc2308_fifo.sv index 5ffd6926..2b42cb7b 100644 --- a/HW/QuartusProjects/Common/adc_ltc2308_fifo.sv +++ b/HW/QuartusProjects/Common/adc_ltc2308_fifo.sv @@ -74,10 +74,9 @@ begin if (slave_read_status) readdataout <= {4'b0, measure_fifo_num, 9'b0, measure_fifo_ch, 3'b0, measure_fifo_done}; else if (slave_read_data) - readdataout <= {13'b0, fifo_ch_q, 4'b0, fifo_q}; + readdataout <= {1'b0, fifo_ch_q, 16'b0, fifo_q}; end -//reg [1:0] post_read_outdata; reg post_read_outdata; reg fifo_rdreq; always @ (posedge clock or negedge reset_n) @@ -118,7 +117,7 @@ reg config_first; reg wait_measure_done; reg measure_start; wire measure_done; -wire [11:0] measure_dataread; +wire [11:0] measured_data; // auto channel change //wire [2:0] adc_ch_sel = (auto_ch_select) ? 3'h7:measure_fifo_ch; @@ -200,7 +199,7 @@ adc_ltc2308 adc_ltc2308_inst( .measure_start(measure_start), // posedge triggle .measure_done(measure_done), .measure_ch(adc_ch), - .measure_dataread(measure_dataread), + .measured_data(measured_data), // adc interface @@ -215,7 +214,7 @@ adc_ltc2308 adc_ltc2308_inst( adc_data_fifo adc_data_fifo_inst( .aclr(adc_reset), - .data({adc_ch_dly, measure_dataread}), + .data({adc_ch_dly, measured_data}), // .rdclk(read_outdata), .rdclk(clock), .rdreq(fifo_rdreq), diff --git a/HW/QuartusProjects/Common/gpio_adr_decoder_reg.sv b/HW/QuartusProjects/Common/gpio_adr_decoder_reg.sv index 96b72cd6..a95a4968 100644 --- a/HW/QuartusProjects/Common/gpio_adr_decoder_reg.sv +++ b/HW/QuartusProjects/Common/gpio_adr_decoder_reg.sv @@ -1,445 +1,442 @@ -/* -// adc addresses: -// 0x0200 for start and status -// 0x0204 for data - -// -// cap sensor address: -// 0x0300 1 bit pr sensor (Data read) -// 0x0304 Hysteresis sens 0-7 (4-bit pr sensor) -// -// 0x1000 I/O port 0..23 -// 0x1004 I/O port 24..47 -// 0x1008 I/O port 48..71 -// 0x100C I/O port 72..95 -// 0x1010 I/O port 96..127 -// 0x1014 I/O port 128..143 - -// 0x1100 DDR for I/O port 0..23 -// 0x1104 DDR for I/O port 24..47 -// 0x1108 DDR for I/O port 48..71 -// 0x110C DDR for I/O port 72..95 -// 0x1110 DDR for I/O port 96..127 -// 0x1114 DDR for I/O port 128..144 -// '1' bit in DDR register makes corresponding GPIO bit an output -// -// 0x1120 Portnums for I/O port 0..3 -// 0x1124 Portnums for I/O port 4..7 -// 0x1128 Portnums for I/O port 8..11 -// 0x112C Portnums for I/O port 12..15 -// 0x1130 Portnums for I/O port 16..19 -// 0x1134 Portnums for I/O port 20..23 -// -// 0x1300 OpenDrainSelect for I/O port 0..23 -// 0x1304 OpenDrainSelect for I/O port 24..47 -// 0x1308 OpenDrainSelect for I/O port 48..71 -// 0x130C OpenDrainSelect for I/O port 72..95 -// 0x1310 OpenDrainSelect for I/O port 96..127 -// 0x1314 OpenDrainSelect for I/O port 128..143 -// '1' bit in OpenDrainSelect register makes corresponding GPIO an -// open drain output. -// If OpenDrain is selected for an I/O bit , the DDR register is ignored. -*/ - -module gpio_adr_decoder_reg( - input CLOCK, - input reg_clk, - input reset_reg_N, - input chip_sel, - input write_reg, - input read_reg, - input [AddrWidth-1:2] busaddress, - input [BusWidth-1:0] busdata_in, - input [MuxGPIOIOWidth-1:0] iodatafromhm3[NumGPIO-1:0], - input [BusWidth-1:0] busdata_fromhm2, -// - inout [GPIOWidth-1:0] gpioport[NumGPIO-1:0], -// - output reg [MuxGPIOIOWidth-1:0] iodatatohm3[NumGPIO-1:0], - output reg [BusWidth-1:0] busdata_to_cpu, -// adc interface - input adc_clk, // max 40mhz - output ADC_CONVST_o, - output ADC_SCK_o, - output ADC_SDI_o, - input ADC_SDO_i, -// Touch sensor: - output [11:0] calibval_0, - output [13:0] counts_0, - output [NumSense-1:0] touched, - input [1:0] buttons -); - -parameter AddrWidth = 16; -parameter BusWidth = 32; -parameter GPIOWidth = 36; -parameter MuxGPIOIOWidth = 36; -parameter NumIOAddrReg = 6; -parameter NumGPIO = 2; - -parameter Capsense = 1; -parameter NumSense = 4; -parameter ADC = ""; -// local param -parameter IoRegWidth = 24; -parameter AdcOutShift = 2; -parameter ReadInShift = 2; -parameter WriteInShift = 2; -parameter PortNumWidth = 8; -parameter NumPinsPrIOAddr = 4; -parameter Mux_regPrIOReg = 6; -parameter TotalNumregs = Mux_regPrIOReg * NumIOAddrReg * NumPinsPrIOAddr; - - wire reset_in = ~reset_reg_N; - wire [GPIOWidth-1:0] gpio_input_data[NumGPIO-1:0]; - - - reg [ReadInShift:0] read_reg_r; - reg [WriteInShift:0] write_reg_r; - reg [AddrWidth-1:0] busaddress_r; - reg [BusWidth-1:0] busdata_in_r; - reg [MuxGPIOIOWidth-1:0] iodatafromhm3_r[NumGPIO-1:0]; - - reg [AddrWidth-1:0] local_address_r; - - reg [IoRegWidth-1:0] io_reg[NumIOAddrReg-1:0]; - reg [IoRegWidth-1:0] od_reg[NumIOAddrReg-1:0]; - reg [IoRegWidth-1:0] ddr_reg[NumIOAddrReg-1:0]; - - reg [BusWidth-1:0] mux_reg[NumIOAddrReg-1:0][Mux_regPrIOReg-1:0]; - - reg [PortNumWidth-1:0] portselnum[TotalNumregs-1:0]; - - - wire [GPIOWidth-1:0] io_reg_gpio[NumGPIO-1:0]; - wire [PortNumWidth-1:0] mux_reg_index; - wire [4:0] mux_reg_addr; - wire [1:0] mux_reg_byte; - - wire [GPIOWidth-1:0] out_ena[NumGPIO-1:0]; - wire [GPIOWidth-1:0] od[NumGPIO-1:0]; - -// wire [PortNumWidth-1:0] portnumsel[NumGPIO-1:0][GPIOWidth-1:0]; - wire [PortNumWidth-1:0] portnumsel[(GPIOWidth * NumGPIO)-1:0]; - - wire read_address = read_reg_r[ReadInShift]; - reg write_address; - -// wire io_address_valid = ((busaddress_r >= 16'h1000) && (busaddress_r < 16'h1020)) ? 1'b1 : 1'b0; - wire ddr_address_valid = ((busaddress_r >= 16'h1100) && (busaddress_r < 16'h1120)) ? 1'b1 : 1'b0; - wire mux_address_valid = ((busaddress_r >= 16'h1120) && (busaddress_r < 16'h1200)) ? 1'b1 : 1'b0; - wire od_address_valid = ((busaddress_r >= 16'h1300) && (busaddress_r < 16'h1320)) ? 1'b1 : 1'b0; - -// wire io_read_valid = (io_address_valid && read_address) ? 1'b1 : 1'b0; -// wire ddr_read_valid = (ddr_address_valid && read_address) ? 1'b1 : 1'b0; - wire mux_read_valid = (mux_address_valid && read_address) ? 1'b1 : 1'b0; -// wire od_read_valid = (od_address_valid && read_address) ? 1'b1 : 1'b0; - -// wire io_write_valid = (io_address_valid && write_address) ? 1'b1 : 1'b0; -// wire ddr_write_valid = (ddr_address_valid && write_address) ? 1'b1 : 1'b0; - wire mux_write_valid = (mux_address_valid && write_address) ? 1'b1 : 1'b0; -// wire od_write_valid = (od_address_valid && write_address) ? 1'b1 : 1'b0; - -// ADC module: -// wire read_adc_address = read_reg_r[AdcOutShift]; - wire read_adc_address = read_reg_r[0]; -// wire read_adc_out = read_reg_r[AdcOutShift]; - wire adc_address_valid = ( (busaddress_r >= 16'h0200) && (busaddress_r <= 16'h0204)) ? 1'b1 : 1'b0; - wire adc_read_valid = (adc_address_valid && read_adc_address) ? 1'b1 : 1'b0; - wire adc_write_valid = (adc_address_valid && write_address) ? 1'b1 : 1'b0; - wire [31:0]adc_data_out; - -// Touch sensor: - wire [NumSense-1:0] sense; - wire charge; - reg [BusWidth-1:0] hysteresis_reg; - wire [3:0] hysteresis[NumSense-1:0]; - - wire sense_reset = ~reset_reg_N | ~buttons[1]; -// wire sense_reset = ~reset_reg_N; - - genvar sh; - generate - for(sh=0;sh= 1) begin - assign io_reg_gpio[0] = {io_reg[1][11:0],io_reg[0][23:0]}; - assign out_ena[0] = {ddr_reg[1][11:0],ddr_reg[0][23:0]}; - assign od[0] = {od_reg[1][11:0],od_reg[0][23:0]}; - end - if (NumGPIO >= 2) begin - assign io_reg_gpio[1] = {io_reg[2][23:0],io_reg[1][23:12]}; - assign out_ena[1] = {ddr_reg[2][23:0],ddr_reg[1][23:12]}; - assign od[1] = {od_reg[2][23:0],od_reg[1][23:12]}; - end - if (NumGPIO >= 3) begin - assign io_reg_gpio[2] = {io_reg[4][11:0],io_reg[3][23:0]}; - assign out_ena[2] = {ddr_reg[4][11:0],ddr_reg[3][23:0]}; - assign od[2] = {od_reg[4][11:0],od_reg[3][23:0]}; - end - if (NumGPIO == 4) begin - assign io_reg_gpio[3] = {io_reg[5][23:0],io_reg[4][23:12]}; - assign out_ena[3] = {ddr_reg[5][23:0],ddr_reg[4][23:12]}; - assign od[3] = {od_reg[5][23:0],od_reg[4][23:12]}; - end - - endgenerate - - genvar ni,ps; - generate for(ni=0;ni= 1) begin - // Writes: - always @( posedge reset_in or posedge write_address) begin - if (reset_in) begin - hysteresis_reg <= 32'h11111111; - end - else if ( write_address ) begin - if (busaddress_r == 10'h0304) begin hysteresis_reg <= busdata_in_r; end - end - end -end -endgenerate - - genvar il; - generate - for(il=0;il=1) begin - bidir_io #(.IOWidth(GPIOWidth * NumGPIO),.PortNumWidth(PortNumWidth)) bidir_io_inst - ( - .clk(reg_clk), - .portselnum(portnumsel), - .out_ena({out_ena[1],out_ena[0]}) , // input out_ena_sig - .od({od[1],od[0]}) , // input od_sig - .out_data({iodatafromhm3[1][GPIOWidth-1:5],4'bz,charge, iodatafromhm3[0]}) , // input [IOIOWidth-1:0] out_data_sig - .gpioport({gpioport[1],gpioport[0]}) , // inout [IOIOWidth-1:0] gpioport_sig - .data_from_gpio({gpio_input_data[1],gpio_input_data[0]}) // output [IOIOWidth-1:0] read_data_sig - ); - end - else begin - bidir_io #(.IOWidth(GPIOWidth * NumGPIO),.PortNumWidth(PortNumWidth)) bidir_io_inst - ( - .clk(reg_clk), - .portselnum(portnumsel), - .out_ena({out_ena[1],out_ena[0]}) , // input out_ena_sig - .od({od[1],od[0]}) , // input od_sig - .out_data({iodatafromhm3[1], iodatafromhm3[0]}) , // input [IOIOWidth-1:0] out_data_sig - .gpioport({gpioport[1],gpioport[0]}) , // inout [IOIOWidth-1:0] gpioport_sig - .data_from_gpio({gpio_input_data[1],gpio_input_data[0]}) // output [IOIOWidth-1:0] read_data_sig - ); - end -endgenerate - // Read: - - integer oo,om,oi; - generate - - always @(posedge reset_in or posedge read_address)begin - if (reset_in)begin - busdata_to_cpu <= 32'b0; - end - else if (read_address) begin - if (Capsense >= 1) begin - if (adc_address_valid) begin busdata_to_cpu <= adc_data_out; end - else if (busaddress_r == 'h0300) begin busdata_to_cpu <= touched; end - else if (busaddress_r == 'h0304) begin busdata_to_cpu <= hysteresis_reg; end - else if(busaddress_r == 'h1000) begin busdata_to_cpu <= {8'b0,gpio_input_data[0][23:0]}; end - else if(busaddress_r == 'h1004) begin busdata_to_cpu <= {8'b0,gpio_input_data[1][11:0],gpio_input_data[0][35:24]}; end - else if(busaddress_r == 'h1008) begin busdata_to_cpu <= {8'b0,gpio_input_data[1][35:12]}; end -// else if(busaddress_r == 'h100c) begin busdata_to_cpu <= {8'b0,gpio_input_data[2][23:0]}; end -// else if(busaddress_r == 'h1010) begin busdata_to_cpu <= {8'b0,gpio_input_data[3][11:0],gpio_input_data[2][35:24]}; end -// else if(busaddress_r == 'h1014) begin busdata_to_cpu <= {8'b0,gpio_input_data[3][35:12]}; end -// else if ((busaddress_r >= 16'h1100) && (busaddress_r < 16'h1200)) begin - else if (ddr_address_valid || od_address_valid) begin - for(oo=0;oo= 16'h1100) && (busaddress_r < 16'h1200)) begin - else if (ddr_address_valid || od_address_valid) begin - for(oo=0;oo=1) begin - assign sense = gpio_input_data[1][5:1]; - - capsense capsense_inst - ( - .clk(reg_clk) , // input clk_sig - .reset(sense_reset) , // input reset_sig - .sense(sense) , // input [num-1:0] sense_sig - .hysteresis(hysteresis), - .calibval_0(calibval_0), - .counts_0(counts_0), - .charge(charge) , // output charge_sig - .touched(touched) // output [num-1:0] touched_sig - ); - - defparam capsense_inst.num = NumSense; - // States - defparam capsense_inst.CHARGE = 1; - defparam capsense_inst.DISCHARGE = 2; - // freqwuency in Mhz , times in us - defparam capsense_inst.clockfrequency = 200; - defparam capsense_inst.periodtime = 5; - end -endgenerate - -endmodule - +/* +// adc addresses: +// 0x0200 for start and status +// 0x0204 for data + +// +// cap sensor address: +// 0x0300 1 bit pr sensor (Data read) +// 0x0304 Hysteresis sens 0-7 (4-bit pr sensor) +// +// 0x1000 I/O port 0..23 +// 0x1004 I/O port 24..47 +// 0x1008 I/O port 48..71 +// 0x100C I/O port 72..95 +// 0x1010 I/O port 96..127 +// 0x1014 I/O port 128..143 + +// 0x1100 DDR for I/O port 0..23 +// 0x1104 DDR for I/O port 24..47 +// 0x1108 DDR for I/O port 48..71 +// 0x110C DDR for I/O port 72..95 +// 0x1110 DDR for I/O port 96..127 +// 0x1114 DDR for I/O port 128..144 +// '1' bit in DDR register makes corresponding GPIO bit an output +// +// 0x1120 Portnums for I/O port 0..3 +// 0x1124 Portnums for I/O port 4..7 +// 0x1128 Portnums for I/O port 8..11 +// 0x112C Portnums for I/O port 12..15 +// 0x1130 Portnums for I/O port 16..19 +// 0x1134 Portnums for I/O port 20..23 +// +// 0x1300 OpenDrainSelect for I/O port 0..23 +// 0x1304 OpenDrainSelect for I/O port 24..47 +// 0x1308 OpenDrainSelect for I/O port 48..71 +// 0x130C OpenDrainSelect for I/O port 72..95 +// 0x1310 OpenDrainSelect for I/O port 96..127 +// 0x1314 OpenDrainSelect for I/O port 128..143 +// '1' bit in OpenDrainSelect register makes corresponding GPIO an +// open drain output. +// If OpenDrain is selected for an I/O bit , the DDR register is ignored. +*/ + +module gpio_adr_decoder_reg( + input CLOCK, + input reg_clk, + input reset_reg_N, + input chip_sel, + input write_reg, + input read_reg, + input [AddrWidth-1:2] busaddress, + input [BusWidth-1:0] busdata_in, + input [MuxGPIOIOWidth-1:0] iodatafromhm3[NumGPIO-1:0], + input [BusWidth-1:0] busdata_fromhm2, +// + inout [GPIOWidth-1:0] gpioport[NumGPIO-1:0], +// + output reg [MuxGPIOIOWidth-1:0] iodatatohm3[NumGPIO-1:0], + output reg [BusWidth-1:0] busdata_to_cpu, +// adc interface + input adc_clk, // max 40mhz + output ADC_CONVST_o, + output ADC_SCK_o, + output ADC_SDI_o, + input ADC_SDO_i, +// Touch sensor: + output [11:0] calibval_0, + output [13:0] counts_0, + output [NumSense-1:0] touched, + input [1:0] buttons +); + +parameter AddrWidth = 16; +parameter BusWidth = 32; +parameter GPIOWidth = 36; +parameter MuxGPIOIOWidth = 36; +parameter NumIOAddrReg = 6; +parameter NumGPIO = 2; + +parameter Capsense = 1; +parameter NumSense = 4; +parameter ADC = ""; +// local param +parameter IoRegWidth = 24; +parameter AdcOutShift = 2; +parameter ReadInShift = 2; +parameter WriteInShift = 2; +parameter PortNumWidth = 8; +parameter NumPinsPrIOAddr = 4; +parameter Mux_regPrIOReg = 6; +parameter TotalNumregs = Mux_regPrIOReg * NumIOAddrReg * NumPinsPrIOAddr; + + wire reset_in = ~reset_reg_N; + wire [GPIOWidth-1:0] gpio_input_data[NumGPIO-1:0]; + + + reg [ReadInShift:0] read_reg_r; + reg [WriteInShift:0] write_reg_r; + reg [AddrWidth-1:0] busaddress_r; + reg [BusWidth-1:0] busdata_in_r; + reg [MuxGPIOIOWidth-1:0] iodatafromhm3_r[NumGPIO-1:0]; + + reg [AddrWidth-1:0] local_address_r; + + reg [IoRegWidth-1:0] io_reg[NumIOAddrReg-1:0]; + reg [IoRegWidth-1:0] od_reg[NumIOAddrReg-1:0]; + reg [IoRegWidth-1:0] ddr_reg[NumIOAddrReg-1:0]; + + reg [BusWidth-1:0] mux_reg[NumIOAddrReg-1:0][Mux_regPrIOReg-1:0]; + + reg [PortNumWidth-1:0] portselnum[TotalNumregs-1:0]; + + + wire [GPIOWidth-1:0] io_reg_gpio[NumGPIO-1:0]; + wire [PortNumWidth-1:0] mux_reg_index; + wire [4:0] mux_reg_addr; + wire [1:0] mux_reg_byte; + + wire [GPIOWidth-1:0] out_ena[NumGPIO-1:0]; + wire [GPIOWidth-1:0] od[NumGPIO-1:0]; + + wire [PortNumWidth-1:0] portnumsel[(GPIOWidth * NumGPIO)-1:0]; + + wire read_address = read_reg_r[ReadInShift]; + reg write_address; + +// wire io_address_valid = ((busaddress_r >= 16'h1000) && (busaddress_r < 16'h1020)) ? 1'b1 : 1'b0; + wire ddr_address_valid = ((busaddress_r >= 16'h1100) && (busaddress_r < 16'h1120)) ? 1'b1 : 1'b0; + wire mux_address_valid = ((busaddress_r >= 16'h1120) && (busaddress_r < 16'h1200)) ? 1'b1 : 1'b0; + wire od_address_valid = ((busaddress_r >= 16'h1300) && (busaddress_r < 16'h1320)) ? 1'b1 : 1'b0; + +// wire io_read_valid = (io_address_valid && read_address) ? 1'b1 : 1'b0; +// wire ddr_read_valid = (ddr_address_valid && read_address) ? 1'b1 : 1'b0; + wire mux_read_valid = (mux_address_valid && read_address) ? 1'b1 : 1'b0; +// wire od_read_valid = (od_address_valid && read_address) ? 1'b1 : 1'b0; + +// wire io_write_valid = (io_address_valid && write_address) ? 1'b1 : 1'b0; +// wire ddr_write_valid = (ddr_address_valid && write_address) ? 1'b1 : 1'b0; + wire mux_write_valid = (mux_address_valid && write_address) ? 1'b1 : 1'b0; +// wire od_write_valid = (od_address_valid && write_address) ? 1'b1 : 1'b0; + +// ADC module: + wire adc_address_valid = ( (busaddress_r >= 16'h0200) && (busaddress_r <= 16'h0204)) ? 1'b1 : 1'b0; + wire adc_read_valid = (adc_address_valid && read_reg) ? 1'b1 : 1'b0; + wire adc_write_valid = (adc_address_valid && write_address) ? 1'b1 : 1'b0; + wire [31:0]adc_data_out; + +// Touch sensor: + wire [NumSense-1:0] sense; + wire charge; + reg [BusWidth-1:0] hysteresis_reg; + wire [3:0] hysteresis[NumSense-1:0]; + + wire sense_reset = ~reset_reg_N | ~buttons[1]; + + genvar sh; + generate + for(sh=0;sh= 1) begin + assign io_reg_gpio[0] = {io_reg[1][11:0],io_reg[0][23:0]}; + assign out_ena[0] = {ddr_reg[1][11:0],ddr_reg[0][23:0]}; + assign od[0] = {od_reg[1][11:0],od_reg[0][23:0]}; + end + if (NumGPIO >= 2) begin + assign io_reg_gpio[1] = {io_reg[2][23:0],io_reg[1][23:12]}; + assign out_ena[1] = {ddr_reg[2][23:0],ddr_reg[1][23:12]}; + assign od[1] = {od_reg[2][23:0],od_reg[1][23:12]}; + end + if (NumGPIO >= 3) begin + assign io_reg_gpio[2] = {io_reg[4][11:0],io_reg[3][23:0]}; + assign out_ena[2] = {ddr_reg[4][11:0],ddr_reg[3][23:0]}; + assign od[2] = {od_reg[4][11:0],od_reg[3][23:0]}; + end + if (NumGPIO == 4) begin + assign io_reg_gpio[3] = {io_reg[5][23:0],io_reg[4][23:12]}; + assign out_ena[3] = {ddr_reg[5][23:0],ddr_reg[4][23:12]}; + assign od[3] = {od_reg[5][23:0],od_reg[4][23:12]}; + end + + endgenerate + + genvar ni,ps; + generate for(ni=0;ni= 1) begin + // Writes: + always @( posedge reset_in or posedge write_address) begin + if (reset_in) begin + hysteresis_reg <= 32'h11111111; + end + else if ( write_address ) begin + if (busaddress_r == 10'h0304) begin hysteresis_reg <= busdata_in_r; end + end + end +end +endgenerate + + genvar il; + generate + for(il=0;il=1) begin + bidir_io #(.IOWidth(GPIOWidth * NumGPIO),.PortNumWidth(PortNumWidth)) bidir_io_inst + ( + .clk(reg_clk), + .portselnum(portnumsel), + .out_ena({out_ena[1],out_ena[0]}) , // input out_ena_sig + .od({od[1],od[0]}) , // input od_sig + .out_data({iodatafromhm3[1][GPIOWidth-1:5],4'bz,charge, iodatafromhm3[0]}) , // input [IOIOWidth-1:0] out_data_sig + .gpioport({gpioport[1],gpioport[0]}) , // inout [IOIOWidth-1:0] gpioport_sig + .data_from_gpio({gpio_input_data[1],gpio_input_data[0]}) // output [IOIOWidth-1:0] read_data_sig + ); + end + else begin + bidir_io #(.IOWidth(GPIOWidth * NumGPIO),.PortNumWidth(PortNumWidth)) bidir_io_inst + ( + .clk(reg_clk), + .portselnum(portnumsel), + .out_ena({out_ena[1],out_ena[0]}) , // input out_ena_sig + .od({od[1],od[0]}) , // input od_sig + .out_data({iodatafromhm3[1], iodatafromhm3[0]}) , // input [IOIOWidth-1:0] out_data_sig + .gpioport({gpioport[1],gpioport[0]}) , // inout [IOIOWidth-1:0] gpioport_sig + .data_from_gpio({gpio_input_data[1],gpio_input_data[0]}) // output [IOIOWidth-1:0] read_data_sig + ); + end +endgenerate + // Read: + + integer oo,om,oi; + generate + + always @(posedge reset_in or posedge read_address)begin + if (reset_in)begin + busdata_to_cpu <= 32'b0; + end + else if (read_address) begin + if (Capsense >= 1) begin + if (adc_address_valid) begin busdata_to_cpu <= adc_data_out; end + else if (busaddress_r == 'h0300) begin busdata_to_cpu <= touched; end + else if (busaddress_r == 'h0304) begin busdata_to_cpu <= hysteresis_reg; end + else if(busaddress_r == 'h1000) begin busdata_to_cpu <= {8'b0,gpio_input_data[0][23:0]}; end + else if(busaddress_r == 'h1004) begin busdata_to_cpu <= {8'b0,gpio_input_data[1][11:0],gpio_input_data[0][35:24]}; end + else if(busaddress_r == 'h1008) begin busdata_to_cpu <= {8'b0,gpio_input_data[1][35:12]}; end +// else if(busaddress_r == 'h100c) begin busdata_to_cpu <= {8'b0,gpio_input_data[2][23:0]}; end +// else if(busaddress_r == 'h1010) begin busdata_to_cpu <= {8'b0,gpio_input_data[3][11:0],gpio_input_data[2][35:24]}; end +// else if(busaddress_r == 'h1014) begin busdata_to_cpu <= {8'b0,gpio_input_data[3][35:12]}; end +// else if ((busaddress_r >= 16'h1100) && (busaddress_r < 16'h1200)) begin + else if (ddr_address_valid || od_address_valid) begin + for(oo=0;oo= 16'h1100) && (busaddress_r < 16'h1200)) begin + else if (ddr_address_valid || od_address_valid) begin + for(oo=0;oo=1) begin + assign sense = gpio_input_data[1][5:1]; + + capsense capsense_inst + ( + .clk(reg_clk) , // input clk_sig + .reset(sense_reset) , // input reset_sig + .sense(sense) , // input [num-1:0] sense_sig + .hysteresis(hysteresis), + .calibval_0(calibval_0), + .counts_0(counts_0), + .charge(charge) , // output charge_sig + .touched(touched) // output [num-1:0] touched_sig + ); + + defparam capsense_inst.num = NumSense; + // States + defparam capsense_inst.CHARGE = 1; + defparam capsense_inst.DISCHARGE = 2; + // freqwuency in Mhz , times in us + defparam capsense_inst.clockfrequency = 200; + defparam capsense_inst.periodtime = 5; + end +endgenerate + +endmodule + diff --git a/HW/QuartusProjects/DE0_Nano_SoC_Cramps/DE0_Nano_SoC_Cramps.sv b/HW/QuartusProjects/DE0_Nano_SoC_Cramps/DE0_Nano_SoC_Cramps.sv index a74097be..cbd89767 100644 --- a/HW/QuartusProjects/DE0_Nano_SoC_Cramps/DE0_Nano_SoC_Cramps.sv +++ b/HW/QuartusProjects/DE0_Nano_SoC_Cramps/DE0_Nano_SoC_Cramps.sv @@ -31,96 +31,98 @@ //Date: Tue Dec 2 09:28:38 2014 // ============================================================================ -`define ENABLE_HPS -//`define ENABLE_CLK - module DE0_Nano_SoC_Cramps( - ///////// ADC ///////// - output ADC_CONVST, - output ADC_SCK, - output ADC_SDI, - input ADC_SDO, - - ///////// ARDUINO ///////// - inout [15:0] ARDUINO_IO, - inout ARDUINO_RESET_N, - -`ifdef ENABLE_CLK - ///////// CLK ///////// - output CLK_I2C_SCL, - inout CLK_I2C_SDA, -`endif /*ENABLE_CLK*/ - - ///////// FPGA ///////// - input FPGA_CLK1_50, - input FPGA_CLK2_50, - input FPGA_CLK3_50, - - ///////// GPIO ///////// - inout [35:0] GPIO[1:0], - -`ifdef ENABLE_HPS - ///////// HPS ///////// - inout HPS_CONV_USB_N, - output [14:0] HPS_DDR3_ADDR, - output [2:0] HPS_DDR3_BA, - output HPS_DDR3_CAS_N, - output HPS_DDR3_CKE, - output HPS_DDR3_CK_N, - output HPS_DDR3_CK_P, - output HPS_DDR3_CS_N, - output [3:0] HPS_DDR3_DM, - inout [31:0] HPS_DDR3_DQ, - inout [3:0] HPS_DDR3_DQS_N, - inout [3:0] HPS_DDR3_DQS_P, - output HPS_DDR3_ODT, - output HPS_DDR3_RAS_N, - output HPS_DDR3_RESET_N, - input HPS_DDR3_RZQ, - output HPS_DDR3_WE_N, - output HPS_ENET_GTX_CLK, - inout HPS_ENET_INT_N, - output HPS_ENET_MDC, - inout HPS_ENET_MDIO, - input HPS_ENET_RX_CLK, - input [3:0] HPS_ENET_RX_DATA, - input HPS_ENET_RX_DV, - output [3:0] HPS_ENET_TX_DATA, - output HPS_ENET_TX_EN, - inout HPS_GSENSOR_INT, - inout HPS_I2C0_SCLK, - inout HPS_I2C0_SDAT, - inout HPS_I2C1_SCLK, - inout HPS_I2C1_SDAT, - inout HPS_KEY, - inout HPS_LED, - inout HPS_LTC_GPIO, - output HPS_SD_CLK, - inout HPS_SD_CMD, - inout [3:0] HPS_SD_DATA, - output HPS_SPIM_CLK, - input HPS_SPIM_MISO, - output HPS_SPIM_MOSI, - inout HPS_SPIM_SS, - input HPS_UART_RX, - output HPS_UART_TX, - input HPS_USB_CLKOUT, - inout [7:0] HPS_USB_DATA, - input HPS_USB_DIR, - input HPS_USB_NXT, - output HPS_USB_STP, - -`endif /*ENABLE_HPS*/ - - ///////// KEY ///////// - input [1:0] KEY, - - ///////// LED ///////// - output [7:0] LED, - - ///////// SW ///////// - input [3:0] SW + ///////// ADC ///////// + output ADC_CONVST, + output ADC_SCK, + output ADC_SDI, + input ADC_SDO, + + ///////// ARDUINO ///////// + inout [15:0] ARDUINO_IO, + inout ARDUINO_RESET_N, + + ///////// CLOCK ////////// + input FPGA_CLK1_50, + input FPGA_CLK2_50, + input FPGA_CLK3_50, + + + output CLK_I2C_SCL, + inout CLK_I2C_SDA, + + + + + + + + + + + + ///////// HPS ////////// + inout HPS_CONV_USB_N, + output [14:0] HPS_DDR3_ADDR, + output [2:0] HPS_DDR3_BA, + output HPS_DDR3_CAS_N, + output HPS_DDR3_CKE, + output HPS_DDR3_CK_N, + output HPS_DDR3_CK_P, + output HPS_DDR3_CS_N, + output [3:0] HPS_DDR3_DM, + inout [31:0] HPS_DDR3_DQ, + inout [3:0] HPS_DDR3_DQS_N, + inout [3:0] HPS_DDR3_DQS_P, + output HPS_DDR3_ODT, + output HPS_DDR3_RAS_N, + output HPS_DDR3_RESET_N, + input HPS_DDR3_RZQ, + output HPS_DDR3_WE_N, + output HPS_ENET_GTX_CLK, + inout HPS_ENET_INT_N, + output HPS_ENET_MDC, + inout HPS_ENET_MDIO, + input HPS_ENET_RX_CLK, + input [3:0] HPS_ENET_RX_DATA, + input HPS_ENET_RX_DV, + output [3:0] HPS_ENET_TX_DATA, + output HPS_ENET_TX_EN, + inout HPS_GSENSOR_INT, + inout HPS_I2C0_SCLK, + inout HPS_I2C0_SDAT, + inout HPS_I2C1_SCLK, + inout HPS_I2C1_SDAT, + inout HPS_KEY, + inout HPS_LED, + inout HPS_LTC_GPIO, + output HPS_SD_CLK, + inout HPS_SD_CMD, + inout [3:0] HPS_SD_DATA, + output HPS_SPIM_CLK, + input HPS_SPIM_MISO, + output HPS_SPIM_MOSI, + inout HPS_SPIM_SS, + input HPS_UART_RX, + output HPS_UART_TX, + input HPS_USB_CLKOUT, + inout [7:0] HPS_USB_DATA, + input HPS_USB_DIR, + input HPS_USB_NXT, + output HPS_USB_STP, + + ///////// KEY ///////// + input [1:0] KEY, + + ///////// LED ///////// + output [7:0] LED, + + ///////// SW ///////// + input [3:0] SW, + + ///////// GPIO ///////// + inout [35:0] GPIO[1:0] ); //======================================================= @@ -130,14 +132,8 @@ module DE0_Nano_SoC_Cramps( import boardtype::*; parameter NumIOAddrReg = 6; -//--------- moved to include file -----------// -// parameter GPIOWidth = 36; -// parameter NumGPIO = 2; -// parameter MuxGPIOIOWidth = IOWidth/NumGPIO; -//-------------------------------------------// - - wire hps_fpga_reset_n; - wire [1:0] fpga_debounced_buttons; + wire hps_fpga_reset_n; + wire [1:0] fpga_debounced_buttons; wire [6:0] fpga_led_internal; // wire [2:0] hps_reset_req; wire hps_cold_reset; @@ -145,6 +141,9 @@ parameter NumIOAddrReg = 6; wire hps_debug_reset; // wire [27:0] stm_hw_events; wire fpga_clk_50; + + + // connection of internal logics assign LED[5:1] = fpga_led_internal; assign fpga_clk_50 = FPGA_CLK1_50; @@ -177,25 +176,35 @@ parameter NumIOAddrReg = 6; wire int_sig; assign ARDUINO_IO[15] = int_sig; -// tri [IOWidth-1:0] hm2_iobits_sig; -// tri [LEDCount-1:0] hm2_leds_sig; - -// assign GPIO_0[IOWidth-1:0] = hm2_iobits_sig; - //======================================================= // Structural coding //======================================================= -// assign ARDUINO_IO[8:0] = out_oe[8:0] ? out_data[8:0] : 1'bz; -// assign ARDUINO_IO[10:9] = ar_out_oe ? ar_in_sig : 1'bz; -// assign out_oe = 9'b1; -// assign ar_out_oe = 2'b0; + + + + + + + + soc_system u0 ( //Clock&Reset .clk_clk (fpga_clk_50 ), // clk.clk .reset_reset_n (hps_fpga_reset_n ), // reset.reset_n + + + + + + + + + + + //HPS ddr3 .memory_mem_a ( HPS_DDR3_ADDR), // memory.mem_a .memory_mem_ba ( HPS_DDR3_BA), // .mem_ba @@ -274,10 +283,6 @@ soc_system u0 ( .dipsw_pio_export ( SW ), // dipsw_pio_external_connection.export .button_pio_export ( fpga_debounced_buttons ), // button_pio_external_connection.export .hps_0_h2f_reset_reset_n ( hps_fpga_reset_n ), // hps_0_h2f_reset.reset_n -// .hps_0_f2h_cold_reset_req_reset_n (~hps_cold_reset ), // hps_0_f2h_cold_reset_req.reset_n -// .hps_0_f2h_debug_reset_req_reset_n (~hps_debug_reset ), // hps_0_f2h_debug_reset_req.reset_n -// .hps_0_f2h_stm_hw_events_stm_hwevents (stm_hw_events ), // hps_0_f2h_stm_hw_events.stm_hwevents -// .hps_0_f2h_warm_reset_req_reset_n (~hps_warm_reset ), // hps_0_f2h_warm_reset_req.reset_n // hm2reg_io_0_conduit .mk_io_hm2_datain (busdata_out), // .hm2_datain .mk_io_hm2_dataout (hm_datai), // hm2reg.hm2_dataout @@ -289,65 +294,55 @@ soc_system u0 ( .clk_100mhz_out_clk (hm_clk_med), // clk_100mhz_out.clk .clk_200mhz_out_clk (hm_clk_high), // clk_100mhz_out.clk .adc_clk_40mhz_clk (adc_clk_40) // adc_clk_40mhz.clk - ); +); top_io_modules top_io_modules_inst ( - .clk(fpga_clk_50) , // input clk_sig - .reset_n(hps_fpga_reset_n) , // input reset_n_sig - .button_in(KEY) , // input [KEY_WIDTH-1:0] button_in_sig - .button_out(fpga_debounced_buttons) , // output [KEY_WIDTH-1:0] button_out_sig -// .hps_cold_reset(hps_cold_reset) , // output hps_cold_reset_sig -// .hps_warm_reset(hps_warm_reset) , // output hps_warm_reset_sig -// .hps_debug_reset(hps_debug_reset) , // output hps_debug_reset_sig - .LED(LED[0]) // output LED_sig + .clk(fpga_clk_50) , // input clk_sig + .reset_n(hps_fpga_reset_n) , // input reset_n_sig + .button_in(KEY) , // input [KEY_WIDTH-1:0] button_in_sig + .button_out(fpga_debounced_buttons) , // output [KEY_WIDTH-1:0] button_out_sig + .LED(LED[0]) // output LED_sig ); defparam top_io_modules_inst.KEY_WIDTH = 2; // Mesa code ------------------------------------------------------// -//assign clklow_sig = fpga_clk_50; assign clkhigh_sig = hm_clk_high; assign clkmed_sig = hm_clk_med; genvar ig; generate for(ig=0;ig A(AddrWidth-1 downto 2), - .readstb(hm_read ) , // input readstb_sig - .writestb(hm_write) , // input writestb_sig - - .clklow(fpga_clk_50) , // input clklow_sig -- PCI clock --> all - .clkmed(clkmed_sig) , // input clkmed_sig -- Processor clock --> sserialwa, twiddle - .clkhigh(clkhigh_sig) , // input clkhigh_sig -- High speed clock --> most - .intirq(int_sig) , // output int_sig --int => LINT, ---> PCI ? -// .dreq(dreq_sig) , // output dreq_sig -// .demandmode(demandmode_sig) , // output demandmode_sig - .iobitsouttop(hm2_bitsout_sig) , // inout [IOWidth-1:0] --iobits => IOBITS,-- external I/O bits - .iobitsintop(hm2_bitsin_sig) // inout [IOWidth-1:0] --iobits => IOBITS,-- external I/O bits + .ibustop(hm_datai) , // input [buswidth-1:0] ibus_sig + .obustop(hm_datao) , // output [buswidth-1:0] obus_sig + .addr(hm_address) , // input [addrwidth-1:2] addr_sig -- addr => A(AddrWidth-1 downto 2), + .readstb(hm_read ) , // input readstb_sig + .writestb(hm_write) , // input writestb_sig + + .clklow(fpga_clk_50) , // input clklow_sig -- PCI clock --> all + .clkmed(clkmed_sig) , // input clkmed_sig -- Processor clock --> sserialwa, twiddle + .clkhigh(clkhigh_sig) , // input clkhigh_sig -- High speed clock --> most + .intirq(int_sig) , // output int_sig --int => LINT, ---> PCI ? + .iobitsouttop(hm2_bitsout_sig) , // inout [IOWidth-1:0] --iobits => IOBITS,-- external I/O bits + .iobitsintop(hm2_bitsin_sig) // inout [IOWidth-1:0] --iobits => IOBITS,-- external I/O bits // .liobits(liobits_sig) , // inout [lIOWidth-1:0] --liobits_sig -// .rates(rates_sig) , // output [4:0] rates_sig // .leds(hm2_leds_sig) // output [ledcount-1:0] leds_sig --leds => LEDS ); diff --git a/HW/QuartusProjects/DE0_Nano_SoC_Cramps/firmware_id.mif b/HW/QuartusProjects/DE0_Nano_SoC_Cramps/firmware_id.mif new file mode 100644 index 00000000..bffb805b --- /dev/null +++ b/HW/QuartusProjects/DE0_Nano_SoC_Cramps/firmware_id.mif @@ -0,0 +1,71 @@ +% +config argument: DE0_Nano_SoC_Cramps + +size of encoded message: 117 0x75 +text format representation: +--- +build_sha: "26d422a" +fpga_part_number: "altera socfpga" +connector { + name: "GPIO0.P0" + pins: 24 +} +connector { + name: "GPIO0.P1" + pins: 24 +} +connector { + name: "GPIO0.P2" + pins: 24 +} +num_leds: 0 +board_name: "Terasic DE0-Nano" +comment: "$BUILD_URL unset" +--- + +wire format length=117 0a0732366434323261120e616c7465726120736f63667067611a0f0a084750494f302e503015180000001a0f0a084750494f302e503115180000001a0f0a084750494f302e5032151800000025000000002a1054657261736963204445302d4e616e6f3210244255494c445f55524c20756e736574 + +size of MIF struct including cookie and length field: 125 +% + + +WIDTH=32; +DEPTH=32; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + 0000 : feedbabe; + 0001 : 00000075; + 0002 : 3632070a; + 0003 : 32323464; + 0004 : 610e1261; + 0005 : 7265746c; + 0006 : 6f732061; + 0007 : 67706663; + 0008 : 0a0f1a61; + 0009 : 49504708; + 000a : 502e304f; + 000b : 00181530; + 000c : 0f1a0000; + 000d : 5047080a; + 000e : 2e304f49; + 000f : 18153150; + 0010 : 1a000000; + 0011 : 47080a0f; + 0012 : 304f4950; + 0013 : 1532502e; + 0014 : 00000018; + 0015 : 00000025; + 0016 : 54102a00; + 0017 : 73617265; + 0018 : 44206369; + 0019 : 4e2d3045; + 001a : 326f6e61; + 001b : 55422410; + 001c : 5f444c49; + 001d : 204c5255; + 001e : 65736e75; + 001f : 00000074; +END; diff --git a/HW/QuartusProjects/DE0_Nano_SoC_Cramps/hm3_DE0_Nano_SoC.qip b/HW/QuartusProjects/DE0_Nano_SoC_Cramps/hm3_DE0_Nano_SoC.qip new file mode 100644 index 00000000..68322e50 --- /dev/null +++ b/HW/QuartusProjects/DE0_Nano_SoC_Cramps/hm3_DE0_Nano_SoC.qip @@ -0,0 +1,2 @@ +set_global_assignment -name VHDL_FILE ../../hm2/config/DE0_Nano_SoC_Cramps/hostmot3_cfg.vhd +set_global_assignment -name SYSTEMVERILOG_FILE ../../hm2/config/DE0_Nano_SoC_Cramps/atlas_3x24_cap.sv diff --git a/HW/QuartusProjects/DE0_Nano_SoC_Cramps/hm3_pin_config.qip b/HW/QuartusProjects/DE0_Nano_SoC_Cramps/hm3_pin_config.qip new file mode 100644 index 00000000..c663e10b --- /dev/null +++ b/HW/QuartusProjects/DE0_Nano_SoC_Cramps/hm3_pin_config.qip @@ -0,0 +1,2 @@ +# I/O Daughterboard adaptor specific: +set_global_assignment -name VHDL_FILE ../../hm2/config/DE0_Nano_SoC_Cramps/PIN_3x24_cap.vhd -library pin diff --git a/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system.qsys b/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system.qsys index 9de94339..355027df 100644 --- a/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system.qsys +++ b/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system.qsys @@ -13,7 +13,7 @@ { datum _sortIndex { - value = "10"; + value = "11"; type = "int"; } } @@ -42,7 +42,7 @@ { datum _sortIndex { - value = "9"; + value = "10"; type = "int"; } } @@ -71,7 +71,7 @@ { datum _sortIndex { - value = "3"; + value = "4"; type = "int"; } } @@ -79,7 +79,7 @@ { datum _sortIndex { - value = "12"; + value = "13"; type = "int"; } } @@ -100,7 +100,7 @@ { datum _sortIndex { - value = "1"; + value = "2"; type = "int"; } } @@ -116,7 +116,7 @@ { datum _sortIndex { - value = "2"; + value = "3"; type = "int"; } } @@ -124,7 +124,7 @@ { datum _sortIndex { - value = "5"; + value = "6"; type = "int"; } } @@ -150,7 +150,7 @@ { datum _sortIndex { - value = "7"; + value = "8"; type = "int"; } } @@ -171,7 +171,7 @@ { datum _sortIndex { - value = "8"; + value = "9"; type = "int"; } } @@ -192,7 +192,7 @@ { datum _sortIndex { - value = "4"; + value = "5"; type = "int"; } } @@ -208,7 +208,7 @@ { datum _sortIndex { - value = "11"; + value = "12"; type = "int"; } } @@ -225,6 +225,14 @@ type = "String"; } } + element pll_0 + { + datum _sortIndex + { + value = "1"; + type = "int"; + } + } element soc_system { datum _originalDeviceFamily @@ -365,7 +373,7 @@ { datum _sortIndex { - value = "6"; + value = "7"; type = "int"; } } @@ -405,7 +413,7 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Create an adjpllin signal to connect with an upstream PLL + + + + + + + + + + + + + + + + + + + + + + + + Automatic Switchover + + + + + + - + @@ -1291,7 +1291,7 @@ - + diff --git a/HW/hm2/config/DE0_Nano_SoC_Cramps/PIN_3x24_cap_enc.vhd b/HW/hm2/config/DE0_Nano_SoC_Cramps/PIN_3x24_cap_enc.vhd new file mode 100644 index 00000000..90c96022 --- /dev/null +++ b/HW/hm2/config/DE0_Nano_SoC_Cramps/PIN_3x24_cap_enc.vhd @@ -0,0 +1,200 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics +-- http://www.mesanet.com +-- +-- This program is is licensed under a disjunctive dual license giving you +-- the choice of one of the two following sets of free software/open source +-- licensing terms: +-- +-- * GNU General Public License (GPL), version 2.0 or later +-- * 3-clause BSD License +-- +-- +-- The GNU GPL License: +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- +-- +-- The 3-clause BSD License: +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- * Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- * Neither the name of Mesa Electronics nor the names of its +-- contributors may be used to endorse or promote products +-- derived from this software without specific prior written +-- permission. +-- +-- +-- Disclaimer: +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- + +use work.IDROMConst.all; + +package Pintypes is + constant ModuleID : ModuleIDType :=( + -- GTag Version Clock NumInst BaseAddr NumRegisters Strides MultiRegs + (HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask), + (WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask), + (IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask), + (QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask), + (StepGenTag, x"02", ClockLowTag, x"0A", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask), + (PWMTag, x"00", ClockHighTag, x"06", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask), + (LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask), + (NANOADCTag, x"00", ClockLowTag, x"08", NANOADCAddr&PadT, NANOADCNumRegs, x"00", NANOADCBitMask), + (CAPSENSETag, x"00", ClockLowTag, x"04", CAPSENSEAddr&PadT, CAPSENSENumRegs, x"00", CAPSENSEBitMask), + (FWIDTag, x"00", ClockLowTag, x"01", FWIDAddr&PadT, FWIDNumRegs, x"00", FWIDMPBitMask), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000") + ); + + + constant PinDesc : PinDescType :=( +-- Base Sec Sec Sec +-- func unit func pin -- hostmot2 DE0-Nano pin Function + IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 00 GPIO_0 01 01 X Step + IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 01 GPIO_0 02 02 X Dir + IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 02 GPIO_0 03 03 Y Step + IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 03 GPIO_0 04 04 Y Dir + IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 04 GPIO_0 05 05 Z Step + IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 05 GPIO_0 06 06 Z Dir + IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 06 GPIO_0 07 07 E0 Step + IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 07 GPIO_0 08 08 E0 Dir + IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 08 GPIO_0 09 09 E1 Step + IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 09 GPIO_0 10 10 E1 Dir + IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 10 GPIO_0 11 13 E2 Step + IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 11 GPIO_0 12 14 E2 Dir + IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 12 GPIO_0 13 15 U Step + IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 13 GPIO_0 14 16 U Dir + IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 14 GPIO_0 15 17 V Step + IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 15 GPIO_0 16 18 V Dir + IOPortTag & x"08" & StepGenTag & StepGenStepPin, -- I/O 16 GPIO_0 17 19 W Step + IOPortTag & x"08" & StepGenTag & StepGenDirPin, -- I/O 17 GPIO_0 18 20 W Dir + IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 18 GPIO_0 19 21 Spindle DAC PWM + IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 19 GPIO_0 20 22 Spindle DAC PWM + IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 20 GPIO_0 21 23 Spindle DAC PWM + IOPortTag & x"03" & PWMTag & PWMAOutPin, -- I/O 21 GPIO_0 22 24 Spindle DAC PWM + IOPortTag & x"04" & PWMTag & PWMAOutPin, -- I/O 22 GPIO_0 23 25 Spindle DAC PWM + IOPortTag & x"05" & PWMTag & PWMAOutPin, -- I/O 23 GPIO_0 24 26 Spindle DAC PWM + IOPortTag & x"00" & NullTag & NullPin, -- I/O 24 GPIO_0 25 27 Limit X-Min + IOPortTag & x"00" & NullTag & NullPin, -- I/O 25 GPIO_0 26 28 Limit X-Max + IOPortTag & x"00" & NullTag & NullPin, -- I/O 26 GPIO_0 27 31 Limit Y-Min + IOPortTag & x"00" & NullTag & NullPin, -- I/O 27 GPIO_0 27 32 Limit Y-Max + IOPortTag & x"00" & NullTag & NullPin, -- I/O 28 GPIO_0 29 33 Limit Z-Min + IOPortTag & x"00" & NullTag & NullPin, -- I/O 29 GPIO_0 30 34 Limit Z-Max + IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 GPIO_0 31 35 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 31 GPIO_0 32 36 Led + IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 GPIO_0 33 37 Axis_ENA_n + IOPortTag & x"00" & NullTag & NullPin, -- I/O 33 GPIO_0 34 38 Machine_Pwr + IOPortTag & x"00" & NullTag & NullPin, -- I/O 34 GPIO_0 35 39 Estop (In) + IOPortTag & x"00" & NullTag & NullPin, -- I/O 35 GPIO_0 36 40 Estop_Sw + +-- Base Sec Sec Sec +-- func unit func pin -- hostmot2 DE0-Nano pin Function + IOPortTag & x"00" & CAPSENSETag & CapChargePin, -- I/O 36 GPIO_1 01 01 CapSense charge + IOPortTag & x"00" & CAPSENSETag & CapSensePin0, -- I/O 37 GPIO_1 02 02 CapSense sense 0 + IOPortTag & x"00" & CAPSENSETag & CapSensePin1, -- I/O 38 GPIO_1 03 03 CapSense sense 1 + IOPortTag & x"00" & CAPSENSETag & CapSensePin2, -- I/O 39 GPIO_1 04 04 CapSense sense 2 + IOPortTag & x"00" & CAPSENSETag & CapSensePin3, -- I/O 40 GPIO_1 05 05 CapSense sense 3 + IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 41 GPIO_1 06 06 Encoder Z + IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 42 GPIO_1 07 07 Encoder B + IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 43 GPIO_1 08 08 Encoder A + IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 44 GPIO_1 09 09 Encoder Z + IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 45 GPIO_1 10 10 Encoder B + IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 46 GPIO_1 11 13 Encoder A + IOPortTag & x"00" & NullTag & NullPin, -- I/O 47 GPIO_1 12 14 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 48 GPIO_1 13 15 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 49 GPIO_1 14 16 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 50 GPIO_1 15 17 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 51 GPIO_1 16 18 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 52 GPIO_1 17 19 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 53 GPIO_1 18 20 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 54 GPIO_1 19 21 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 55 GPIO_1 20 22 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 56 GPIO_1 21 23 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 57 GPIO_1 22 24 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 58 GPIO_1 23 25 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 59 GPIO_1 24 26 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 60 GPIO_1 25 27 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 61 GPIO_1 26 28 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 62 GPIO_1 27 31 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 63 GPIO_1 28 32 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 64 GPIO_1 29 33 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 65 GPIO_1 30 34 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 66 GPIO_1 31 35 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 67 GPIO_1 32 36 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 68 GPIO_1 33 37 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 69 GPIO_1 34 38 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 70 GPIO_1 35 39 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 71 GPIO_1 36 40 just GPIO + + -- Remainder of 144 pin descriptors are unused + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin); + +end package Pintypes; --PIN_Cramps_3x24_dpll_irq diff --git a/HW/hm2/config/DE0_Nano_SoC_Cramps/atlas_3x24_cap_enc.sv b/HW/hm2/config/DE0_Nano_SoC_Cramps/atlas_3x24_cap_enc.sv new file mode 100644 index 00000000..ab5a52ca --- /dev/null +++ b/HW/hm2/config/DE0_Nano_SoC_Cramps/atlas_3x24_cap_enc.sv @@ -0,0 +1,34 @@ +package boardtype; +// DE0-Nano Dev kit and I/O adaptors specific info +// {STRAIGHT=0,DB25=1} BoardAdaptor; + +parameter BoardAdaptor = 0; + parameter ClockHigh = 200000000; // 200 MHz + parameter ClockMed = 100000000; // 100 MHz + parameter ClockLow = 50000000; // 50 MHz +// parameter BoardNameLow = 32'h41524554; // "TERA" +// parameter BoardNameHigh = 32'h4E304544; // "DE0N" + parameter BoardNameLow = 32'h4153454D; // "MESA" + parameter BoardNameHigh = 32'h35324935; // "5I25" + parameter FPGASize = 9; // Reported as 32-bit value in IDROM.vhd (9 matches Mesanet value for 5i25) + // FIXME: Figure out Mesanet encoding and put something sensible here + parameter FPGAPins = 144; // Total Number of available I/O pins for Hostmot2 use Reported as 32-bit value in IDROM.vhd + // Proposal: On DE0 NANO board Limit to total count of gpios + arduinoconnectors + ltc + adc I/Os + // Maximum of 144 pindesc entries currently hard-coded in IDROM.vhd + parameter IOPorts = 3; // Number of external ports (DE0-Nano_DB25 can have 2 on each 40-pin expansion header) + parameter IOWidth = 72; // Number of total I/O pins = IOPorts * PortWidth + parameter PortWidth = 24; // Number of I/O pins per port: 17 per DB25 + parameter LIOWidth = 0; // Number of local I/Os (used for on-board serial-port on Mesanet cards) + parameter LEDCount = 0; // Number of LEDs + parameter SepClocks = "true"; // Deprecated + parameter OneWS = "true"; // Deprecated + parameter BusWidth = 32; + parameter AddrWidth = 16; + + parameter GPIOWidth = 36; + parameter NumGPIO = 2; + parameter MuxGPIOIOWidth = IOWidth/NumGPIO; + parameter MuxLedWidth = LEDCount/NumGPIO; + parameter ADC = "DE0-Nano-SoC"; + parameter Capsense = 1; +endpackage //_HeaderIncluded diff --git a/HW/hm2/config/DE10_Nano_FB_Cramps/PIN_3x24_cap_enc.vhd b/HW/hm2/config/DE10_Nano_FB_Cramps/PIN_3x24_cap_enc.vhd new file mode 100644 index 00000000..90c96022 --- /dev/null +++ b/HW/hm2/config/DE10_Nano_FB_Cramps/PIN_3x24_cap_enc.vhd @@ -0,0 +1,200 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics +-- http://www.mesanet.com +-- +-- This program is is licensed under a disjunctive dual license giving you +-- the choice of one of the two following sets of free software/open source +-- licensing terms: +-- +-- * GNU General Public License (GPL), version 2.0 or later +-- * 3-clause BSD License +-- +-- +-- The GNU GPL License: +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- +-- +-- The 3-clause BSD License: +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- * Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- * Neither the name of Mesa Electronics nor the names of its +-- contributors may be used to endorse or promote products +-- derived from this software without specific prior written +-- permission. +-- +-- +-- Disclaimer: +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- + +use work.IDROMConst.all; + +package Pintypes is + constant ModuleID : ModuleIDType :=( + -- GTag Version Clock NumInst BaseAddr NumRegisters Strides MultiRegs + (HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask), + (WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask), + (IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask), + (QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask), + (StepGenTag, x"02", ClockLowTag, x"0A", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask), + (PWMTag, x"00", ClockHighTag, x"06", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask), + (LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask), + (NANOADCTag, x"00", ClockLowTag, x"08", NANOADCAddr&PadT, NANOADCNumRegs, x"00", NANOADCBitMask), + (CAPSENSETag, x"00", ClockLowTag, x"04", CAPSENSEAddr&PadT, CAPSENSENumRegs, x"00", CAPSENSEBitMask), + (FWIDTag, x"00", ClockLowTag, x"01", FWIDAddr&PadT, FWIDNumRegs, x"00", FWIDMPBitMask), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000") + ); + + + constant PinDesc : PinDescType :=( +-- Base Sec Sec Sec +-- func unit func pin -- hostmot2 DE0-Nano pin Function + IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 00 GPIO_0 01 01 X Step + IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 01 GPIO_0 02 02 X Dir + IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 02 GPIO_0 03 03 Y Step + IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 03 GPIO_0 04 04 Y Dir + IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 04 GPIO_0 05 05 Z Step + IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 05 GPIO_0 06 06 Z Dir + IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 06 GPIO_0 07 07 E0 Step + IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 07 GPIO_0 08 08 E0 Dir + IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 08 GPIO_0 09 09 E1 Step + IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 09 GPIO_0 10 10 E1 Dir + IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 10 GPIO_0 11 13 E2 Step + IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 11 GPIO_0 12 14 E2 Dir + IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 12 GPIO_0 13 15 U Step + IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 13 GPIO_0 14 16 U Dir + IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 14 GPIO_0 15 17 V Step + IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 15 GPIO_0 16 18 V Dir + IOPortTag & x"08" & StepGenTag & StepGenStepPin, -- I/O 16 GPIO_0 17 19 W Step + IOPortTag & x"08" & StepGenTag & StepGenDirPin, -- I/O 17 GPIO_0 18 20 W Dir + IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 18 GPIO_0 19 21 Spindle DAC PWM + IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 19 GPIO_0 20 22 Spindle DAC PWM + IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 20 GPIO_0 21 23 Spindle DAC PWM + IOPortTag & x"03" & PWMTag & PWMAOutPin, -- I/O 21 GPIO_0 22 24 Spindle DAC PWM + IOPortTag & x"04" & PWMTag & PWMAOutPin, -- I/O 22 GPIO_0 23 25 Spindle DAC PWM + IOPortTag & x"05" & PWMTag & PWMAOutPin, -- I/O 23 GPIO_0 24 26 Spindle DAC PWM + IOPortTag & x"00" & NullTag & NullPin, -- I/O 24 GPIO_0 25 27 Limit X-Min + IOPortTag & x"00" & NullTag & NullPin, -- I/O 25 GPIO_0 26 28 Limit X-Max + IOPortTag & x"00" & NullTag & NullPin, -- I/O 26 GPIO_0 27 31 Limit Y-Min + IOPortTag & x"00" & NullTag & NullPin, -- I/O 27 GPIO_0 27 32 Limit Y-Max + IOPortTag & x"00" & NullTag & NullPin, -- I/O 28 GPIO_0 29 33 Limit Z-Min + IOPortTag & x"00" & NullTag & NullPin, -- I/O 29 GPIO_0 30 34 Limit Z-Max + IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 GPIO_0 31 35 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 31 GPIO_0 32 36 Led + IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 GPIO_0 33 37 Axis_ENA_n + IOPortTag & x"00" & NullTag & NullPin, -- I/O 33 GPIO_0 34 38 Machine_Pwr + IOPortTag & x"00" & NullTag & NullPin, -- I/O 34 GPIO_0 35 39 Estop (In) + IOPortTag & x"00" & NullTag & NullPin, -- I/O 35 GPIO_0 36 40 Estop_Sw + +-- Base Sec Sec Sec +-- func unit func pin -- hostmot2 DE0-Nano pin Function + IOPortTag & x"00" & CAPSENSETag & CapChargePin, -- I/O 36 GPIO_1 01 01 CapSense charge + IOPortTag & x"00" & CAPSENSETag & CapSensePin0, -- I/O 37 GPIO_1 02 02 CapSense sense 0 + IOPortTag & x"00" & CAPSENSETag & CapSensePin1, -- I/O 38 GPIO_1 03 03 CapSense sense 1 + IOPortTag & x"00" & CAPSENSETag & CapSensePin2, -- I/O 39 GPIO_1 04 04 CapSense sense 2 + IOPortTag & x"00" & CAPSENSETag & CapSensePin3, -- I/O 40 GPIO_1 05 05 CapSense sense 3 + IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 41 GPIO_1 06 06 Encoder Z + IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 42 GPIO_1 07 07 Encoder B + IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 43 GPIO_1 08 08 Encoder A + IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 44 GPIO_1 09 09 Encoder Z + IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 45 GPIO_1 10 10 Encoder B + IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 46 GPIO_1 11 13 Encoder A + IOPortTag & x"00" & NullTag & NullPin, -- I/O 47 GPIO_1 12 14 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 48 GPIO_1 13 15 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 49 GPIO_1 14 16 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 50 GPIO_1 15 17 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 51 GPIO_1 16 18 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 52 GPIO_1 17 19 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 53 GPIO_1 18 20 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 54 GPIO_1 19 21 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 55 GPIO_1 20 22 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 56 GPIO_1 21 23 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 57 GPIO_1 22 24 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 58 GPIO_1 23 25 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 59 GPIO_1 24 26 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 60 GPIO_1 25 27 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 61 GPIO_1 26 28 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 62 GPIO_1 27 31 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 63 GPIO_1 28 32 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 64 GPIO_1 29 33 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 65 GPIO_1 30 34 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 66 GPIO_1 31 35 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 67 GPIO_1 32 36 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 68 GPIO_1 33 37 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 69 GPIO_1 34 38 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 70 GPIO_1 35 39 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 71 GPIO_1 36 40 just GPIO + + -- Remainder of 144 pin descriptors are unused + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin); + +end package Pintypes; --PIN_Cramps_3x24_dpll_irq diff --git a/HW/hm2/config/DE10_Nano_FB_Cramps/atlas_3x24_cap_enc.sv b/HW/hm2/config/DE10_Nano_FB_Cramps/atlas_3x24_cap_enc.sv new file mode 100644 index 00000000..ab5a52ca --- /dev/null +++ b/HW/hm2/config/DE10_Nano_FB_Cramps/atlas_3x24_cap_enc.sv @@ -0,0 +1,34 @@ +package boardtype; +// DE0-Nano Dev kit and I/O adaptors specific info +// {STRAIGHT=0,DB25=1} BoardAdaptor; + +parameter BoardAdaptor = 0; + parameter ClockHigh = 200000000; // 200 MHz + parameter ClockMed = 100000000; // 100 MHz + parameter ClockLow = 50000000; // 50 MHz +// parameter BoardNameLow = 32'h41524554; // "TERA" +// parameter BoardNameHigh = 32'h4E304544; // "DE0N" + parameter BoardNameLow = 32'h4153454D; // "MESA" + parameter BoardNameHigh = 32'h35324935; // "5I25" + parameter FPGASize = 9; // Reported as 32-bit value in IDROM.vhd (9 matches Mesanet value for 5i25) + // FIXME: Figure out Mesanet encoding and put something sensible here + parameter FPGAPins = 144; // Total Number of available I/O pins for Hostmot2 use Reported as 32-bit value in IDROM.vhd + // Proposal: On DE0 NANO board Limit to total count of gpios + arduinoconnectors + ltc + adc I/Os + // Maximum of 144 pindesc entries currently hard-coded in IDROM.vhd + parameter IOPorts = 3; // Number of external ports (DE0-Nano_DB25 can have 2 on each 40-pin expansion header) + parameter IOWidth = 72; // Number of total I/O pins = IOPorts * PortWidth + parameter PortWidth = 24; // Number of I/O pins per port: 17 per DB25 + parameter LIOWidth = 0; // Number of local I/Os (used for on-board serial-port on Mesanet cards) + parameter LEDCount = 0; // Number of LEDs + parameter SepClocks = "true"; // Deprecated + parameter OneWS = "true"; // Deprecated + parameter BusWidth = 32; + parameter AddrWidth = 16; + + parameter GPIOWidth = 36; + parameter NumGPIO = 2; + parameter MuxGPIOIOWidth = IOWidth/NumGPIO; + parameter MuxLedWidth = LEDCount/NumGPIO; + parameter ADC = "DE0-Nano-SoC"; + parameter Capsense = 1; +endpackage //_HeaderIncluded