diff --git a/HW/QuartusProjects/Common/adc_fifo.sv b/HW/QuartusProjects/Common/adc_fifo.sv
deleted file mode 100644
index 55066af3..00000000
--- a/HW/QuartusProjects/Common/adc_fifo.sv
+++ /dev/null
@@ -1,252 +0,0 @@
-/* note for avalon interface
-	bus type: nagtive
-	read legacy = 0 (to consistent to FIFO)
-
-*/
-
-module adc_fifo(
-	// avalon slave port
-    input   clock,
-    input   reset_n,
-    input   addr,
-    input   read,
-    input   reg_outdata,
-    input   write,
-    output  reg [31:0]  readdataout,
-    input   [31:0]      writedatain,
-
-    input   adc_clk, // max 40mhz
-	// adc interface
-    output  ADC_CONVST_o,
-    output  ADC_SCK_o,
-    output  ADC_SDI_o,
-    input   ADC_SDO_i
-);
-
-parameter ADC = "";
-
-////////////////////////////////////
-// avalon slave port
-`define WRITE_REG_START_CH				0
-`define WRITE_REG_MEASURE_NUM			1
-
-// write for control
-reg 				measure_fifo_start;
-reg  [11:0] 	measure_fifo_num;
-reg	[2:0]		measure_fifo_ch;
-reg				auto_ch_select;
-
-always @ ( negedge reset_n or posedge write)
-begin
-	if (!reset_n)
-		measure_fifo_start <= 1'b0;
-	else if (write) begin
-		if (addr == `WRITE_REG_START_CH) begin
-			measure_fifo_start	<= writedatain[0];
-			measure_fifo_ch		<= writedatain[6:4];
-			auto_ch_select			<= writedatain[8];
-		end
-		else if (write  && addr == `WRITE_REG_MEASURE_NUM) begin
-			{measure_fifo_num} <= writedatain[11:0];
-		end
-	end
-end
-
-///////////////////////
-// read
-`define READ_REG_MEASURE_DONE	0
-`define READ_REG_ADC_VALUE		1
-wire slave_read_status;
-wire slave_read_data;
-
-reg post_read;
-//reg reg_outdata;//
-
-always @(posedge clock) begin
-	post_read <= read;
-end
-//
-//always @(negedge clock) begin
-//	reg_outdata <= (read && post_read) ? 1'b1 : 1'b0;
-//end
-//
-assign slave_read_status = (addr == `READ_REG_MEASURE_DONE) ?1'b1:1'b0;
-assign slave_read_data = (addr == `READ_REG_ADC_VALUE) ?1'b1:1'b0;
-
-reg measure_fifo_done;
-always @ (posedge reg_outdata)
-begin
-	if (slave_read_status)
-		readdataout <= {4'b0, measure_fifo_num, 9'b0, measure_fifo_ch, 3'b0, measure_fifo_done};
-	else if (slave_read_data)
-//		readdataout <= {13'b0, fifo_ch_q, 4'b0, fifo_q};
-		readdataout <= {20'b0, fifo_q};
-end
-
-reg pre_slave_read_data;
-always @ (posedge clock or negedge reset_n)
-begin
-	if (!reset_n)
-		pre_slave_read_data <= 1'b0;
-	else
-		pre_slave_read_data <= slave_read_data;
-end
-
-// read ack for adc data. (note. Slave_read_data is read lency=2, so slave_read_data is assert two clock)
-assign fifo_rdreq = (pre_slave_read_data & slave_read_data)?1'b1:1'b0;
-
-////////////////////////////////////
-// create triggle message: adc_reset
-
-reg pre_measure_fifo_start;
-always @ (posedge adc_clk)
-begin
-	pre_measure_fifo_start <= measure_fifo_start;
-//	pre_measure_fifo_start[1] <= pre_measure_fifo_start[0];
-end
-
-wire adc_reset ;
-assign adc_reset  = (!pre_measure_fifo_start & measure_fifo_start)?1'b1:1'b0;
-
-////////////////////////////////////
-// control measure_start
-reg [11:0] measure_count;
-
-reg config_first;
-reg wait_measure_done;
-reg measure_start;
-wire measure_done;
-wire [11:0] measure_dataread;
-wire [11:0] reading[7:0];
-
-// auto channel change
-//wire [2:0] adc_ch_sel = (auto_ch_select) ? 3'h7:measure_fifo_ch;
-reg [2:0] adc_ch;
-reg [2:0] adc_ch_dly;
-
-always @ (posedge adc_clk or posedge adc_reset )
-begin
-	if (adc_reset)
-	begin
-		measure_start <= 1'b0;
-		config_first <= 1'b1;
-		measure_count <= 0;
-		measure_fifo_done <= 1'b0;
-		wait_measure_done <= 1'b0;
-		adc_ch <= 0;
-	end
-	else if (!measure_fifo_done & !measure_start & !wait_measure_done)
-	begin
-		measure_start <= 1'b1;
-		wait_measure_done <= 1'b1;
-	end
-	else if (wait_measure_done) // && measure_start)
-	begin
-		measure_start <= 1'b0;
-		if (measure_done)
-		begin
-			if (config_first)
-				config_first <= 1'b0;
-			else
-			begin	// read data and save into fifo
-				if (measure_count < measure_fifo_num) // && !fifo_wrfull)
-				begin
-					measure_count <= measure_count + 1;
-					wait_measure_done <= 1'b0;
-      			if (pre_measure_fifo_start)
-					if (auto_ch_select)
-					begin
-						adc_ch <= ((adc_ch + 1) & 3'h7);
-						adc_ch_dly <= adc_ch;
-               end
-					else
-					begin
-						adc_ch <= measure_fifo_ch;
-						adc_ch_dly <= adc_ch;
-               end
-				end
-				else
-					measure_fifo_done <= 1'b1;
-			end
-		end
-	end
-end
-
-// write data into fifo
-
-reg pre_measure_done;
-
-always @ (posedge adc_clk or posedge adc_reset )
-begin
-	if (adc_reset)
-		pre_measure_done <= 1'b0;
-	else
-		pre_measure_done <= measure_done;
-end
-
-assign fifo_wrreq = (!pre_measure_done & measure_done & !config_first)?1'b1:1'b0;
-
-///////////////////////////////////////
-// SPI
-/*
-assign measure_dataread = reading[adc_ch];
-
-altera_up_adv_adc altera_up_adv_adc_inst
-(
-	.clock(adc_clk) ,	// input  clock_sig
-	.reset(reset_n) ,	// input  reset_sig
-	.go(measure_start) ,	// input  go_sig
-	.sclk(ADC_SCK_o) ,	// output  sclk_sig
-	.cs_n(ADC_CONVST_o) ,	// output  cs_n_sig
-	.din(ADC_SDI_o) ,	// output  din_sig
-	.dout(ADC_SDO_i) ,	// input  dout_sig
-	.done(measure_done) ,	// output  done_sig
-	.reading(reading) 	// output [11:0] reading_sig
-);
-
-defparam altera_up_adv_adc_inst.T_SCLK = 'b00000100;
-defparam altera_up_adv_adc_inst.NUM_CH = 'b0111;
-defparam altera_up_adv_adc_inst.BOARD = ADC;
-defparam altera_up_adv_adc_inst.BOARD_REV = "Autodetect";
-*/
-adc_ltc2308 adc_ltc2308_inst(
-	.clk(adc_clk), // max 40mhz
-
-	// start measure
-	.measure_start(measure_start), // posedge triggle
-	.measure_done(measure_done),
-	.measure_ch(adc_ch),
-	.measure_dataread(measure_dataread),
-
-
-	// adc interface
-	.ADC_CONVST(ADC_CONVST_o),
-	.ADC_SCK(ADC_SCK_o),
-	.ADC_SDI(ADC_SDI_o),
-	.ADC_SDO(ADC_SDO_i)
-);
-
-
-///////////////////////////////////////
-// FIFO
-wire fifo_wrfull;
-wire fifo_rdempty;
-wire  fifo_wrreq;
-wire [11:0]	 fifo_q;
-wire fifo_rdreq;
-wire [2:0] fifo_ch_q;
-
-adc_data_fifo adc_data_fifo_inst(
-	.aclr(adc_reset),
-	.data({adc_ch_dly, measure_dataread}),
-	.rdclk(read),
-	.rdreq(fifo_rdreq),
-	.wrclk(adc_clk),
-	.wrreq(fifo_wrreq),
-	.q({fifo_ch_q, fifo_q}),
-	.rdempty(fifo_rdempty),
-	.wrfull(fifo_wrfull)
-);
-
-
-endmodule
diff --git a/HW/QuartusProjects/Common/altera_up_adv_adc.v b/HW/QuartusProjects/Common/altera_up_adv_adc.v
deleted file mode 100644
index 491a7f30..00000000
--- a/HW/QuartusProjects/Common/altera_up_adv_adc.v
+++ /dev/null
@@ -1,424 +0,0 @@
-// (C) 2001-2016 Intel Corporation. All rights reserved.
-// Your use of Intel Corporation's design tools, logic functions and other 
-// software and tools, and its AMPP partner logic functions, and any output 
-// files any of the foregoing (including device programming or simulation 
-// files), and any associated documentation or information are expressly subject 
-// to the terms and conditions of the Intel Program License Subscription 
-// Agreement, Intel MegaCore Function License Agreement, or other applicable 
-// license agreement, including, without limitation, that your use is for the 
-// sole purpose of programming logic devices manufactured by Intel and sold by 
-// Intel or its authorized distributors.  Please refer to the applicable 
-// agreement for further details.
-
-
-// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
-// IN THIS FILE.
-
-//  - - - - - - - - - -ADC- - - - - - - - - - - - - - -
-module altera_up_adv_adc (
-	input clock,
-	input reset,
-	input go,
-	output reg sclk,
-	output reg cs_n,
-	output reg din,
-	input dout,
-	output reg done,
-	output reg [11:0] reading[7:0]
-);
-//input go, dout, clock, reset;
-
-//output reg done;
-//output reg sclk, din, cs_n;
-//output reg [11:0] reading[0], reading[1], reading[2], reading[3], reading[4], reading[5], reading[6], reading[7];
-
-parameter T_SCLK = 8'd4;
-parameter NUM_CH = 4'd7;
-parameter BOARD = "DE1-SoC";
-parameter BOARD_REV = "Autodetect";
-
-generate
-
-    if (BOARD == "DE1-SoC" || BOARD == "DE0-Nano-SoC")
-    begin
-    
-        //FSM state values
-        parameter resetState = 3'd0, waitState=3'd1, transState=3'd2, doneState=3'd3, pauseState=3'd4, initCtrlRegState=3'd5, pauseStateNoAddrIncr=3'd6;
-
-        reg [2:0] currState, nextState;
-        reg [14:0] dout_shift_reg;
-        reg [11:0] din_shift_reg;
-        reg [7:0] counter;
-        reg [12:0] pause_counter;
-        reg [3:0] sclk_counter;
-        reg [2:0] address, next_addr;
-        reg [3:0] ad_or_ltc_error_count = 4'd0;
-        wire isLTC;
-        
-        // if AD7928 chip, isLTC == 0. if LTC 2308 chip, isLTC == 1.
-        if (BOARD == "DE1-SoC" && BOARD_REV == "Autodetect")
-            assign isLTC = ad_or_ltc_error_count[3];
-        else if (BOARD == "DE1-SoC" && BOARD_REV == "A - E")
-            assign isLTC = 1'b0;
-        else // DE0-Nano-SoC and DE1-SoC rev F+ have the LTC chip
-            assign isLTC = 1'b1;
-
-        wire transStateComplete = ((isLTC && sclk_counter==4'd11) || sclk_counter==4'd15) && counter==0;
-
-        always @(posedge clock)
-            currState <=nextState;
-            
-        // - - - - -NextState Selection Logic - - - - - - - -
-            always @(*)
-            begin
-                din = din_shift_reg[11];
-                if (reset)
-                    nextState=resetState;
-                case (currState)
-                    resetState:begin
-                        cs_n=1;
-                        done=0;
-                        /*if (isLTC)
-                            nextState=waitState;
-                        else*/
-                            nextState=initCtrlRegState;
-                    end
-                    initCtrlRegState:begin
-                        cs_n=0;
-                        done=0;
-                        if (transStateComplete && !sclk)
-                            if (isLTC)
-                                nextState = pauseStateNoAddrIncr;
-                            else
-                                nextState = waitState;
-                        else
-                            nextState=initCtrlRegState;
-                    end
-                    pauseStateNoAddrIncr:begin
-                        cs_n=1;
-                        done=0;
-                        if (pause_counter > 13'd0)
-                            nextState=pauseStateNoAddrIncr;
-                        else
-                            nextState=transState;
-                    end
-                    waitState:begin
-                        cs_n=1;
-                        done=0;
-                        if (go)
-                            nextState=transState;
-                        else
-                            nextState=waitState;
-                    end
-                    transState:begin
-                        cs_n=0;
-                        done=0;
-                        if (transStateComplete && !sclk)
-                            nextState=pauseState;
-                        else
-                            nextState=transState;
-                    end
-                    // pause state must be >= 50ns! This is the "tquiet" required between conversions (or tCONV = 1.6us for LTC)
-                    pauseState:begin
-                        cs_n=1;
-                        done=0;
-                        if (pause_counter > 13'd0)
-                            nextState=pauseState;
-                        else if(address==NUM_CH[2:0])
-                            nextState=doneState;
-                        else
-                            nextState=transState;
-                    end
-                    doneState:begin
-                        cs_n=1;
-                        done=1;
-                        if (go)
-                            nextState=doneState;
-                        else
-                            nextState=resetState;
-                    end
-                    default:begin
-                        cs_n=1;
-                        done=0;
-                        nextState = resetState;
-                    end
-                endcase
-            end
-        // - - - - - - - - - pause counter logic - - - - - - - - - - 
-            always @(posedge clock)
-            if (currState == pauseState || currState == pauseStateNoAddrIncr)
-                pause_counter <= pause_counter - 13'd1;
-            else 
-                // T_SCLK is such that T_SCLK cycles of clock -> 20MHz or less SCLK.
-                if (isLTC)
-                    pause_counter <= {T_SCLK[7:0],5'd0};
-                else
-                    pause_counter <= {5'd0,T_SCLK[7:1],(T_SCLK[0]&&sclk)}-8'd1;
-        // - - - - - - - - - counter logic - - - - - - - - - - 
-            always @(posedge clock or posedge reset)
-            if (reset)
-                counter <= T_SCLK[7:1]+(T_SCLK[0]&&sclk)-8'd1;
-            else if (cs_n)
-                counter <= T_SCLK[7:1]+(T_SCLK[0]&&sclk)-8'd1;
-            else if (counter == 0)
-                counter <= T_SCLK[7:1]+(T_SCLK[0]&&sclk)-8'd1;
-            else
-                counter <= counter - 8'b1;
-        // - - - - - - - - ADC_SCLK generation - - - - - - - - - 
-            always @(posedge clock or posedge reset)
-            if (reset)
-                sclk <= ~isLTC;
-            else if (cs_n)
-                sclk <= ~isLTC;
-            else if (counter == 0)
-                sclk <= ~sclk;
-        // - - - - - - - - - - - sclk_counter logic - - - - - - - -
-            always @ (posedge clock)
-                if (reset || currState == doneState || currState == pauseState || currState == pauseStateNoAddrIncr || currState == waitState || currState == resetState)
-                    sclk_counter <=4'b0;
-                else if (counter == 0 && !sclk)
-                    sclk_counter <= sclk_counter + 4'b1;
-        // - - - - - - - - - - readings logic - - - - - - - - - -
-            always @(posedge clock)
-                if (reset)
-                begin
-                    reading[0] <= 12'd0;
-                    //ad_or_ltc <= 1'b0;
-                    ad_or_ltc_error_count <= 4'd0;
-                end
-                else if (transStateComplete && sclk)
-                begin
-                    if (!isLTC && dout_shift_reg[13:11] == address)
-                        case (dout_shift_reg[13:11])
-                            3'd0: reading[0] <= {dout_shift_reg[10:0],dout}; // should be {dout_shift_reg[10:0],dout}
-                            3'd1: reading[1] <= {dout_shift_reg[10:0],dout};
-                            3'd2: reading[2] <= {dout_shift_reg[10:0],dout};
-                            3'd3: reading[3] <= {dout_shift_reg[10:0],dout};
-                            3'd4: reading[4] <= {dout_shift_reg[10:0],dout};
-                            3'd5: reading[5] <= {dout_shift_reg[10:0],dout};
-                            3'd6: reading[6] <= {dout_shift_reg[10:0],dout};
-                            3'd7: reading[7] <= {dout_shift_reg[10:0],dout};
-                        endcase
-                    else if (isLTC)
-                        case (address)
-                            3'd0: begin
-                                if (NUM_CH[2:0] == 3'd0)
-                                    reading[0] <= {dout_shift_reg[10:0],dout};
-                                else if (NUM_CH[2:0] == 3'd1)
-                                    reading[1] <= {dout_shift_reg[10:0],dout};
-                                else if (NUM_CH[2:0] == 3'd2)
-                                    reading[2] <= {dout_shift_reg[10:0],dout};
-                                else if (NUM_CH[2:0] == 3'd3)
-                                    reading[3] <= {dout_shift_reg[10:0],dout};
-                                else if (NUM_CH[2:0] == 3'd4)
-                                    reading[4] <= {dout_shift_reg[10:0],dout};
-                                else if (NUM_CH[2:0] == 3'd5)
-                                    reading[5] <= {dout_shift_reg[10:0],dout};
-                                else if (NUM_CH[2:0] == 3'd6)
-                                    reading[6] <= {dout_shift_reg[10:0],dout};
-                                else if (NUM_CH[2:0] == 3'd7)
-                                    reading[7] <= {dout_shift_reg[10:0],dout};
-                            end
-                            3'd1: reading[0] <= {dout_shift_reg[10:0],dout};
-                            3'd2: reading[1] <= {dout_shift_reg[10:0],dout};
-                            3'd3: reading[2] <= {dout_shift_reg[10:0],dout};
-                            3'd4: reading[3] <= {dout_shift_reg[10:0],dout};
-                            3'd5: reading[4] <= {dout_shift_reg[10:0],dout};
-                            3'd6: reading[5] <= {dout_shift_reg[10:0],dout};
-                            3'd7: reading[6] <= {dout_shift_reg[10:0],dout};
-                        endcase
-
-                    else if (ad_or_ltc_error_count < 4'd15 && currState == transState)
-                        ad_or_ltc_error_count <= ad_or_ltc_error_count + 4'd1;
-                        //ad_or_ltc <= 1'b1;
-                end
-        // - - - - - - - - - address logic - - - - - - - - -
-            always @(posedge clock)
-                if (reset || currState == waitState || (currState == resetState && isLTC))
-                    address <= 3'd0;
-                else if (currState == pauseState && pause_counter == 13'd0)
-                    if (address < NUM_CH[2:0])
-                        address <= next_addr;
-                    /*if (address >= NUM_CH[2:0])
-                        address <= 3'd0;
-                    else
-                        address <= next_addr;*/
-        // - - - - - - - - - - dout_shift_reg logic - - - - - - - - - - - - 
-            always @(posedge clock)
-                if (reset)
-                    dout_shift_reg <= 15'd0;
-                else if (counter==0 && ~isLTC == sclk && (!isLTC || sclk_counter != 4'd11) && sclk_counter != 4'd15)
-                    dout_shift_reg [14:0] <= {dout_shift_reg [13:0], dout};
-        // - - - - - - - - - - din_shift_reg logic - - - - - - - - -
-            always @(posedge clock)
-                if (currState == resetState)
-                    if (isLTC)
-                        din_shift_reg <= {1'b1,NUM_CH[0],NUM_CH[2],NUM_CH[1],2'b10,6'd0};// S/D, O/S, S1, S0, UNI, SLP
-                    else
-                        din_shift_reg <= {3'b110,NUM_CH[2:0],6'b111001};     //13'hDF9; // Ctrl reg initialize to 0xdf90. MSB is a dummy value that doesnt actually get used
-                else if ((currState == waitState && go) || currState == pauseStateNoAddrIncr ||
-                            (currState == pauseState && address != NUM_CH[2:0]) ||
-                            (isLTC && currState == transState && counter != 0 &&  sclk_counter == 4'd0)) // For LTC, grab immediately after transition to transState
-                    if (isLTC)
-                        din_shift_reg <= {1'b1,address[0],address[2],address[1],2'b10,6'd0};// S/D, O/S, S1, S0, UNI, SLP
-                    else
-                        din_shift_reg <= {3'b010,NUM_CH[2:0],6'b111001};     //13'h5DF9  WRITE=0,SEQ=1,DONTCARE,ADDR2,ADDR1,ADDR0,DONTCARE*6
-                else if (counter == 8'd0 && isLTC == sclk)
-                    din_shift_reg <={din_shift_reg[10:0],1'b0};
-        // - - - - - - - - - - next_addr logic - - - - - - - - - - - -
-            always @(posedge clock)
-                if (reset)
-                    next_addr <= 3'd0;
-                else
-                    next_addr <= address + 3'b1;
-	end
-    else if (BOARD == "DE0-Nano")
-    begin
-        //FSM state values
-        parameter resetState = 3'd0, waitState=3'd1, transState=3'd2, doneState=3'd3, pauseState=3'd4;
-
-        reg [2:0] currState, nextState;
-        reg [10:0] shift_reg;
-        reg [5:0] addr_shift_reg;
-        reg [7:0] counter;
-        reg [3:0] sclk_counter;
-        reg [2:0] address, next_addr;
-
-        always @(posedge clock)
-            currState <=nextState;
-            
-        // - - - - -NextState Selection Logic - - - - - - - -
-            always @(*)
-            begin
-                din = addr_shift_reg[5];
-                if (reset)
-                    nextState=resetState;
-                case (currState)
-                    resetState:begin
-                        cs_n=1;
-                        done=0;
-                        nextState=waitState;
-                    end
-                    waitState:begin
-                        cs_n=1;
-                        done=0;
-                        if (go)
-                            nextState=transState;
-                        else
-                            nextState=waitState;
-                    end
-                    transState:begin
-                        cs_n=0;
-                        done=0;
-                        if (sclk_counter==4'd15&& counter==0 && !sclk)
-                            nextState=pauseState;
-                        else
-                            nextState=transState;
-                    end
-                    pauseState:begin
-                        cs_n=0;
-                        done=0;
-                        if(address==3'd0)
-                            nextState=doneState;
-                        else
-                            nextState=transState;
-                    end
-                    doneState:begin
-                        cs_n=1;
-                        done=1;
-                        if (go)
-                            nextState=doneState;
-                        else
-                            nextState=waitState;
-                    end
-                    default:begin
-                        cs_n=1;
-                        done=0;
-                        nextState = resetState;
-                    end
-                endcase
-            end
-        // - - - - - - - - - counter logic - - - - - - - - - - 
-            always @(posedge clock or posedge reset)
-            if (reset)
-                counter <= T_SCLK[7:1]+(T_SCLK[0]&&sclk)-8'd1;
-            else if (cs_n)
-                counter <= T_SCLK[7:1]+(T_SCLK[0]&&sclk)-8'd1;
-            else if (counter == 0)
-                counter <= T_SCLK[7:1]+(T_SCLK[0]&&sclk)-8'd1;
-            else
-                counter <= counter - 8'b1;
-        // - - - - - - - - ADC_SCLK generation - - - - - - - - - 
-            always @(posedge clock or posedge reset)
-            if (reset)
-                sclk <= 1;
-            else if (cs_n)
-                sclk <= 1;
-            else if (counter == 0)
-                sclk <= ~sclk;
-        // - - - - - - - - - - - sclk_counter logic - - - - - - - -
-            always @ (posedge clock)
-                if (currState == doneState || currState == waitState)
-                    sclk_counter <=4'b0;
-                else if (counter == 0 && !sclk)
-                    sclk_counter <= sclk_counter + 4'b1;
-        // - - - - - - - - - - readings logic - - - - - - - - - -
-            always @(posedge clock)
-                if (sclk_counter == 4'd15 && counter == 0 && !sclk)
-                    if (address == 0)
-                        case (NUM_CH)
-                            4'd2: reading[1] <= {shift_reg[10:0],dout};
-                            4'd3: reading[2] <= {shift_reg[10:0],dout};
-                            4'd4: reading[3] <= {shift_reg[10:0],dout};
-                            4'd5: reading[4] <= {shift_reg[10:0],dout};
-                            4'd6: reading[5] <= {shift_reg[10:0],dout};
-                            4'd7: reading[6] <= {shift_reg[10:0],dout};
-                            4'd8: reading[7] <= {shift_reg[10:0],dout};
-                        endcase
-                    else 
-                        case (address)
-                            3'd1: reading[0] <= {shift_reg[10:0],dout};
-                            3'd2: reading[1] <= {shift_reg[10:0],dout};
-                            3'd3: reading[2] <= {shift_reg[10:0],dout};
-                            3'd4: reading[3] <= {shift_reg[10:0],dout};
-                            3'd5: reading[4] <= {shift_reg[10:0],dout};
-                            3'd6: reading[5] <= {shift_reg[10:0],dout};
-                            3'd7: reading[6] <= {shift_reg[10:0],dout};
-                        endcase
-        // - - - - - - - - - address logic - - - - - - - - -
-            always @(posedge clock)
-                if (currState == resetState)
-                    address <= 3'd1;
-                else if (currState == pauseState)
-                    if (address >= (NUM_CH-1))
-                        address <= 3'd0;
-                    else
-                        address <= next_addr;
-        // - - - - - - - - - - shift_reg logic - - - - - - - - - - - - 
-            always @(posedge clock)
-                if (counter==0 && !sclk && sclk_counter != 4'd15)
-                    shift_reg [10:0] <= {shift_reg [9:0], dout};
-        // - - - - - - - - - - addr_shift_reg logic - - - - - - - - -
-            always @(posedge clock)
-                if (currState == waitState && go)
-                    addr_shift_reg <= 6'b000001;
-                else if (currState == pauseState)
-                    if (address >= (NUM_CH-1))
-                        addr_shift_reg <= 6'b0;
-                    else
-                        addr_shift_reg <= {3'b0, next_addr};
-                else if (counter==0 && sclk)
-                    addr_shift_reg <={addr_shift_reg[4:0],1'b0};
-        // - - - - - - - - - - next_addr logic - - - - - - - - - - - -
-            always @(posedge clock)
-                next_addr <= address + 3'b1;
-    end
-    
-endgenerate
-        
-endmodule 
diff --git a/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/DE10_Nano_SoC_FB_DB25-old.v b/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/DE10_Nano_SoC_FB_DB25-old.v
deleted file mode 100644
index 6ebdb55e..00000000
--- a/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/DE10_Nano_SoC_FB_DB25-old.v
+++ /dev/null
@@ -1,293 +0,0 @@
-`default_nettype none
-//=======================================================
-//  This code is generated by Terasic System Builder
-//=======================================================
-
-module DE10_Nano_SoC_FB_DB25(
-
-	//////////// CLOCK //////////
-	input 		          		FPGA_CLK1_50,
-	input 		          		FPGA_CLK2_50,
-	input 		          		FPGA_CLK3_50,
-
-	//////////// HDMI //////////
-	inout 		          		HDMI_I2C_SCL,
-	inout 		          		HDMI_I2C_SDA,
-	inout 		          		HDMI_I2S,
-	inout 		          		HDMI_LRCLK,
-	inout 		          		HDMI_MCLK,
-	inout 		          		HDMI_SCLK,
-	output		          		HDMI_TX_CLK,
-	output		    [23:0]		HDMI_TX_D,
-	output		          		HDMI_TX_DE,
-	output		          		HDMI_TX_HS,
-	input 		          		HDMI_TX_INT,
-	output		          		HDMI_TX_VS,
-
-	//////////// HPS //////////
-	inout 		          		HPS_CONV_USB_N,
-	output		    [14:0]		HPS_DDR3_ADDR,
-	output		     [2:0]		HPS_DDR3_BA,
-	output		          		HPS_DDR3_CAS_N,
-	output		          		HPS_DDR3_CK_N,
-	output		          		HPS_DDR3_CK_P,
-	output		          		HPS_DDR3_CKE,
-	output		          		HPS_DDR3_CS_N,
-	output		     [3:0]		HPS_DDR3_DM,
-	inout 		    [31:0]		HPS_DDR3_DQ,
-	inout 		     [3:0]		HPS_DDR3_DQS_N,
-	inout 		     [3:0]		HPS_DDR3_DQS_P,
-	output		          		HPS_DDR3_ODT,
-	output		          		HPS_DDR3_RAS_N,
-	output		          		HPS_DDR3_RESET_N,
-	input 		          		HPS_DDR3_RZQ,
-	output		          		HPS_DDR3_WE_N,
-	output		          		HPS_ENET_GTX_CLK,
-	inout 		          		HPS_ENET_INT_N,
-	output		          		HPS_ENET_MDC,
-	inout 		          		HPS_ENET_MDIO,
-	input 		          		HPS_ENET_RX_CLK,
-	input 		     [3:0]		HPS_ENET_RX_DATA,
-	input 		          		HPS_ENET_RX_DV,
-	output		     [3:0]		HPS_ENET_TX_DATA,
-	output		          		HPS_ENET_TX_EN,
-	inout 		          		HPS_GSENSOR_INT,
-	inout 		          		HPS_I2C0_SCLK,
-	inout 		          		HPS_I2C0_SDAT,
-	inout 		          		HPS_I2C1_SCLK,
-	inout 		          		HPS_I2C1_SDAT,
-	inout 		          		HPS_KEY,
-	inout 		          		HPS_LED,
-	inout 		          		HPS_LTC_GPIO,
-	output		          		HPS_SD_CLK,
-	inout 		          		HPS_SD_CMD,
-	inout 		     [3:0]		HPS_SD_DATA,
-	output		          		HPS_SPIM_CLK,
-	input 		          		HPS_SPIM_MISO,
-	output		          		HPS_SPIM_MOSI,
-	inout 		          		HPS_SPIM_SS,
-	input 		          		HPS_UART_RX,
-	output		          		HPS_UART_TX,
-	input 		          		HPS_USB_CLKOUT,
-	inout 		     [7:0]		HPS_USB_DATA,
-	input 		          		HPS_USB_DIR,
-	input 		          		HPS_USB_NXT,
-	output		          		HPS_USB_STP,
-
-	//////////// KEY //////////
-	input 		     [1:0]		KEY,
-
-	//////////// LED //////////
-	output		     [7:0]		LED,
-
-	//////////// SW //////////
-	input 		     [3:0]		SW
-);
-
-
-
-//=======================================================
-//  REG/WIRE declarations
-//=======================================================
- wire  hps_fpga_reset_n;
-  wire [1:0] fpga_debounced_buttons;
-  wire [6:0]  fpga_led_internal;
-  wire [2:0]  hps_reset_req;
-  wire        hps_cold_reset;
-  wire        hps_warm_reset;
-  wire        hps_debug_reset;
-  wire [27:0] stm_hw_events;
-  wire 		  fpga_clk_50;
-  wire               clk_65;
-// connection of internal logics
-  assign LED[7:1] = fpga_led_internal;
-  assign fpga_clk_50=FPGA_CLK1_50;
-  assign stm_hw_events    = {{15{1'b0}}, SW, fpga_led_internal, fpga_debounced_buttons};
-
-
-
-//=======================================================
-//  Structural coding
-//=======================================================
-I2C_HDMI_Config u_I2C_HDMI_Config (
-	.iCLK(FPGA_CLK1_50),
-	.iRST_N( 1'b1),
-	.I2C_SCLK(HDMI_I2C_SCL),
-	.I2C_SDAT(HDMI_I2C_SDA),
-	.HDMI_TX_INT(HDMI_TX_INT)
-	);
-
-assign HDMI_TX_CLK = clk_65;
-
-soc_system u0 (
-		//Clock&Reset
-	  .clk_clk                                  (FPGA_CLK1_50 ),                               //                            clk.clk
-	  .reset_reset_n                            (hps_fpga_reset_n ),                         //                          reset.reset_n
-	  .lcd_clk_clk                               (clk_65 ),                               //                            clk.clk
-	  .alt_vip_itc_0_clocked_video_vid_clk       (HDMI_TX_CLK ),       // alt_vip_itc_0_clocked_video.vid_clk
-	  .alt_vip_itc_0_clocked_video_vid_data      (HDMI_TX_D ),      //                            .vid_data
-	  .alt_vip_itc_0_clocked_video_underflow     ( ),     //                            .underflow
-	  .alt_vip_itc_0_clocked_video_vid_datavalid (HDMI_TX_DE), //                            .vid_datavalid
-	  .alt_vip_itc_0_clocked_video_vid_v_sync    (HDMI_TX_VS ),    //                            .vid_v_sync
-	  .alt_vip_itc_0_clocked_video_vid_h_sync    (HDMI_TX_HS ),    //                            .vid_h_sync
-	  .alt_vip_itc_0_clocked_video_vid_f         ( ),         //                            .vid_f
-	  .alt_vip_itc_0_clocked_video_vid_h         ( ),         //                            .vid_h
-	  .alt_vip_itc_0_clocked_video_vid_v         ( ),          //                            .vid_v
-
-	  //HPS ddr3
-	  .memory_mem_a                          ( HPS_DDR3_ADDR),                       //                memory.mem_a
-	  .memory_mem_ba                         ( HPS_DDR3_BA),                         //                .mem_ba
-	  .memory_mem_ck                         ( HPS_DDR3_CK_P),                       //                .mem_ck
-	  .memory_mem_ck_n                       ( HPS_DDR3_CK_N),                       //                .mem_ck_n
-	  .memory_mem_cke                        ( HPS_DDR3_CKE),                        //                .mem_cke
-	  .memory_mem_cs_n                       ( HPS_DDR3_CS_N),                       //                .mem_cs_n
-	  .memory_mem_ras_n                      ( HPS_DDR3_RAS_N),                      //                .mem_ras_n
-	  .memory_mem_cas_n                      ( HPS_DDR3_CAS_N),                      //                .mem_cas_n
-	  .memory_mem_we_n                       ( HPS_DDR3_WE_N),                       //                .mem_we_n
-	  .memory_mem_reset_n                    ( HPS_DDR3_RESET_N),                    //                .mem_reset_n
-	  .memory_mem_dq                         ( HPS_DDR3_DQ),                         //                .mem_dq
-	  .memory_mem_dqs                        ( HPS_DDR3_DQS_P),                      //                .mem_dqs
-	  .memory_mem_dqs_n                      ( HPS_DDR3_DQS_N),                      //                .mem_dqs_n
-	  .memory_mem_odt                        ( HPS_DDR3_ODT),                        //                .mem_odt
-	  .memory_mem_dm                         ( HPS_DDR3_DM),                         //                .mem_dm
-	  .memory_oct_rzqin                      ( HPS_DDR3_RZQ),                        //                .oct_rzqin
-	  //HPS ethernet
-	  .hps_0_hps_io_hps_io_emac1_inst_TX_CLK ( HPS_ENET_GTX_CLK),       //                             hps_0_hps_io.hps_io_emac1_inst_TX_CLK
-	  .hps_0_hps_io_hps_io_emac1_inst_TXD0   ( HPS_ENET_TX_DATA[0] ),   //                             .hps_io_emac1_inst_TXD0
-	  .hps_0_hps_io_hps_io_emac1_inst_TXD1   ( HPS_ENET_TX_DATA[1] ),   //                             .hps_io_emac1_inst_TXD1
-	  .hps_0_hps_io_hps_io_emac1_inst_TXD2   ( HPS_ENET_TX_DATA[2] ),   //                             .hps_io_emac1_inst_TXD2
-	  .hps_0_hps_io_hps_io_emac1_inst_TXD3   ( HPS_ENET_TX_DATA[3] ),   //                             .hps_io_emac1_inst_TXD3
-	  .hps_0_hps_io_hps_io_emac1_inst_RXD0   ( HPS_ENET_RX_DATA[0] ),   //                             .hps_io_emac1_inst_RXD0
-	  .hps_0_hps_io_hps_io_emac1_inst_MDIO   ( HPS_ENET_MDIO ),         //                             .hps_io_emac1_inst_MDIO
-	  .hps_0_hps_io_hps_io_emac1_inst_MDC    ( HPS_ENET_MDC  ),         //                             .hps_io_emac1_inst_MDC
-	  .hps_0_hps_io_hps_io_emac1_inst_RX_CTL ( HPS_ENET_RX_DV),         //                             .hps_io_emac1_inst_RX_CTL
-	  .hps_0_hps_io_hps_io_emac1_inst_TX_CTL ( HPS_ENET_TX_EN),         //                             .hps_io_emac1_inst_TX_CTL
-	  .hps_0_hps_io_hps_io_emac1_inst_RX_CLK ( HPS_ENET_RX_CLK),        //                             .hps_io_emac1_inst_RX_CLK
-	  .hps_0_hps_io_hps_io_emac1_inst_RXD1   ( HPS_ENET_RX_DATA[1] ),   //                             .hps_io_emac1_inst_RXD1
-	  .hps_0_hps_io_hps_io_emac1_inst_RXD2   ( HPS_ENET_RX_DATA[2] ),   //                             .hps_io_emac1_inst_RXD2
-	  .hps_0_hps_io_hps_io_emac1_inst_RXD3   ( HPS_ENET_RX_DATA[3] ),   //                             .hps_io_emac1_inst_RXD3
-	  //HPS SD card
-	  .hps_0_hps_io_hps_io_sdio_inst_CMD     ( HPS_SD_CMD    ),           //                               .hps_io_sdio_inst_CMD
-	  .hps_0_hps_io_hps_io_sdio_inst_D0      ( HPS_SD_DATA[0]     ),      //                               .hps_io_sdio_inst_D0
-	  .hps_0_hps_io_hps_io_sdio_inst_D1      ( HPS_SD_DATA[1]     ),      //                               .hps_io_sdio_inst_D1
-	  .hps_0_hps_io_hps_io_sdio_inst_CLK     ( HPS_SD_CLK   ),            //                               .hps_io_sdio_inst_CLK
-	  .hps_0_hps_io_hps_io_sdio_inst_D2      ( HPS_SD_DATA[2]     ),      //                               .hps_io_sdio_inst_D2
-	  .hps_0_hps_io_hps_io_sdio_inst_D3      ( HPS_SD_DATA[3]     ),      //                               .hps_io_sdio_inst_D3
-	  //HPS USB
-	  .hps_0_hps_io_hps_io_usb1_inst_D0      ( HPS_USB_DATA[0]    ),      //                               .hps_io_usb1_inst_D0
-	  .hps_0_hps_io_hps_io_usb1_inst_D1      ( HPS_USB_DATA[1]    ),      //                               .hps_io_usb1_inst_D1
-	  .hps_0_hps_io_hps_io_usb1_inst_D2      ( HPS_USB_DATA[2]    ),      //                               .hps_io_usb1_inst_D2
-	  .hps_0_hps_io_hps_io_usb1_inst_D3      ( HPS_USB_DATA[3]    ),      //                               .hps_io_usb1_inst_D3
-	  .hps_0_hps_io_hps_io_usb1_inst_D4      ( HPS_USB_DATA[4]    ),      //                               .hps_io_usb1_inst_D4
-	  .hps_0_hps_io_hps_io_usb1_inst_D5      ( HPS_USB_DATA[5]    ),      //                               .hps_io_usb1_inst_D5
-	  .hps_0_hps_io_hps_io_usb1_inst_D6      ( HPS_USB_DATA[6]    ),      //                               .hps_io_usb1_inst_D6
-	  .hps_0_hps_io_hps_io_usb1_inst_D7      ( HPS_USB_DATA[7]    ),      //                               .hps_io_usb1_inst_D7
-	  .hps_0_hps_io_hps_io_usb1_inst_CLK     ( HPS_USB_CLKOUT    ),       //                               .hps_io_usb1_inst_CLK
-	  .hps_0_hps_io_hps_io_usb1_inst_STP     ( HPS_USB_STP    ),          //                               .hps_io_usb1_inst_STP
-	  .hps_0_hps_io_hps_io_usb1_inst_DIR     ( HPS_USB_DIR    ),          //                               .hps_io_usb1_inst_DIR
-	  .hps_0_hps_io_hps_io_usb1_inst_NXT     ( HPS_USB_NXT    ),          //                               .hps_io_usb1_inst_NXT
-		//HPS SPI
-	  .hps_0_hps_io_hps_io_spim1_inst_CLK    ( HPS_SPIM_CLK  ),           //                               .hps_io_spim1_inst_CLK
-	  .hps_0_hps_io_hps_io_spim1_inst_MOSI   ( HPS_SPIM_MOSI ),           //                               .hps_io_spim1_inst_MOSI
-	  .hps_0_hps_io_hps_io_spim1_inst_MISO   ( HPS_SPIM_MISO ),           //                               .hps_io_spim1_inst_MISO
-	  .hps_0_hps_io_hps_io_spim1_inst_SS0    ( HPS_SPIM_SS   ),             //                               .hps_io_spim1_inst_SS0
-		//HPS UART
-	  .hps_0_hps_io_hps_io_uart0_inst_RX     ( HPS_UART_RX   ),          //                               .hps_io_uart0_inst_RX
-	  .hps_0_hps_io_hps_io_uart0_inst_TX     ( HPS_UART_TX   ),          //                               .hps_io_uart0_inst_TX
-		//HPS I2C1
-	  .hps_0_hps_io_hps_io_i2c0_inst_SDA     ( HPS_I2C0_SDAT  ),        //                               .hps_io_i2c0_inst_SDA
-	  .hps_0_hps_io_hps_io_i2c0_inst_SCL     ( HPS_I2C0_SCLK  ),        //                               .hps_io_i2c0_inst_SCL
-		//HPS I2C2
-	  .hps_0_hps_io_hps_io_i2c1_inst_SDA     ( HPS_I2C1_SDAT  ),        //                               .hps_io_i2c1_inst_SDA
-	  .hps_0_hps_io_hps_io_i2c1_inst_SCL     ( HPS_I2C1_SCLK  ),        //                               .hps_io_i2c1_inst_SCL
-		//GPIO
-	  .hps_0_hps_io_hps_io_gpio_inst_GPIO09  ( HPS_CONV_USB_N ),  //                               .hps_io_gpio_inst_GPIO09
-	  .hps_0_hps_io_hps_io_gpio_inst_GPIO35  ( HPS_ENET_INT_N ),  //                               .hps_io_gpio_inst_GPIO35
-	  .hps_0_hps_io_hps_io_gpio_inst_GPIO40  ( HPS_LTC_GPIO   ),  //                               .hps_io_gpio_inst_GPIO40
-	  .hps_0_hps_io_hps_io_gpio_inst_GPIO53  ( HPS_LED   ),  //                               .hps_io_gpio_inst_GPIO53
-	  .hps_0_hps_io_hps_io_gpio_inst_GPIO54  ( HPS_KEY   ),  //                               .hps_io_gpio_inst_GPIO54
-	  .hps_0_hps_io_hps_io_gpio_inst_GPIO61  ( HPS_GSENSOR_INT ),  //                               .hps_io_gpio_inst_GPIO61
-		//FPGA Partion
-	  .led_pio_external_connection_export    ( fpga_led_internal 	),    //    led_pio_external_connection.export
-	  .dipsw_pio_external_connection_export  ( SW	),  //  dipsw_pio_external_connection.export
-	  .button_pio_external_connection_export ( fpga_debounced_buttons	), // button_pio_external_connection.export
-	  .hps_0_h2f_reset_reset_n               ( hps_fpga_reset_n ),                //                hps_0_h2f_reset.reset_n
-	  .hps_0_f2h_cold_reset_req_reset_n      (~hps_cold_reset ),      //       hps_0_f2h_cold_reset_req.reset_n
-     .hps_0_f2h_debug_reset_req_reset_n     (~hps_debug_reset ),     //      hps_0_f2h_debug_reset_req.reset_n
-     .hps_0_f2h_stm_hw_events_stm_hwevents  (stm_hw_events ),  //        hps_0_f2h_stm_hw_events.stm_hwevents
-     .hps_0_f2h_warm_reset_req_reset_n      (~hps_warm_reset ),      //       hps_0_f2h_warm_reset_req.reset_n
-
- );
-
-// Debounce logic to clean out glitches within 1ms
-debounce debounce_inst (
-  .clk                                  (fpga_clk_50),
-  .reset_n                              (hps_fpga_reset_n),
-  .data_in                              (KEY),
-  .data_out                             (fpga_debounced_buttons)
-);
-  defparam debounce_inst.WIDTH = 2;
-  defparam debounce_inst.POLARITY = "LOW";
-  defparam debounce_inst.TIMEOUT = 50000;               // at 50Mhz this is a debounce time of 1ms
-  defparam debounce_inst.TIMEOUT_WIDTH = 16;            // ceil(log2(TIMEOUT))
-
-// Source/Probe megawizard instance
-hps_reset hps_reset_inst (
-  .source_clk (fpga_clk_50),
-  .source     (hps_reset_req)
-);
-
-altera_edge_detector pulse_cold_reset (
-  .clk       (fpga_clk_50),
-  .rst_n     (hps_fpga_reset_n),
-  .signal_in (hps_reset_req[0]),
-  .pulse_out (hps_cold_reset)
-);
-  defparam pulse_cold_reset.PULSE_EXT = 6;
-  defparam pulse_cold_reset.EDGE_TYPE = 1;
-  defparam pulse_cold_reset.IGNORE_RST_WHILE_BUSY = 1;
-
-altera_edge_detector pulse_warm_reset (
-  .clk       (fpga_clk_50),
-  .rst_n     (hps_fpga_reset_n),
-  .signal_in (hps_reset_req[1]),
-  .pulse_out (hps_warm_reset)
-);
-  defparam pulse_warm_reset.PULSE_EXT = 2;
-  defparam pulse_warm_reset.EDGE_TYPE = 1;
-  defparam pulse_warm_reset.IGNORE_RST_WHILE_BUSY = 1;
-
-altera_edge_detector pulse_debug_reset (
-  .clk       (fpga_clk_50),
-  .rst_n     (hps_fpga_reset_n),
-  .signal_in (hps_reset_req[2]),
-  .pulse_out (hps_debug_reset)
-);
-  defparam pulse_debug_reset.PULSE_EXT = 32;
-  defparam pulse_debug_reset.EDGE_TYPE = 1;
-  defparam pulse_debug_reset.IGNORE_RST_WHILE_BUSY = 1;
-
-reg [25:0] counter;
-reg  led_level;
-always @	(posedge fpga_clk_50 or negedge hps_fpga_reset_n)
-begin
-if(~hps_fpga_reset_n)
-begin
-		counter<=0;
-		led_level<=0;
-end
-
-else if(counter==24999999)
-	begin
-		counter<=0;
-		led_level<=~led_level;
-	end
-else
-		counter<=counter+1'b1;
-end
-
-assign LED[0]=led_level;
-
-
-
-endmodule
diff --git a/HW/QuartusProjects/SoCkit_GHRD/Makefile b/HW/QuartusProjects/SoCkit_GHRD/Makefile
deleted file mode 100755
index 640eec6b..00000000
--- a/HW/QuartusProjects/SoCkit_GHRD/Makefile
+++ /dev/null
@@ -1,734 +0,0 @@
-################################################
-#
-# Makefile to Manage QuartusII/QSys Design
-#
-# Copyright Altera (c) 2015
-# All Rights Reserved
-#
-################################################
-
-SHELL := /bin/bash
-
-.SUFFIXES: # Delete the default suffixes
-
-################################################
-# Tools
-
-CAT := cat
-CD := cd
-CHMOD := chmod
-CP := cp -rf
-ECHO := echo
-DATE := date
-FIND := find
-GREP := grep
-HEAD := head
-MKDIR := mkdir -p
-MV := mv
-RM := rm -rf
-SED := sed
-TAR := tar
-TOUCH := touch
-WHICH := which
-
-# Helpful Macros
-SPACE := $(empty) $(empty)
-
-ifndef COMSPEC
-ifdef ComSpec
-COMSPEC = $(ComSpec)
-endif # ComSpec
-endif # COMSPEC
-
-ifdef COMSPEC # if Windows OS
-IS_WINDOWS_HOST := 1
-endif
-
-ifeq ($(IS_WINDOWS_HOST),1)
-ifneq ($(shell $(WHICH) cygwin1.dll 2>/dev/null),)
-IS_CYGWIN_HOST := 1
-endif
-endif
-
-ifneq ($(shell $(WHICH) quartus 2>/dev/null),)
-HAVE_QUARTUS := 1
-endif
-
-ifeq ($(HAVE_QUARTUS),1)
-HAVE_QSYS := 1
-endif
-
-#<unused>
-#ifneq ($(shell $(WHICH) quartus_pgm 2>/dev/null),)
-#HAVE_QUARTUS_PGM := 1
-#endif
-
-################################################
-
-################################################
-.PHONY: default
-default: help
-################################################
-
-################################################
-.PHONY: all
-all: dts dtb rbf
-
-ifeq ($(HAVE_QUARTUS),1)
-all: sof rbf
-endif
-################################################
-
-################################################
-# Target Stamping
-
-SOCEDS_VERSION := $(if $(wildcard $(SOCEDS_DEST_ROOT)/version.txt),$(shell $(CAT) $(SOCEDS_DEST_ROOT)/version.txt 2>/dev/null | $(GREP) Version | $(HEAD) -n1 | $(SED) -e 's,^Version[: \t=]*\([0-9.]*\).*,\1,g' 2>/dev/null))
-
-define get_stamp_dir
-stamp$(if $(SOCEDS_VERSION),/$(SOCEDS_VERSION))
-endef
-
-define get_stamp_target
-$(get_stamp_dir)$(if $1,/$1.stamp,$(error ERROR: Arg 1 missing to $0 function))
-endef
-
-define stamp_target
-@$(MKDIR) $(@D)
-@$(TOUCH) $@
-endef
-
-.PHONY: clean
-clean:
-	@$(ECHO) "Cleaning stamp files (which will trigger rebuild)"
-	@$(RM) $(get_stamp_dir)
-	@$(ECHO) " TIP: Use 'make scrub_clean' to get a deeper clean"
-################################################
-
-
-################################################
-# Archiving & Cleaning your QuartusII/QSys Project
-
-AR_TIMESTAMP := $(if $(SOCEDS_VERSION),$(subst .,_,$(SOCEDS_VERSION))_)$(subst $(SPACE),,$(shell $(DATE) +%m%d%Y_%k%M%S))
-
-AR_DIR := tgz
-AR_FILE := $(AR_DIR)/$(basename $(firstword $(wildcard *.qpf)))_$(AR_TIMESTAMP).tar.gz
-
-SOFTWARE_DIR := software
-PRELOADER_DIR := $(SOFTWARE_DIR)/preloader
-
-AR_REGEX += \
-	Makefile ip readme.txt ds5 \
-	altera_avalon* *.qpf *.qsf *.sdc *.v *.sv *.vhd *.qsys *.tcl *.terp *.stp \
-	*.sed quartus.ini *.sof *.rbf *.sopcinfo *.jdi output_files *.sh *.ipx\
-	hps_isw_handoff */*.svd */synthesis/*.svd */synth/*.svd *.dts *.dtb *.xml \
-	$(SOFTWARE_DIR)
-
-AR_FILTER_OUT += %_tb.qsys
-################################################
-
-
-
-################################################
-# Build QuartusII/QSys Project
-#
-
-#############
-# QSys
-QSYS_FILE := $(firstword $(wildcard *top*.qsys) $(wildcard *main*.qsys) $(wildcard *soc*.qsys) $(wildcard *.qsys))
-ifeq ($(QSYS_FILE),)
-$(error ERROR: QSYS_FILE *.qsys file not set and could not be discovered)
-endif
-QSYS_DEPS += $(wildcard *.qsys)
-QSYS_BASE := $(basename $(QSYS_FILE))
-QSYS_QIP := $(wildard $(QSYS_BASE)/synthesis/$(QSYS_BASE).qip) $(wildcard $(QSYS_BASE)/$(QSYS_BASE).qip)
-QSYS_SOPCINFO := $(QSYS_BASE).sopcinfo
-QSYS_STAMP := $(call get_stamp_target,qsys)
-
-# Under cygwin, ensure TMP env variable is not a cygwin style path
-# before calling ip-generate
-ifeq ($(IS_CYGWIN_HOST),1)
-ifneq ($(shell $(WHICH) cygpath 2>/dev/null),)
-SET_QSYS_GENERATE_ENV = TMP="$(shell cygpath -m "$(TMP)")"
-endif
-endif
-
-.PHONY: qsys_compile
-qsys_compile: $(QSYS_STAMP)
-
-ifeq ($(HAVE_QSYS),1)
-$(QSYS_SOPCINFO) $(QSYS_QIP): $(QSYS_STAMP)
-endif
-
-$(QSYS_STAMP): $(QSYS_DEPS)
-	$(SET_QSYS_GENERATE_ENV) qsys-generate $(QSYS_FILE) --synthesis=VERILOG $(QSYS_GENERATE_ARGS)
-	$(stamp_target)
-
-HELP_TARGETS += qsys_edit
-
-qsys_edit.HELP := Launch QSys GUI
-ifneq ($(HAVE_QSYS),1)
-qsys_edit.HELP := $(qsys_edit.HELP) (Install Quartus II Software to enable)
-endif
-
-.PHONY: qsys_edit
-qsys_edit:
-	qsys-edit $(QSYS_FILE) &
-
-
-SCRUB_CLEAN_FILES += $(wildcard .qsys_edit)
-
-ifeq ($(HAVE_QSYS),1)
-SCRUB_CLEAN_FILES += $(QSYS_QIP) $(QSYS_SOPCINFO) $(QSYS_BASE)
-endif
-
-#############
-# Quartus II
-
-QUARTUS_QPF := $(firstword $(wildcard *.qpf))
-ifeq ($(QUARTUS_QPF),)
-$(error ERROR: QUARTUS_QPF *.qpf file not set and could not be discovered)
-endif
-QUARTUS_QSF := $(patsubst %.qpf,%.qsf,$(QUARTUS_QPF))
-QUARTUS_BASE := $(basename $(QUARTUS_QPF))
-QUARTUS_HDL_SOURCE := $(wildcard *.v *.sv *.vhd)
-QUARTUS_MISC_SOURCE := $(wildcard *.stp *.sdc)
-
-QUARTUS_PIN_ASSIGNMENTS_STAMP := $(call get_stamp_target,quartus_pin_assignments)
-QUARTUS_DEPS += $(QUARTUS_QPF) $(QUARTUS_QSF) $(QUARTUS_HDL_SOURCE) $(QUARTUS_MISC_SOURCE) $(QSYS_STAMP) $(QSYS_QIP) $(QUARTUS_PIN_ASSIGNMENTS_STAMP)
-
-QUARTUS_SOF := output_files/$(QUARTUS_BASE).sof
-QUARTUS_STAMP := $(call get_stamp_target,quartus)
-
-.PHONY: quartus_compile
-quartus_compile: $(QUARTUS_STAMP)
-
-ifeq ($(HAVE_QUARTUS),1)
-$(QUARTUS_SOF): $(QUARTUS_STAMP)
-endif
-
-$(QUARTUS_PIN_ASSIGNMENTS_STAMP): $(QSYS_STAMP)
-	quartus_map $(QUARTUS_QPF)
-	quartus_cdb --merge $(QUARTUS_QPF)
-	$(MAKE) quartus_apply_tcl_pin_assignments QUARTUS_ENABLE_PIN_ASSIGNMENTS_APPLY=1
-	$(stamp_target)
-
-#######
-# we need to recursively call this makefile to
-# apply *_pin_assignments.tcl script because the
-# pin_assignment.tcl files may not exist yet
-# when makefile was originally called
-
-ifeq ($(QUARTUS_ENABLE_PIN_ASSIGNMENTS_APPLY),1)
-
-QUARTUS_TCL_PIN_ASSIGNMENTS = $(wildcard $(QSYS_BASE)/synthesis/submodules/*_pin_assignments.tcl) $(wildcard $(QSYS_BASE)/synth/submodules/*_pin_assignments.tcl)
-QUARTUS_TCL_PIN_ASSIGNMENTS_APPLY_TARGETS = $(patsubst %,quartus_apply_tcl-%,$(QUARTUS_TCL_PIN_ASSIGNMENTS))
-
-.PHONY: quartus_apply_tcl_pin_assignments
-quartus_apply_tcl_pin_assignments: $(QUARTUS_TCL_PIN_ASSIGNMENTS_APPLY_TARGETS)
-
-.PHONY: $(QUARTUS_TCL_PIN_ASSIGNMENTS_APPLY_TARGETS)
-$(QUARTUS_TCL_PIN_ASSIGNMENTS_APPLY_TARGETS): quartus_apply_tcl-%: %
-	@$(ECHO) "Applying $<... to $(QUARTUS_QPF)..."
-	quartus_sta -t $< $(QUARTUS_QPF)
-
-endif # QUARTUS_ENABLE_PIN_ASSIGNMENTS_APPLY == 1
-######
-
-$(QUARTUS_STAMP): $(QUARTUS_DEPS)
-	quartus_stp $(QUARTUS_BASE)
-	quartus_sh --flow compile $(QUARTUS_QPF)
-	$(stamp_target)
-
-HELP_TARGETS += quartus_edit
-quartus_edit.HELP := Launch Quartus II GUI
-
-ifneq ($(HAVE_QUARTUS),1)
-quartus_edit.HELP := $(quartus_edit.HELP) (Install Quartus II Software to enable)
-endif
-
-
-.PHONY: quartus_edit
-quartus_edit:
-	quartus $(QUARTUS_QPF) &
-
-HELP_TARGETS += sof
-sof.HELP := QSys generate & Quartus compile this design
-ifneq ($(HAVE_QUARTUS),1)
-sof.HELP := $(sof.HELP) (Install Quartus II Software to enable)
-endif
-
-BATCH_TARGETS += sof
-
-.PHONY: sof
-sof: $(QUARTUS_SOF)
-
-
-QUARTUS_RBF := $(patsubst %.sof,%.rbf,$(QUARTUS_SOF))
-#
-# This converts the sof into compressed, unencrypted
-# raw binary format corresponding to MSEL value of 8
-# in the FPGAMGRREGS_STAT register. If you read the
-# the whole register, it should be 0x50.
-#
-# CVSoC DevBoard SW1 MSEL should be set to up,down,up,down,up,up
-#
-# SoCKit: SW6 MSEL[4:0] should be set to 0 1 0 1 0
-#		FPP x32, Fast, compressed bitstream
-#
-
-ifeq ($(HAVE_QUARTUS),1)
-$(QUARTUS_RBF): $(QUARTUS_STAMP)
-endif
-
-QUARTUS_CPF_ENABLE_COMPRESSION ?= 1
-ifeq ($(QUARTUS_CPF_ENABLE_COMPRESSION),1)
-QUARTUS_CPF_ARGS += -o bitstream_compression=on
-endif
-
-$(QUARTUS_RBF): %.rbf: %.sof
-	quartus_cpf -c $(QUARTUS_CPF_ARGS) $< $@
-
-.PHONY: rbf
-rbf: $(QUARTUS_RBF)
-
-.PHONY: create_rbf
-create_rbf:
-	quartus_cpf -c $(QUARTUS_CPF_ARGS) $(QUARTUS_SOF) $(QUARTUS_RBF)
-
-
-ifeq ($(HAVE_QUARTUS),1)
-SCRUB_CLEAN_FILES += $(QUARTUS_SOF) $(QUARTUS_RBF) output_files hps_isw_handoff
-endif
-
-################################################
-
-
-################################################
-# QSYS/Quartus Project Generation
-#  - we don't run this generation step automatically because
-#    it will destroy any changes and/or customizations that
-#    you've made to your qsys or your quartus project
-#
-QSYS_QSYS_GEN := $(firstword $(wildcard create_*_qsys.tcl))
-QUARTUS_TOP_GEN := $(firstword $(wildcard create_*_top.tcl))
-QUARTUS_QSF_QPF_GEN := $(firstword $(wildcard create_*_quartus.tcl))
-
-.PHONY: quartus_generate_qsf_qpf
-ifneq ($(QUARTUS_QSF_QPF_GEN),)
-quartus_generate_qsf_qpf: $(QUARTUS_QSF_QPF_GEN)
-	$(RM) $(QUARTUS_QSF) $(QUARTUS_QPF)
-	quartus_sh --script=$< $(QUARTUS_TCL_ARGS)
-else
-quartus_generate_qsf_qpf:
-	@$(ECHO) "Make target '$@' is not supported for this design"
-endif
-
-.PHONY: quartus_generate_top
-ifneq ($(QUARTUS_TOP_GEN),)
-quartus_generate_top: $(QUARTUS_TOP_GEN)
-	@$(RM) *_top.v
-	quartus_sh --script=$< $(QUARTUS_TCL_ARGS)
-else
-quartus_generate_top:
-	@$(ECHO) "Make target '$@' is not supported for this design"
-endif
-
-.PHONY: qsys_generate_qsys
-ifneq ($(QSYS_QSYS_GEN),)
-
-# Note that this target has a strange & known issue
-# that requires the Stratix V device family to be installed.
-# If the stratix V device family is not installed then the target
-# will hang. This issue will hopefully be resolved in a future
-# version of quartus/qsys.
-
-qsys_generate_qsys: $(QSYS_QSYS_GEN)
-	$(RM) $(QSYS_FILE)
-	qsys-script --script=$< $(QSYS_TCL_ARGS)
-else
-qsys_generate_qsys:
-	@$(ECHO) "Make target '$@' is not supported for this design"
-endif
-################################################
-
-
-################################################
-# Quartus Programming
-QUARTUS_PGM_STAMP := $(call get_stamp_target,quartus_pgm)
-
-# set these for your board
-# BOARD_CABLE =
-
-# FPGA Board Device Index. Default to 2 since this is the most
-#  common setting for dev board
-# For SoCKIT board, this should be set to 1
-BOARD_DEVICE_INDEX ?= 1
-
-define quartus_pgm_sof
-jtagconfig
-quartus_pgm --mode=jtag $(if $(BOARD_CABLE),--cable="$(BOARD_CABLE)") --operation=p\;$1$(if $(BOARD_DEVICE_INDEX),"@$(BOARD_DEVICE_INDEX)")
-jtagconfig $(if $(BOARD_CABLE),-c "$(BOARD_CABLE)") -n
-endef
-
-.PHONY: pgm
-pgm: $(QUARTUS_PGM_STAMP)
-
-$(QUARTUS_PGM_STAMP): $(QUARTUS_SOF)
-	$(call quartus_pgm_sof,$<)
-	$(stamp_target)
-
-HELP_TARGETS += program_fpga
-program_fpga.HELP := Quartus program sof to your attached dev board
-
-.PHONY: program_fpga
-program_fpga:
-	$(call quartus_pgm_sof,$(QUARTUS_SOF))
-
-
-# HPS Device Index. Default to 1 since this is the most
-#  common setting for dev board
-BOARD_HPS_DEVICE_INDEX ?= 1
-
-define quartus_hps_pgm_qspi
-jtagconfig
-quartus_hps $(if $(BOARD_CABLE),--cable="$(BOARD_CABLE)") $(if $(BOARD_HPS_DEVICE_INDEX),--device=$(BOARD_HPS_DEVICE_INDEX)) --operation=PV $1
-endef
-
-HELP_TARGETS += program_qspi
-program_qspi.HELP := Flash program preloader into QSPI Flash
-
-.PHONY: program_qspi
-program_qspi: $(PRELOADER_DIR)/preloader-mkpimage.bin
-	$(call quartus_hps_pgm_qspi,$<)
-
-
-# GHRD HPS Reset Targets
-ifneq ($(wildcard ghrd_reset.tcl),)
-# use the already programmed fpga to reset the hps
-HPS_RESET_TARGETS := hps_cold_reset hps_warm_reset hps_debug_reset
-
-.PHONY: $(HPS_RESET_TARGETS)
-$(HPS_RESET_TARGETS): hps_%_reset:
-	quartus_stp --script=ghrd_reset.tcl $(if $(BOARD_CABLE),--cable-name "$(BOARD_CABLE)") $(if $(BOARD_DEVICE_INDEX),--device-index "$(BOARD_DEVICE_INDEX)") --$*-reset
-endif
-
-################################################
-
-
-################################################
-# Preloader
-
-QSYS_HPS_INST_NAME ?= hps_0
-
-SBT.CREATE_SETTINGS := bsp-create-settings
-SBT.GENERATE := bsp-generate-files
-
-HELP_TARGETS += preloader
-preloader.HELP := Build Preloader BSP for this design into $(PRELOADER_DIR) directory
-
-PRELOADER_ID := hps_isw_handoff/$(QSYS_BASE)_$(QSYS_HPS_INST_NAME)/id
-PRELOADER_DEPS += $(PRELOADER_ID)
-
-ifeq ($(HAVE_QUARTUS),1)
-PRELOADER_DEPS += $(QUARTUS_STAMP)
-
-$(PRELOADER_ID): $(QUARTUS_STAMP)
-endif
-
-PRELOADER_STAMP := $(call get_stamp_target,preloader)
-
-PRELOADER_DISABLE_WATCHDOG ?= 1
-ifeq ($(PRELOADER_DISABLE_WATCHDOG),1)
-PRELOADER_EXTRA_ARGS += --set spl.boot.WATCHDOG_ENABLE false
-endif
-
-PRELOADER_ENABLE_ECC_SCRUBBING ?= 0
-ifeq ($(PRELOADER_ENABLE_ECC_SCRUBBING),1)
-# If enabled, we should scrub all 1GB of DDR. This may be overkill
-PRELOADER_EXTRA_ARGS += \
-	--set spl.boot.SDRAM_SCRUBBING true
-endif
-
-
-.PHONY: preloader
-preloader: $(PRELOADER_STAMP)
-
-# Create and build preloader with watchdog disabled.
-# This is useful for board bring up and troubleshooting.
-$(PRELOADER_STAMP): $(PRELOADER_DEPS)
-
-	@$(MKDIR) $(PRELOADER_DIR)
-
-	$(SBT.CREATE_SETTINGS) \
-		--type spl \
-		--bsp-dir $(PRELOADER_DIR) \
-		--preloader-settings-dir "hps_isw_handoff/$(QSYS_BASE)_$(QSYS_HPS_INST_NAME)" \
-		--settings $(PRELOADER_DIR)/settings.bsp \
-		$(PRELOADER_EXTRA_ARGS)
-
-	$(MAKE) -C $(PRELOADER_DIR)
-
-	$(stamp_target)
-
-
-UBOOT_STAMP := $(call get_stamp_target,uboot)
-
-$(UBOOT_STAMP): $(PRELOADER_STAMP)
-	$(MAKE) -C $(PRELOADER_DIR) uboot
-	$(stamp_target)
-
-
-ifeq ($(IS_WINDOWS_HOST),1)
-EXE_EXT := .exe
-endif
-UBOOT_MKIMAGE := $(PRELOADER_DIR)/uboot-socfpga/tools/mkimage$(EXE_EXT)
-AR_REGEX += $(UBOOT_MKIMAGE)
-
-
-HELP_TARGETS += uboot
-uboot.HELP := Build U-Boot into $(PRELOADER_DIR) directory
-
-.PHONY: uboot
-uboot: $(UBOOT_STAMP)
-
-
-SCRUB_CLEAN_FILES += $(PRELOADER_DIR)
-
-################################################
-
-
-################################################
-# Preloader/Uboot SD Card Programming
-
-# Update the A2 Partition on your sd card with
-# the preloader and uboot that build with this design
-
-# These targets assume you have a pre-imaged sd card
-# or an sd card *.img file
-# An example sd image for the Altera SoC Development
-# Board can be found here:
-# <soceds_install>/embeddedsw/socfpga/prebuilt_images
-
-ALT_BOOT_DISK_UTIL := alt-boot-disk-util
-
-ifeq ($(IS_WINDOWS_HOST),1)
-
-ifeq ($(SDCARD),)
-ifeq ($(SD_DRIVE_LETTER),)
-GUESS_DRIVE_LETTER = $(firstword $(foreach drive_letter,d e f g h i j k l m n o p q r s t u v w x y z,$(if $(wildcard $(drive_letter):/zImage),$(drive_letter))))
-SD_DRIVE_LETTER = $(GUESS_DRIVE_LETTER)
-endif # SD_DRIVE_LETTER == <empty>
-SDCARD ?= $(if $(SD_DRIVE_LETTER),-d $(SD_DRIVE_LETTER),$(error ERROR: SD_DRIVE_LETTER not specified. Try "make $(MAKECMDGOALS) SD_DRIVE_LETTER=[sd_card_windows_drive_letter]"))
-endif # SDCARD == <empty>
-
-else # if not a Windows Host
-
-SDCARD ?= $(error ERROR: SD Card not specified. Try "make $(MAKECMDGOALS) SDCARD=/dev/sdX", where X represents your target SD Card device)
-
-endif
-
-PRELOADER_BIN ?= $(PRELOADER_DIR)/preloader-mkpimage.bin
-
-.PHONY: sd-update-preloader
-sd-update-preloader: $(PRELOADER_BIN)
-	$(ALT_BOOT_DISK_UTIL) -p $< -a write $(SDCARD)
-
-NEXTSTAGE_BIN ?= $(PRELOADER_DIR)/uboot-socfpga/u-boot.img
-
-.PHONY: sd-update-uboot
-sd-update-uboot: $(NEXTSTAGE_BIN)
-	$(ALT_BOOT_DISK_UTIL) -b $< -a write $(SDCARD)
-
-sd-update-preloader-uboot: sd-update-preloader sd-update-uboot
-
-################################################
-
-
-################################################
-# Device Tree
-
-DTS.SOPC2DTS := sopc2dts
-DTS.DTC := dtc
-
-DTS.BOARDINFO ?= $(QSYS_BASE)_board_info.xml
-DTS.COMMON ?= hps_common_board_info.xml
-
-DTS.EXTRA_DEPS += $(DTS.BOARDINFO) $(DTS.COMMON)
-
-DTS.SOPC2DTS_ARGS += $(if $(DTS.BOARDINFO),--board $(DTS.BOARDINFO))
-DTS.SOPC2DTS_ARGS += $(if $(DTS.COMMON),--board $(DTS.COMMON))
-DTS.SOPC2DTS_ARGS += --bridge-removal all
-DTS.SOPC2DTS_ARGS += --clocks
-
-define dts.sopc2dts
-$(if $(DTS.BOARDINFO),,$(warning WARNING: DTS BoardInfo file was not specified or found))
-$(DTS.SOPC2DTS) --input $1 --output $2 $3 $(DTS.SOPC2DTS_ARGS)
-endef
-
-
-# Device Tree Source (dts)
-DEVICE_TREE_SOURCE := $(patsubst %.sopcinfo,%.dts,$(QSYS_SOPCINFO))
-
-HELP_TARGETS += dts
-dts.HELP := Generate a device tree for this qsys design
-
-.PHONY: dts
-dts: $(DEVICE_TREE_SOURCE)
-
-ifeq ($(HAVE_QSYS),1)
-$(DEVICE_TREE_SOURCE): $(QSYS_STAMP)
-endif
-
-$(DEVICE_TREE_SOURCE): %.dts: %.sopcinfo $(DTS.EXTRA_DEPS)
-	$(call dts.sopc2dts,$<,$@)
-
-
-# Device Tree Blob (dtb)
-DEVICE_TREE_BLOB := $(patsubst %.sopcinfo,%.dtb,$(QSYS_SOPCINFO))
-
-HELP_TARGETS += dtb
-dtb.HELP := Generate a device tree blob for this qsys design
-
-.PHONY: dtb
-dtb: $(DEVICE_TREE_BLOB)
-
-ifeq ($(HAVE_QSYS),1)
-$(DEVICE_TREE_BLOB): $(QSYS_STAMP)
-endif
-
-$(DEVICE_TREE_BLOB): %.dtb: %.dts
-	$(DTS.DTC) -I dts -O dtb -o $@ $<
-
-SCRUB_CLEAN_FILES += $(DEVICE_TREE_SOURCE) $(DEVICE_TREE_BLOB)
-
-################################################
-
-
-################################################
-boot.script: Makefile
-	@$(RM) $@
-	@$(ECHO) "Generating $@"
-	@$(ECHO) "fatload mmc 0:1 \$$fpgadata $(QUARTUS_RBF);" >>$@
-	@$(ECHO) "fpga load 0 \$$fpgadata \$$filesize;" >>$@
-	@$(ECHO) "setenv fdtimage $(DEVICE_TREE_BLOB);" >>$@
-	@$(ECHO) "run bridge_enable_handoff;" >>$@
-	@$(ECHO) "run mmcload;" >>$@
-	@$(ECHO) "run mmcboot;" >>$@
-
-ifeq ($(wildcard $(UBOOT_MKIMAGE)),)
-$(UBOOT_MKIMAGE): $(PRELOADER_STAMP)
-endif
-
-u-boot.scr: boot.script $(UBOOT_MKIMAGE)
-	$(UBOOT_MKIMAGE) -A arm -O linux -T script -C none -a 0 -e 0 -n "bootscript" -d $< $@
-
-SD_FAT_TGZ ?= sd_fat.tar.gz
-SD_FAT_TGZ_DEPS += u-boot.scr boot.script $(QUARTUS_RBF) $(DEVICE_TREE_BLOB)
-
-$(SD_FAT_TGZ): $(SD_FAT_TGZ_DEPS)
-	@$(RM) $@
-	@$(MKDIR) $(@D)
-	$(TAR) -czf $@ $^
-
-.PHONY: sd-fat
-sd-fat: $(SD_FAT_TGZ)
-
-AR_FILES += $(wildcard $(SD_FAT_TGZ))
-
-SCRUB_CLEAN_FILES += $(SD_FAT_TGZ)
-
-################################################
-
-
-################################################
-# Clean-up and Archive
-
-AR_FILES += $(filter-out $(AR_FILTER_OUT),$(wildcard $(AR_REGEX)))
-
-TOP_DIR=top
-
-CLEAN_FILES += $(filter-out $(TOP_DIR) $(AR_DIR) $(AR_FILES),$(wildcard *))
-
-HELP_TARGETS += tgz
-tgz.HELP := Create a tarball with the barebones source files that comprise this design
-
-.PHONY: tarball tgz
-tarball tgz: $(AR_FILE)
-
-$(AR_FILE):
-	@$(MKDIR) $(@D)
-	@$(if $(wildcard $(@D)/*.tar.gz),$(MKDIR) $(@D)/.archive;$(MV) $(@D)/*.tar.gz $(@D)/.archive)
-	@$(ECHO) "Generating $@..."
-	@$(TAR) -czf $@ $(AR_FILES)
-
-SCRUB_CLEAN_FILES += $(CLEAN_FILES)
-
-HELP_TARGETS += scrub_clean
-scrub_clean.HELP := Restore design to its barebones state
-
-.PHONY: scrub scrub_clean
-scrub scrub_clean:
-	$(if $(strip $(wildcard $(SCRUB_CLEAN_FILES))),$(RM) $(wildcard $(SCRUB_CLEAN_FILES)),@$(ECHO) "You're already as clean as it gets!")
-
-.PHONY: tgz_scrub_clean
-tgz_scrub_clean:
-	$(FIND) $(SOFTWARE_DIR) \( -name '*.o' -o -name '.depend*' -o -name '*.d' -o -name '*.dep' \) -delete || true
-	$(MAKE) tgz AR_FILE=$(AR_FILE)
-	$(MAKE) -s scrub_clean
-	$(TAR) -xzf $(AR_FILE)
-
-################################################
-
-
-################################################
-# Running Batch Jobs
-ifneq ($(BATCH_TARGETS),)
-
-BATCH_DIR := $(if $(TMP),$(TMP)/)batch/$(AR_TIMESTAMP)
-
-.PHONY: $(patsubst %,batch-%,$(BATCH_TARGETS))
-$(patsubst %,batch-%,$(BATCH_TARGETS)): batch-%: $(AR_FILE)
-	@$(RM) $(BATCH_DIR)
-	@$(MKDIR) $(BATCH_DIR)
-	$(CP) $< $(BATCH_DIR)
-	$(CD) $(BATCH_DIR) && $(TAR) -xzf $(notdir $<) && $(CHMOD) -R 755 *
-	$(MAKE) -C $(BATCH_DIR) $*
-
-endif # BATCH_TARGETS != <empty>
-################################################
-
-
-################################################
-# Help system
-
-HELP_TARGETS += help
-help.HELP := Displays this info (i.e. the available targets)
-
-.PHONY: help
-help: help-init help-targets help-fini
-
-HELP_TARGETS_X := $(patsubst %,help-%,$(sort $(HELP_TARGETS)))
-.PHONY: $(HELP_TARGETS_X)
-help-targets: $(HELP_TARGETS_X)
-$(HELP_TARGETS_X): help-%:
-	@$(ECHO) "*********************"
-	@$(ECHO) "* Target: $*"
-	@$(ECHO) "*   $($*.HELP)"
-
-.PHONY: help-init
-help-init:
-	@$(ECHO) "*****************************************"
-	@$(ECHO) "*                                       *"
-	@$(ECHO) "* Manage QuartusII/QSys design          *"
-	@$(ECHO) "*                                       *"
-	@$(ECHO) "*     Copyright (c) 2015                *"
-	@$(ECHO) "*     All Rights Reserved               *"
-	@$(ECHO) "*                                       *"
-	@$(ECHO) "*****************************************"
-	@$(ECHO) ""
-
-.PHONY: help-fini
-help-fini:
-	@$(ECHO) "*********************"
-
-################################################
diff --git a/HW/QuartusProjects/SoCkit_GHRD/hps_common_board_info-sockit-15.1.xml b/HW/QuartusProjects/SoCkit_GHRD/hps_common_board_info-sockit-15.1.xml
deleted file mode 100755
index 02c35d8b..00000000
--- a/HW/QuartusProjects/SoCkit_GHRD/hps_common_board_info-sockit-15.1.xml
+++ /dev/null
@@ -1,241 +0,0 @@
-<BoardInfo>
-
-<!--
-Starting in the 3.11 kernel, the ethernet driver looks for alias
-in the device tree for a bus_id used to talk the phy.  Having
-these aliases allows seamless support of multiple emacs
--->
-<alias name="ethernet0" value="/sopc@0/ethernet@0xff702000"/>
-<alias name="spi0" value="/sopc@0/spi@0xfff00000"/>
-<alias name="spi1" value="/sopc@0/spi@0xfff01000"/>
-
-
-<DTAppend name="next-level-cache" type="phandle" parentlabel="hps_0_arm_a9_0" val="hps_0_L2"/>
-<DTAppend name="next-level-cache" type="phandle" parentlabel="hps_0_arm_a9_1" val="hps_0_L2"/>
-
-<DTAppend name="cache-unified" type="bool" parentlabel="hps_0_L2" val="true"/>
-<DTAppend name="arm,tag-latency" parentlabel="hps_0_L2">
-	<val type="number">1</val>
-	<val type="number">1</val>
-	<val type="number">1</val>
-</DTAppend>
-<DTAppend name="arm,data-latency" parentlabel="hps_0_L2">
-	<val type="number">2</val>
-	<val type="number">1</val>
-	<val type="number">1</val>
-</DTAppend>
-
-<DTAppend name="status" type="string" parentlabel="hps_0_wd_timer1" val="disabled" />
-<DTAppend name="phy-mode" type="string" parentlabel="hps_0_gmac1" val="rgmii"/>
-
-<DTAppend name="snps,multicast-filter-bins" type="number" parentlabel="hps_0_gmac1" val="256"/>
-<DTAppend name="snps,perfect-filter-entries" type="number" parentlabel="hps_0_gmac1" val="128"/>
-<DTAppend name="txc-skew-ps" type="number" parentlabel="hps_0_gmac1" val="3000"/>
-<DTAppend name="rxc-skew-ps" type="number" parentlabel="hps_0_gmac1" val="3000"/>
-<DTAppend name="txen-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="rxdv-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="rxd0-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="rxd1-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="rxd2-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="rxd3-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="txd0-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="txd1-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="txd2-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="txd3-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="max-frame-size" type="number" parentlabel="hps_0_gmac1" val="3800"/>
-
-
-<!--<DTAppend name="speed-mode" type="number" parentlabel="hps_0_i2c0" val="0"/>-->
-<!-- adjust the falling times to decrease the i2c frequency to 50Khz
-     because the LCD module does not work at the standard 100Khz
--->
-<!-- remove for SoCKit
-<DTAppend name="i2c-sda-falling-time-ns" type="number" parentlabel="hps_0_i2c0" val="5000"/>
-<DTAppend name="i2c-scl-falling-time-ns" type="number" parentlabel="hps_0_i2c0" val="5000"/>
-
-<I2CBus master="hps_0_i2c0">
-	<I2CChip addr="0x28" label="lcd" name="newhaven,nhd-0216k3z-nsw-bbw"></I2CChip>
-	<I2CChip addr="0x51" label="eeprom" name="atmel,24c32"></I2CChip>
-	<I2CChip addr="0x68" label="rtc" name="dallas,ds1339"></I2CChip>
-</I2CBus>
-<DTAppend name="height" type="number" parentlabel="lcd" val="2"/>
-<DTAppend name="width" type="number" parentlabel="lcd" val="16"/>
-<DTAppend name="brightness" type="number" parentlabel="lcd" val="8"/>
-<DTAppend name="pagesize" type="number" parentlabel="eeprom" val="32"/>
--->
-
-<DTAppend name="#address-cells" type="number" parentlabel="hps_0_sdmmc" val="1"/>
-<DTAppend name="#size-cells" type="number" parentlabel="hps_0_sdmmc" val="0"/>
-<DTAppend name="supports-highspeed"  parentlabel="hps_0_sdmmc" />
-<DTAppend name="broken-cd" type="bool" parentlabel="hps_0_sdmmc" val="true"/>
-<DTAppend name="compatible" type="string" parentlabel="hps_0_sdmmc" val="altr,socfpga-dw-mshc" action="replace"/>
-<DTAppend name="altr,dw-mshc-ciu-div" type="number" parentlabel="hps_0_sdmmc" val="3"/>
-<DTAppend name="altr,dw-mshc-sdr-timing"  parentlabel="hps_0_sdmmc" >
-<val type="number">0</val>
-<val type="number">3</val>
-</DTAppend>
-<DTAppend name="slot@0" type="node" parentlabel="hps_0_sdmmc" newlabel="slot_0"/>
-<DTAppend name="reg" type="number" parentlabel="slot_0" val="0"/>
-<DTAppend name="bus-width" type="number" parentlabel="slot_0" val="4"/>
-
-<DTAppend name="#address-cells" type="number" parentlabel="hps_0_qspi" val="1"/>
-<DTAppend name="#size-cells" type="number" parentlabel="hps_0_qspi" val="0"/>
-<DTAppend name="master-ref-clk" type="number" parentlabel="hps_0_qspi" val="400000000"/>
-<DTAppend name="ext-decoder" type="number" parentlabel="hps_0_qspi" val="0"/>
-<DTAppend name="#address-cells" type="number" parentlabel="flash0" val="1"/>
-<DTAppend name="#size-cells" type="number" parentlabel="flash0" val="1"/>
-<DTAppend name="reg" type="number" parentlabel="flash0" val="0"/>
-<DTAppend name="spi-max-frequency" type="number" parentlabel="flash0" val="100000000"/>
-<DTAppend name="page-size" type="number" parentlabel="flash0" val="256"/>
-<DTAppend name="block-size" type="number" parentlabel="flash0" val="16"/>
-<DTAppend name="m25p,fast-read" type="bool" parentlabel="flash0" val="true"/>
-<DTAppend name="read-delay" type="number" parentlabel="flash0" val="4"/>
-<DTAppend name="tshsl-ns" type="number" parentlabel="flash0" val="50"/>
-<DTAppend name="tsd2d-ns" type="number" parentlabel="flash0" val="50"/>
-<DTAppend name="tchsh-ns" type="number" parentlabel="flash0" val="4"/>
-<DTAppend name="tslch-ns" type="number" parentlabel="flash0" val="4"/>
-
-<DTAppend name="spidev@0" type="node" parentlabel="hps_0_spim0" newlabel="spidev0"/>
-<DTAppend name="compatible" type="string" parentlabel="spidev0" val="spidev"/>
-<DTAppend name="reg" type="number" parentlabel="spidev0" val="0"/>
-<DTAppend name="spi-max-frequency" type="number" parentlabel="spidev0" val="100000000"/>
-<DTAppend name="enable-dma" type="number" parentlabel="spidev0" val="1"/>
-
-<DTAppend name="spidev@0" type="node" parentlabel="hps_0_spim1" newlabel="spidev1"/>
-<DTAppend name="compatible" type="string" parentlabel="spidev1" val="spidev"/>
-<DTAppend name="reg" type="number" parentlabel="spidev1" val="0"/>
-<DTAppend name="spi-max-frequency" type="number" parentlabel="spidev1" val="100000000"/>
-<DTAppend name="enable-dma" type="number" parentlabel="spidev1" val="1"/>
-
-<DTAppend name="leds" type="node" parentlabel="sopc0" newlabel="soc_leds"/>
-<DTAppend name="compatible" type="string" parentlabel="soc_leds" val="gpio-leds"/>
-
-<DTAppend name="hps0" type="node" parentlabel="soc_leds" newlabel="led_hps0"/>
-<DTAppend name="hps1" type="node" parentlabel="soc_leds" newlabel="led_hps1"/>
-<DTAppend name="hps2" type="node" parentlabel="soc_leds" newlabel="led_hps2"/>
-<DTAppend name="hps3" type="node" parentlabel="soc_leds" newlabel="led_hps3"/>
-
-<DTAppend name="fpga0" type="node" parentlabel="soc_leds" newlabel="led_fpga0"/>
-<DTAppend name="fpga1" type="node" parentlabel="soc_leds" newlabel="led_fpga1"/>
-<DTAppend name="fpga2" type="node" parentlabel="soc_leds" newlabel="led_fpga2"/>
-<DTAppend name="fpga3" type="node" parentlabel="soc_leds" newlabel="led_fpga3"/>
-
-<DTAppend name="label" type="string" parentlabel="led_hps0" val="hps_led0"/>
-<DTAppend name="gpios" parentlabel="led_hps0" >
-<val type="phandle">hps_0_gpio1_porta</val>
-<val type="number">27</val>
-<val type="number">1</val>
-</DTAppend>
-
-<DTAppend name="label" type="string" parentlabel="led_hps1" val="hps_led1"/>
-<DTAppend name="gpios" parentlabel="led_hps1" >
-<val type="phandle">hps_0_gpio1_porta</val>
-<val type="number">26</val>
-<val type="number">1</val>
-</DTAppend>
-
-<DTAppend name="label" type="string" parentlabel="led_hps2" val="hps_led2"/>
-<DTAppend name="gpios" parentlabel="led_hps2" >
-<val type="phandle">hps_0_gpio1_porta</val>
-<val type="number">25</val>
-<val type="number">1</val>
-</DTAppend>
-
-<DTAppend name="label" type="string" parentlabel="led_hps3" val="hps_led3"/>
-<DTAppend name="gpios" parentlabel="led_hps3" >
-<val type="phandle">hps_0_gpio1_porta</val>
-<val type="number">24</val>
-<val type="number">1</val>
-</DTAppend>
-
-<DTAppend name="label" type="string" parentlabel="led_fpga0" val="fpga_led0"/>
-<DTAppend name="gpios" parentlabel="led_fpga0" >
-<val type="phandle">led_pio</val>
-<val type="number">0</val>
-<val type="number">1</val>
-</DTAppend>
-
-<DTAppend name="label" type="string" parentlabel="led_fpga1" val="fpga_led1"/>
-<DTAppend name="gpios" parentlabel="led_fpga1" >
-<val type="phandle">led_pio</val>
-<val type="number">1</val>
-<val type="number">1</val>
-</DTAppend>
-
-<DTAppend name="label" type="string" parentlabel="led_fpga2" val="fpga_led2"/>
-<DTAppend name="gpios" parentlabel="led_fpga2" >
-<val type="phandle">led_pio</val>
-<val type="number">2</val>
-<val type="number">1</val>
-</DTAppend>
-
-<DTAppend name="label" type="string" parentlabel="led_fpga3" val="fpga_led3"/>
-<DTAppend name="gpios" parentlabel="led_fpga3" >
-<val type="phandle">led_pio</val>
-<val type="number">3</val>
-<val type="number">1</val>
-</DTAppend>
-
-<DTAppend name="pmu0" type="node" parentlabel="sopc0" newlabel="pmu"/>
-<DTAppend name="#address-cells" type="number" parentlabel="pmu" val="1"/>
-<DTAppend name="#size-cells" type="number" parentlabel="pmu" val="1"/>
-<DTAppend name="compatible" type="string" parentlabel="pmu" val="arm,cortex-a9-pmu"/>
-<DTAppend name="interrupt-parent" type="phandle" parentlabel="pmu" val="hps_0_arm_gic_0"/>
-<DTAppend name="interrupts" parentlabel="pmu">
-<val type="number">0</val>
-<val type="number">176</val>
-<val type="number">4</val>
-<val type="number">0</val>
-<val type="number">177</val>
-<val type="number">4</val>
-</DTAppend>
-<DTAppend name="ranges" type="bool" parentlabel="pmu" val="true"/>
-
-<DTAppend name="cti0@ff118000" type="node" parentlabel="pmu" newlabel="cti0"/>
-<DTAppend name="compatible" type="string" parentlabel="cti0" val="arm,coresight-cti"/>
-<DTAppend name="reg" parentlabel="cti0">
-<val type="hex">0xff118000</val>
-<val type="hex">0x1000</val>
-</DTAppend>
-
-<DTAppend name="cti0@ff119000" type="node" parentlabel="pmu" newlabel="cti1"/>
-<DTAppend name="compatible" type="string" parentlabel="cti1" val="arm,coresight-cti"/>
-<DTAppend name="reg" parentlabel="cti1">
-<val type="hex">0xff119000</val>
-<val type="hex">0x1000</val>
-</DTAppend>
-
-<DTAppend name="fpgabridge@0" type="node" parentlabel="sopc0" newlabel="fpgabridge0"/>
-<DTAppend name="compatible" type="string" parentlabel="fpgabridge0" val="altr,socfpga-hps2fpga-bridge"/>
-<DTAppend name="label" type="string" parentlabel="fpgabridge0" val="hps2fpga"/>
-<DTAppend name="clocks" type="phandle" parentlabel="fpgabridge0" val="l4_main_clk"/>
-
-<DTAppend name="fpgabridge@1" type="node" parentlabel="sopc0" newlabel="fpgabridge1"/>
-<DTAppend name="compatible" type="string" parentlabel="fpgabridge1" val="altr,socfpga-lwhps2fpga-bridge"/>
-<DTAppend name="label" type="string" parentlabel="fpgabridge1" val="lwhps2fpga"/>
-<DTAppend name="clocks" type="phandle" parentlabel="fpgabridge1" val="l4_main_clk"/>
-
-<DTAppend name="fpgabridge@2" type="node" parentlabel="sopc0" newlabel="fpgabridge2"/>
-<DTAppend name="compatible" type="string" parentlabel="fpgabridge2" val="altr,socfpga-fpga2hps-bridge"/>
-<DTAppend name="label" type="string" parentlabel="fpgabridge2" val="fpga2hps"/>
-<DTAppend name="clocks" type="phandle" parentlabel="fpgabridge2" val="l4_main_clk"/>
-<DTAppend name="usbphy@0" type="node" parentlabel="sopc0" newlabel="usbphy0" />
-<DTAppend name="#phy-cells" type="number" val="0" parentlabel="usbphy0" />
-<DTAppend name="compatible" type="string" val="usb-nop-xceiv" parentlabel="usbphy0" />
-<DTAppend name="status" type="string" val="okay" parentlabel="usbphy0" />
-
-<DTAppend name="phys" type="phandle" parentlabel="hps_0_usb1" val="usbphy0" />
-
-<DTappend name="bus-num" parentlabel="hps_0_spim0">
-<val type="hex">0x0</val>
-</DTappend>
-
-<DTappend name="bus-num" parentlabel="hps_0_spim1">
-<val type="hex">0x1</val>
-</DTappend>
-
-
-<Chosen>
-        <Bootargs val="console=ttyS0,115200"></Bootargs>
-</Chosen>
-</BoardInfo>
diff --git a/HW/QuartusProjects/SoCkit_GHRD/hps_common_board_info.xml b/HW/QuartusProjects/SoCkit_GHRD/hps_common_board_info.xml
deleted file mode 100755
index 5962f0df..00000000
--- a/HW/QuartusProjects/SoCkit_GHRD/hps_common_board_info.xml
+++ /dev/null
@@ -1,99 +0,0 @@
-<BoardInfo>
-
-<!--
-Starting in the 3.11 kernel, the ethernet driver looks for alias
-in the device tree for a bus_id used to talk the phy.  Having
-these aliases allows seamless support of multiple emacs
--->
-
-
-<DTAppend name="next-level-cache" type="phandle" parentlabel="hps_0_arm_a9_0" val="hps_0_L2"/>
-<DTAppend name="next-level-cache" type="phandle" parentlabel="hps_0_arm_a9_1" val="hps_0_L2"/>
-
-<DTAppend name="cache-unified" type="bool" parentlabel="hps_0_L2" val="true"/>
-<DTAppend name="arm,tag-latency" parentlabel="hps_0_L2">
-	<val type="number">1</val>
-	<val type="number">1</val>
-	<val type="number">1</val>
-</DTAppend>
-<DTAppend name="arm,data-latency" parentlabel="hps_0_L2">
-	<val type="number">2</val>
-	<val type="number">1</val>
-	<val type="number">1</val>
-</DTAppend>
-
-<DTAppend name="status" type="string" parentlabel="hps_0_wd_timer1" val="disabled" />
-
-<DTAppend name="compatible" type="string" parentlabel="hps_0_rstmgr" val="syscon" action="add"/>
-
-<DTAppend name="pmu0" type="node" parentlabel="sopc0" newlabel="pmu"/>
-<DTAppend name="#address-cells" type="number" parentlabel="pmu" val="1"/>
-<DTAppend name="#size-cells" type="number" parentlabel="pmu" val="1"/>
-<DTAppend name="compatible" type="string" parentlabel="pmu" val="arm,cortex-a9-pmu"/>
-<DTAppend name="interrupt-parent" type="phandle" parentlabel="pmu" val="hps_0_arm_gic_0"/>
-<DTAppend name="interrupts" parentlabel="pmu">
-<val type="number">0</val>
-<val type="number">176</val>
-<val type="number">4</val>
-<val type="number">0</val>
-<val type="number">177</val>
-<val type="number">4</val>
-</DTAppend>
-<DTAppend name="ranges" type="bool" parentlabel="pmu" val="true"/>
-
-<DTAppend name="cti0@ff118000" type="node" parentlabel="pmu" newlabel="cti0"/>
-<DTAppend name="compatible" type="string" parentlabel="cti0" val="arm,coresight-cti"/>
-<DTAppend name="reg" parentlabel="cti0">
-<val type="hex">0xff118000</val>
-<val type="hex">0x1000</val>
-</DTAppend>
-
-<DTAppend name="cti0@ff119000" type="node" parentlabel="pmu" newlabel="cti1"/>
-<DTAppend name="compatible" type="string" parentlabel="cti1" val="arm,coresight-cti"/>
-<DTAppend name="reg" parentlabel="cti1">
-<val type="hex">0xff119000</val>
-<val type="hex">0x1000</val>
-</DTAppend>
-
-<DTAppend name="fpgabridge@0" type="node" parentlabel="sopc0" newlabel="fpgabridge0"/>
-<DTAppend name="compatible" type="string" parentlabel="fpgabridge0" val="altr,socfpga-hps2fpga-bridge"/>
-<DTAppend name="label" type="string" parentlabel="fpgabridge0" val="hps2fpga"/>
-<DTAppend name="clocks" type="phandle" parentlabel="fpgabridge0" val="l4_main_clk"/>
-<DTAppend name="init-val" type="number" parentlabel="fpgabridge0" val="1"/>
-
-<DTAppend name="fpgabridge@1" type="node" parentlabel="sopc0" newlabel="fpgabridge1"/>
-<DTAppend name="compatible" type="string" parentlabel="fpgabridge1" val="altr,socfpga-lwhps2fpga-bridge"/>
-<DTAppend name="label" type="string" parentlabel="fpgabridge1" val="lwhps2fpga"/>
-<DTAppend name="clocks" type="phandle" parentlabel="fpgabridge1" val="l4_main_clk"/>
-<DTAppend name="init-val" type="number" parentlabel="fpgabridge1" val="1"/>
-
-<DTAppend name="fpgabridge@2" type="node" parentlabel="sopc0" newlabel="fpgabridge2"/>
-<DTAppend name="compatible" type="string" parentlabel="fpgabridge2" val="altr,socfpga-fpga2hps-bridge"/>
-<DTAppend name="label" type="string" parentlabel="fpgabridge2" val="fpga2hps"/>
-<DTAppend name="clocks" type="phandle" parentlabel="fpgabridge2" val="l4_main_clk"/>
-<DTAppend name="init-val" type="number" parentlabel="fpgabridge2" val="1"/>
-
-
-<DTAppend name="reg" parentlabel="hps_0_usb0">
-<val type="hex">0xffb00000</val>
-<val type="hex">0x40000</val>
-</DTAppend>
-
-<DTAppend name="reg" parentlabel="hps_0_usb1">
-<val type="hex">0xffb40000</val>
-<val type="hex">0x40000</val>
-</DTAppend>
-
-<DTAppend name="bus-num" parentlabel="hps_0_spim0">
-<val type="hex">0x0</val>
-</DTAppend>
-
-<DTAppend name="bus-num" parentlabel="hps_0_spim1">
-   <val type="hex">0x1</val>
-</DTAppend>
-
-<!--
-<DTAppend name="compatible" type="string" parentlabel="memcpy_msgdma" val="demo,memcpy_msgdma"/>
--->
-
-</BoardInfo>
diff --git a/HW/QuartusProjects/SoCkit_GHRD/soc_system.ipx b/HW/QuartusProjects/SoCkit_GHRD/soc_system.ipx
deleted file mode 100644
index 7012ab46..00000000
--- a/HW/QuartusProjects/SoCkit_GHRD/soc_system.ipx
+++ /dev/null
@@ -1,4 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<library>
- <path path="../../cv-ip/**/*" />
-</library>
diff --git a/HW/QuartusProjects/SoCkit_GHRD/soc_system.qpf b/HW/QuartusProjects/SoCkit_GHRD/soc_system.qpf
deleted file mode 100755
index 84788b06..00000000
--- a/HW/QuartusProjects/SoCkit_GHRD/soc_system.qpf
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.0.0 Build 144 02/27/2013 SJ Web Edition
-# Date created = 15:03:49  March 12, 2013
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.0"
-DATE = "15:03:49  March 12, 2013"
-
-# Revisions
-
-PROJECT_REVISION = "soc_system"
-
diff --git a/HW/QuartusProjects/SoCkit_GHRD/soc_system.qsf b/HW/QuartusProjects/SoCkit_GHRD/soc_system.qsf
deleted file mode 100755
index 24663d74..00000000
--- a/HW/QuartusProjects/SoCkit_GHRD/soc_system.qsf
+++ /dev/null
@@ -1,1158 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2012 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors.  Please refer to the
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 12.1 Build 177 11/07/2012 Service Pack 0.dp5;1 SJ Full Version
-# Date created = 13:31:48  January 25, 2013
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		soc_system_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-set_global_assignment -name FAMILY "Cyclone V"
-set_global_assignment -name DEVICE 5CSXFC6D6F31C8ES
-set_global_assignment -name TOP_LEVEL_ENTITY ghrd_top
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:03:48  MARCH 12, 2013"
-
-#============================================================
-# common MESA Hostmot 2 Sources:
-
-# MESA board , pin and daughter card config options:
-set_global_assignment -name QIP_FILE ../../hm2/config/hm2_i25_G540x2_34_config.qip
-#============================================================
-
-set_global_assignment -name LAST_QUARTUS_VERSION 15.1.2
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity soc_system -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity soc_system -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -entity soc_system -section_id Top
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_mem_stable_n -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_n -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to hps_0|hps_io|border|hps_sdram_inst -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to hps_0|hps_io|border|hps_sdram_inst|pll0|fbout -entity soc_system -tag __hps_sdram_p0
-set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name ECO_REGENERATE_REPORT ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
-set_global_assignment -name IOBANK_VCCIO 1.5V -section_id 4A
-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3A
-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7A
-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7B
-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7C
-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7D
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3] -entity soc_system -tag __hps_sdram_p0
-
-
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_ba -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dm -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dqs -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dqs_n -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_oct_rzqin -entity soc_system -tag __hps_sdram_p0
-
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[0] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[0] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[1] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[1] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[2] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[2] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[3] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[3] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[4] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[4] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[5] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[5] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[6] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[6] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[7] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[7] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[8] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[8] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[9] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[9] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[10] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[10] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[11] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[11] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[12] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[12] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[13] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[13] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[14] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[14] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[15] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[15] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[16] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[16] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[17] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[17] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[18] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[18] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[19] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[19] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[20] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[20] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[21] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[21] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[22] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[22] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[23] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[23] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[24] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[24] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[25] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[25] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[26] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[26] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[27] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[27] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[28] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[28] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[29] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[29] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[30] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[30] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[31] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[31] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs[0] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs[0] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs[1] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs[1] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs[2] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs[2] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs[3] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs[3] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n[0] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n[0] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n[1] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n[1] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n[2] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n[2] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n[3] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n[3] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to memory_mem_ck -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to memory_mem_ck_n -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[0] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[10] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[11] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[12] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[13] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[14] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[1] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[2] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[3] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[4] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[5] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[6] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[7] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[8] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[9] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ba[0] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ba[1] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ba[2] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_cas_n -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_cke -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_cs_n -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_odt -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ras_n -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_we_n -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_reset_n -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dm[0] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dm[1] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dm[2] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dm[3] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_a[0] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_a[10] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_a[11] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_a[12] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_a[13] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_a[14] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_a[1] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_a[2] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_a[3] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_a[4] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_a[5] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_a[6] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_a[7] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_a[8] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_a[9] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_ba[0] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_ba[1] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_ba[2] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_cas_n -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_ck -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_ck_n -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_cke -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_cs_n -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dm[0] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dm[1] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dm[2] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dm[3] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[0] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[10] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[11] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[12] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[13] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[14] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[15] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[16] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[17] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[18] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[19] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[1] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[20] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[21] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[22] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[23] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[24] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[25] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[26] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[27] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[28] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[29] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[2] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[30] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[31] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[3] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[4] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[5] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[6] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[7] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[8] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq[9] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dqs[0] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dqs[1] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dqs[2] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dqs[3] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dqs_n[0] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dqs_n[1] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dqs_n[2] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dqs_n[3] -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_odt -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_ras_n -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_reset_n -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_we_n -entity soc_system -tag __hps_sdram_p0
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity soc_system -section_id Top
-set_location_assignment PIN_Y26 -to clk_100m_fpga
-set_location_assignment PIN_K14 -to clk_50m_fpga
-set_location_assignment PIN_AA16 -to clk_top1
-set_location_assignment PIN_AF14 -to clk_bot1
-set_location_assignment PIN_AJ14 -to ddr3_fpga_a[0]
-set_location_assignment PIN_AK14 -to ddr3_fpga_a[1]
-set_location_assignment PIN_AH12 -to ddr3_fpga_a[2]
-set_location_assignment PIN_AJ12 -to ddr3_fpga_a[3]
-set_location_assignment PIN_AG15 -to ddr3_fpga_a[4]
-set_location_assignment PIN_AH15 -to ddr3_fpga_a[5]
-set_location_assignment PIN_AK12 -to ddr3_fpga_a[6]
-set_location_assignment PIN_AK13 -to ddr3_fpga_a[7]
-set_location_assignment PIN_AH13 -to ddr3_fpga_a[8]
-set_location_assignment PIN_AH14 -to ddr3_fpga_a[9]
-set_location_assignment PIN_AJ9 -to ddr3_fpga_a[10]
-set_location_assignment PIN_AK9 -to ddr3_fpga_a[11]
-set_location_assignment PIN_AK7 -to ddr3_fpga_a[12]
-set_location_assignment PIN_AK8 -to ddr3_fpga_a[13]
-set_location_assignment PIN_AG12 -to ddr3_fpga_a[14]
-set_location_assignment PIN_AH10 -to ddr3_fpga_ba[0]
-set_location_assignment PIN_AJ11 -to ddr3_fpga_ba[1]
-set_location_assignment PIN_AK11 -to ddr3_fpga_ba[2]
-set_location_assignment PIN_AH7 -to ddr3_fpga_casn
-set_location_assignment PIN_AJ21 -to ddr3_fpga_cke
-set_location_assignment PIN_AA15 -to ddr3_fpga_clk_n
-set_location_assignment PIN_AA14 -to ddr3_fpga_clk_p
-set_location_assignment PIN_AB15 -to ddr3_fpga_csn
-set_location_assignment PIN_AH17 -to ddr3_fpga_dm[0]
-set_location_assignment PIN_AG23 -to ddr3_fpga_dm[1]
-set_location_assignment PIN_AK23 -to ddr3_fpga_dm[2]
-set_location_assignment PIN_AJ27 -to ddr3_fpga_dm[3]
-set_location_assignment PIN_AF18 -to ddr3_fpga_dq[0]
-set_location_assignment PIN_AE17 -to ddr3_fpga_dq[1]
-set_location_assignment PIN_AG16 -to ddr3_fpga_dq[2]
-set_location_assignment PIN_AF16 -to ddr3_fpga_dq[3]
-set_location_assignment PIN_AH20 -to ddr3_fpga_dq[4]
-set_location_assignment PIN_AG21 -to ddr3_fpga_dq[5]
-set_location_assignment PIN_AJ16 -to ddr3_fpga_dq[6]
-set_location_assignment PIN_AH18 -to ddr3_fpga_dq[7]
-set_location_assignment PIN_AK18 -to ddr3_fpga_dq[8]
-set_location_assignment PIN_AJ17 -to ddr3_fpga_dq[9]
-set_location_assignment PIN_AG18 -to ddr3_fpga_dq[10]
-set_location_assignment PIN_AK19 -to ddr3_fpga_dq[11]
-set_location_assignment PIN_AG20 -to ddr3_fpga_dq[12]
-set_location_assignment PIN_AF19 -to ddr3_fpga_dq[13]
-set_location_assignment PIN_AJ20 -to ddr3_fpga_dq[14]
-set_location_assignment PIN_AH24 -to ddr3_fpga_dq[15]
-set_location_assignment PIN_AE19 -to ddr3_fpga_dq[16]
-set_location_assignment PIN_AE18 -to ddr3_fpga_dq[17]
-set_location_assignment PIN_AG22 -to ddr3_fpga_dq[18]
-set_location_assignment PIN_AK22 -to ddr3_fpga_dq[19]
-set_location_assignment PIN_AF21 -to ddr3_fpga_dq[20]
-set_location_assignment PIN_AF20 -to ddr3_fpga_dq[21]
-set_location_assignment PIN_AH23 -to ddr3_fpga_dq[22]
-set_location_assignment PIN_AK24 -to ddr3_fpga_dq[23]
-set_location_assignment PIN_AF24 -to ddr3_fpga_dq[24]
-set_location_assignment PIN_AF23 -to ddr3_fpga_dq[25]
-set_location_assignment PIN_AJ24 -to ddr3_fpga_dq[26]
-set_location_assignment PIN_AK26 -to ddr3_fpga_dq[27]
-set_location_assignment PIN_AE23 -to ddr3_fpga_dq[28]
-set_location_assignment PIN_AE22 -to ddr3_fpga_dq[29]
-set_location_assignment PIN_AG25 -to ddr3_fpga_dq[30]
-set_location_assignment PIN_AK27 -to ddr3_fpga_dq[31]
-set_location_assignment PIN_W16 -to ddr3_fpga_dqs_n[0]
-set_location_assignment PIN_W17 -to ddr3_fpga_dqs_n[1]
-set_location_assignment PIN_AA18 -to ddr3_fpga_dqs_n[2]
-set_location_assignment PIN_AD19 -to ddr3_fpga_dqs_n[3]
-set_location_assignment PIN_V16 -to ddr3_fpga_dqs_p[0]
-set_location_assignment PIN_V17 -to ddr3_fpga_dqs_p[1]
-set_location_assignment PIN_Y17 -to ddr3_fpga_dqs_p[2]
-set_location_assignment PIN_AC20 -to ddr3_fpga_dqs_p[3]
-set_location_assignment PIN_AE16 -to ddr3_fpga_odt
-set_location_assignment PIN_AH8 -to ddr3_fpga_rasn
-set_location_assignment PIN_AK21 -to ddr3_fpga_resetn
-set_location_assignment PIN_AJ6 -to ddr3_fpga_wen
-set_location_assignment PIN_AG17 -to ddr3_fpga_rzq
-
-set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 5B
-set_location_assignment PIN_Y21 -to vga_g[0]
-set_location_assignment PIN_AA25 -to vga_g[1]
-set_location_assignment PIN_AB26 -to vga_g[2]
-set_location_assignment PIN_AB22 -to vga_g[3]
-set_location_assignment PIN_AB23 -to vga_g[4]
-set_location_assignment PIN_AA24 -to vga_g[5]
-set_location_assignment PIN_AB25 -to vga_g[6]
-set_location_assignment PIN_AE27 -to vga_g[7]
-set_location_assignment PIN_W20 -to vga_clk
-set_location_assignment PIN_AH3 -to vga_balnk_n
-set_location_assignment PIN_AE28 -to vga_b[0]
-set_location_assignment PIN_Y23 -to vga_b[1]
-set_location_assignment PIN_Y24 -to vga_b[2]
-set_location_assignment PIN_AG28 -to vga_b[3]
-set_location_assignment PIN_AF28 -to vga_b[4]
-set_location_assignment PIN_V23 -to vga_b[5]
-set_location_assignment PIN_W24 -to vga_b[6]
-set_location_assignment PIN_AF29 -to vga_b[7]
-set_location_assignment PIN_AA12 -to vga_r[0]
-set_location_assignment PIN_AB12 -to vga_r[1]
-set_location_assignment PIN_AF6 -to vga_r[2]
-set_location_assignment PIN_AG6 -to vga_r[3]
-set_location_assignment PIN_AG5 -to vga_r[4]
-set_location_assignment PIN_AH5 -to vga_r[5]
-set_location_assignment PIN_AJ1 -to vga_r[6]
-set_location_assignment PIN_AJ2 -to vga_r[7]
-set_location_assignment PIN_AG2 -to vga_sync_n
-set_location_assignment PIN_AC12 -to vga_vs
-set_location_assignment PIN_AC27 -to aud_adcdat
-set_location_assignment PIN_AG30 -to aud_adclrck
-set_location_assignment PIN_AE7 -to aud_bclk
-set_location_assignment PIN_AG3 -to aud_dacdat
-set_location_assignment PIN_AH4 -to aud_daclrck
-set_location_assignment PIN_AH30 -to aud_i2c_sclk
-set_location_assignment PIN_AF30 -to aud_i2c_sdat
-set_location_assignment PIN_AD26 -to aud_mute
-set_location_assignment PIN_AC9 -to aud_xck
-set_location_assignment PIN_AG27 -to fan_ctrl
-set_location_assignment PIN_AH2 -to irda_rxd
-
-set_location_assignment PIN_AF8 -to temp_cs_n
-set_location_assignment PIN_AF9 -to temp_sclk
-set_location_assignment PIN_AG7 -to temp_mosi
-set_location_assignment PIN_AG1 -to temp_miso
-
-
-set_location_assignment PIN_J14 -to hsmc_clk_in0
-set_location_assignment PIN_AD29 -to hsmc_clk_out0
-
-set_location_assignment PIN_AE2 -to hsmc_gxb_rx_p[0]
-set_location_assignment PIN_AC2 -to hsmc_gxb_rx_p[1]
-set_location_assignment PIN_AA2 -to hsmc_gxb_rx_p[2]
-set_location_assignment PIN_W2 -to hsmc_gxb_rx_p[3]
-set_location_assignment PIN_U2 -to hsmc_gxb_rx_p[4]
-set_location_assignment PIN_R2 -to hsmc_gxb_rx_p[5]
-set_location_assignment PIN_N2 -to hsmc_gxb_rx_p[6]
-#set_location_assignment PIN_L2 -to hsmc_gxb_rx_p[7]
-set_location_assignment PIN_J2 -to hsmc_gxb_rx_p[7]
-
-set_location_assignment PIN_AD4 -to hsmc_gxb_tx_p[0]
-set_location_assignment PIN_AB4 -to hsmc_gxb_tx_p[1]
-set_location_assignment PIN_Y4 -to hsmc_gxb_tx_p[2]
-set_location_assignment PIN_V4 -to hsmc_gxb_tx_p[3]
-set_location_assignment PIN_T4 -to hsmc_gxb_tx_p[4]
-set_location_assignment PIN_P4 -to hsmc_gxb_tx_p[5]
-set_location_assignment PIN_M4 -to hsmc_gxb_tx_p[6]
-#set_location_assignment PIN_K4 -to hsmc_gxb_tx_p[7]
-set_location_assignment PIN_H4 -to hsmc_gxb_tx_p[7]
-
-#set_location_assignment PIN_W7 -to hsmc_ref_clk_n
-set_location_assignment PIN_P9 -to hsmc_ref_clk_p
-#set_location_assignment PIN_T8 -to hsmc_ref_clk_p
-
-set_location_assignment PIN_C10 -to hsmc_d[0]
-set_location_assignment PIN_C9 -to hsmc_d[2]
-set_location_assignment PIN_H13 -to hsmc_d[1]
-set_location_assignment PIN_H12 -to hsmc_d[3]
-
-set_location_assignment PIN_AA28 -to hsmc_scl
-set_location_assignment PIN_AE29 -to hsmc_sda
-
-set_location_assignment PIN_W25 -to user_dipsw_fpga[0]
-set_location_assignment PIN_V25 -to user_dipsw_fpga[1]
-set_location_assignment PIN_AC28 -to user_dipsw_fpga[2]
-set_location_assignment PIN_AC29 -to user_dipsw_fpga[3]
-set_location_assignment PIN_AF10 -to user_led_fpga[0]
-set_location_assignment PIN_AD10 -to user_led_fpga[1]
-set_location_assignment PIN_AE11 -to user_led_fpga[2]
-set_location_assignment PIN_AD7 -to user_led_fpga[3]
-set_location_assignment PIN_AE9 -to user_pb_fpga[0]
-set_location_assignment PIN_AE12 -to user_pb_fpga[1]
-set_location_assignment PIN_AD9 -to user_pb_fpga[2]
-set_location_assignment PIN_AD11 -to user_pb_fpga[3]
-
-
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
-set_global_assignment -name AUTO_OPEN_DRAIN_PINS OFF
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_usb1_D0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_usb1_D1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_usb1_D2
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_usb1_D3
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_usb1_D4
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_usb1_D5
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_usb1_D6
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_usb1_D7
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_usb1_DIR
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_usb1_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_usb1_STP
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_usb1_NXT
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_uart0_TX
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_uart0_RX
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_qspi_IO0
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_qspi_IO1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_qspi_IO2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_qspi_IO3
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_qspi_SS0
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_qspi_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_sdio_CLK_IN
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_sdio_CMD
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_sdio_D0
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_sdio_D1
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_sdio_D2
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_sdio_D3
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_sdio_D4
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_sdio_D5
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_sdio_D6
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_sdio_D7
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_sdio_PWREN
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hps_sdio_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_spim0_MISO
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_spim0_MOSI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_spim0_SS0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_spim1_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_spim1_MISO
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_spim1_MOSI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_spim1_SS0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_spim0_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_emac1_MDIO
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_emac1_RXD0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_emac1_RXD1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_emac1_RXD2
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_emac1_RXD3
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_emac1_RX_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_emac1_RX_CTL
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_emac1_TXD0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_emac1_TXD1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_emac1_TXD2
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_emac1_TXD3
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_emac1_TX_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_emac1_TX_CTL
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_emac1_MDC
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_gpio_GPIO09
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_gpio_GPIO35
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_gpio_GPIO48
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_gpio_GPIO53
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_gpio_GPIO54
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_gpio_GPIO55
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_gpio_GPIO56
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_gpio_GPIO61
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_gpio_GPIO62
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_gpio_GPIO00
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_i2c1_SDA
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_i2c1_SCL
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_oct_rzqin -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[0] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[1] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[2] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[3] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[4] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[5] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[6] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[7] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[8] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[9] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[10] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[11] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[12] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[13] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[14] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[15] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[16] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[17] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[18] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[19] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[20] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[21] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[22] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[23] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[24] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[25] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[26] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[27] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[28] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[29] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[30] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[31] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_dqs[0] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_dqs[1] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_dqs[2] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_dqs[3] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_dqs_n[0] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_dqs_n[1] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_dqs_n[2] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_dqs_n[3] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_ck -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_ck_n -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[0] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[10] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[11] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[12] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[13] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[14] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[1] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[2] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[3] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[4] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[5] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[6] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[7] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[8] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[9] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_ba[0] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_ba[1] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_ba[2] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_cas_n -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_cke -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_cs_n -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_odt -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_ras_n -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_we_n -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_reset_n -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dm[0] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dm[1] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dm[2] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dm[3] -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_mem_stable_n -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_n -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __hps_sdram_p0
-set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to hps_0|hps_io|border|hps_sdram_inst -tag __hps_sdram_p0
-set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to hps_0|hps_io|border|hps_sdram_inst|pll0|fbout -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1] -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2] -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2] -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3] -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[0] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[1] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[2] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[3] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[4] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[5] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[6] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[7] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[8] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[9] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[10] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[11] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[12] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[13] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[14] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_ba -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ba[0] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ba[1] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ba[2] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_cas_n -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ck -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ck_n -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_cke -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_cs_n -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dm -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dm[0] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dm[1] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dm[2] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dm[3] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dq -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[0] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[1] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[2] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[3] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[4] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[5] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[6] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[7] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[8] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[9] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[10] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[11] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[12] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[13] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[14] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[15] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[16] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[17] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[18] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[19] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[20] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[21] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[22] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[23] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[24] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[25] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[26] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[27] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[28] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[29] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[30] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[31] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dqs -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dqs[0] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dqs[1] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dqs[2] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dqs[3] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_mem_dqs_n -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dqs_n[0] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dqs_n[1] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dqs_n[2] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dqs_n[3] -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_odt -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ras_n -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_reset_n -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_we_n -tag __hps_sdram_p0
-set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to memory_oct_rzqin -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[0] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[0] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[1] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[1] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[2] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[2] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[3] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[3] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[4] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[4] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[5] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[5] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[6] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[6] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[7] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[7] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[8] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[8] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[9] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[9] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[10] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[10] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[11] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[11] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[12] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[12] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[13] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[13] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[14] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[14] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[15] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[15] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[16] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[16] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[17] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[17] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[18] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[18] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[19] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[19] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[20] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[20] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[21] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[21] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[22] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[22] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[23] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[23] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[24] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[24] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[25] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[25] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[26] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[26] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[27] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[27] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[28] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[28] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[29] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[29] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[30] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[30] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[31] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[31] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs[0] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs[0] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs[1] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs[1] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs[2] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs[2] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs[3] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs[3] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n[0] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n[0] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n[1] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n[1] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n[2] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n[2] -tag __hps_sdram_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n[3] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n[3] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to memory_mem_ck -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to memory_mem_ck_n -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[0] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[10] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[11] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[12] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[13] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[14] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[1] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[2] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[3] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[4] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[5] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[6] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[7] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[8] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[9] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ba[0] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ba[1] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ba[2] -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_cas_n -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_cke -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_cs_n -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_odt -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ras_n -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_we_n -tag __hps_sdram_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_reset_n -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dm[0] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dm[1] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dm[2] -tag __hps_sdram_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dm[3] -tag __hps_sdram_p0
-set_instance_assignment -name IO_STANDARD "1.5 V" -to clk_top1
-set_instance_assignment -name IO_STANDARD "1.5 V" -to clk_bot1
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_a
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_ba
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_casn
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_cke
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_clk_n
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_clk_p
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_csn
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_dm
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_dq
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_dqs_n
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_dqs_p
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_odt
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_rasn
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_resetn
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_wen
-set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_fpga_rzq
-set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_100m_fpga
-set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_50m_fpga
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_balnk_n
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_clk
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_hs
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_sync_n
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_vs
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_adcdat
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_adclrck
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_bclk
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_dacdat
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_daclrck
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_i2c_sclk
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_i2c_sdat
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_mute
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_xck
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fan_ctrl
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to irda_rxd
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to temp_cs_n
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to temp_sclk
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to temp_mosi
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to temp_miso
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkin_p[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkin_p[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkout_p[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkout_p[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clk_in0
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clk_out0
-set_instance_assignment -name IO_STANDARD HCSL -to hsmc_ref_clk_p
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[9]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[13]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[14]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[15]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[16]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_scl
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_sda
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[9]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[13]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[14]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[15]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[16]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[0]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[1]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[2]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[3]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[4]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[5]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[6]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[7]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[0]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[1]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[2]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[3]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[4]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[5]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[6]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to user_dipsw_fpga[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to user_dipsw_fpga[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to user_dipsw_fpga[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to user_dipsw_fpga[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_led_fpga[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_led_fpga[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_led_fpga[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_led_fpga[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_pb_fpga[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_pb_fpga[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_pb_fpga[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_pb_fpga[3]
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_mem_stable_n -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_n -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1] -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2] -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2] -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3] -tag __hps_sdram_p0
-set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3] -tag __hps_sdram_p0
-set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to u0|hps_0|hps_io|border|hps_sdram_inst -tag __hps_sdram_p0
-set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to u0|hps_0|hps_io|border|hps_sdram_inst|pll0|fbout -tag __hps_sdram_p0
-set_instance_assignment -name D5_DELAY 2 -to memory_mem_ck -tag __hps_sdram_p0
-set_instance_assignment -name D5_DELAY 2 -to memory_mem_ck_n -tag __hps_sdram_p0
-set_location_assignment PIN_AD27 -to fpga_resetn
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fpga_resetn
-set_location_assignment PIN_AE26 -to clk_i2c_sclk
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_i2c_sdat
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_i2c_sclk
-set_location_assignment PIN_AJ29 -to clk_i2c_sdat
-set_global_assignment -name IP_SEARCH_PATHS "../../cv-ip/**/*;./ip;../../cv-ip/ADC_LTC2308_FIFO;../../cv-ip/hm2reg_io;../../ip"
-set_global_assignment -name ENABLE_OCT_DONE OFF
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
-set_global_assignment -name VERILOG_FILE ../../cv-ip/debounce/debounce.v
-set_global_assignment -name VERILOG_FILE ../../cv-ip/edge_detect/altera_edge_detector.v
-set_global_assignment -name QIP_FILE ../../cv-ip/altsource_probe/hps_reset.qip
-set_global_assignment -name QIP_FILE soc_system/synthesis/soc_system.qip
-set_global_assignment -name VERILOG_FILE top/config_soc.v
-set_global_assignment -name SDC_FILE soc_system_timing.sdc
-set_global_assignment -name VERILOG_FILE top/ghrd_top.v
-set_global_assignment -name CDF_FILE output_files/Chain1.cdf
-set_global_assignment -name QIP_FILE ../../hm2/hm2_socfpga.qip
-set_global_assignment -name PARTITION_NETLIST_TYPE POST_SYNTH -section_id "soc_system:u0"
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id "soc_system:u0"
-set_global_assignment -name PARTITION_COLOR 39423 -section_id "soc_system:u0"
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkin_n[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[9]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[13]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[14]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[15]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[16]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[17]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[18]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[19]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[20]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[21]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[22]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[23]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[24]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[25]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[26]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[27]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[28]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[29]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[30]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[31]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[32]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[33]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[34]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[35]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[9]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[13]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[14]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[15]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[16]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[17]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[18]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[19]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[20]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[21]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[22]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[23]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[24]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[25]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[26]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[27]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[28]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[29]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[30]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[31]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[32]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[33]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[34]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[35]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n8
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p8
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n8
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p8
-set_instance_assignment -name IO_STANDARD HCSL -to hsmc_ref_clk_n
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[0]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[1]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[2]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[3]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[4]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[5]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[6]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[7]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[0]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[1]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[2]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[3]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[4]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[5]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[6]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[7]
-set_location_assignment PIN_G15 -to GPIO0[0]
-set_location_assignment PIN_F14 -to GPIO0[1]
-set_location_assignment PIN_H15 -to GPIO0[2]
-set_location_assignment PIN_F15 -to GPIO0[3]
-set_location_assignment PIN_A13 -to GPIO0[4]
-set_location_assignment PIN_G13 -to GPIO0[5]
-set_location_assignment PIN_B13 -to GPIO0[6]
-set_location_assignment PIN_H14 -to GPIO0[7]
-set_location_assignment PIN_B11 -to GPIO0[8]
-set_location_assignment PIN_E13 -to GPIO0[9]
-set_location_assignment PIN_C12 -to GPIO0[10]
-set_location_assignment PIN_F13 -to GPIO0[11]
-set_location_assignment PIN_B8 -to GPIO0[12]
-set_location_assignment PIN_B12 -to GPIO0[13]
-set_location_assignment PIN_C8 -to GPIO0[14]
-set_location_assignment PIN_C13 -to GPIO0[15]
-set_location_assignment PIN_A10 -to GPIO0[16]
-set_location_assignment PIN_D10 -to GPIO0[17]
-set_location_assignment PIN_A11 -to GPIO0[18]
-set_location_assignment PIN_D11 -to GPIO0[19]
-set_location_assignment PIN_B7 -to GPIO0[20]
-set_location_assignment PIN_D12 -to GPIO0[21]
-set_location_assignment PIN_C7 -to GPIO0[22]
-set_location_assignment PIN_E12 -to GPIO0[23]
-set_location_assignment PIN_A5 -to GPIO0[24]
-set_location_assignment PIN_D9 -to GPIO0[25]
-set_location_assignment PIN_A6 -to GPIO0[26]
-set_location_assignment PIN_E9 -to GPIO0[27]
-set_location_assignment PIN_A3 -to GPIO0[28]
-set_location_assignment PIN_B5 -to GPIO0[29]
-set_location_assignment PIN_A4 -to GPIO0[30]
-set_location_assignment PIN_B6 -to GPIO0[31]
-set_location_assignment PIN_B2 -to GPIO0[32]
-set_location_assignment PIN_C2 -to GPIO0[33]
-set_location_assignment PIN_B1 -to GPIO0[34]
-set_location_assignment PIN_D2 -to GPIO0[35]
-set_location_assignment PIN_AB27 -to GPIO1[0]
-set_location_assignment PIN_F8 -to GPIO1[1]
-set_location_assignment PIN_AA26 -to GPIO1[2]
-set_location_assignment PIN_F9 -to GPIO1[3]
-set_location_assignment PIN_B3 -to GPIO1[4]
-set_location_assignment PIN_G8 -to GPIO1[5]
-set_location_assignment PIN_C3 -to GPIO1[6]
-set_location_assignment PIN_H8 -to GPIO1[7]
-set_location_assignment PIN_D4 -to GPIO1[8]
-set_location_assignment PIN_H7 -to GPIO1[9]
-set_location_assignment PIN_E4 -to GPIO1[10]
-set_location_assignment PIN_J7 -to GPIO1[11]
-set_location_assignment PIN_E2 -to GPIO1[12]
-set_location_assignment PIN_K8 -to GPIO1[13]
-set_location_assignment PIN_E3 -to GPIO1[14]
-set_location_assignment PIN_K7 -to GPIO1[15]
-set_location_assignment PIN_E6 -to GPIO1[16]
-set_location_assignment PIN_J9 -to GPIO1[17]
-set_location_assignment PIN_E7 -to GPIO1[18]
-set_location_assignment PIN_J10 -to GPIO1[19]
-set_location_assignment PIN_C4 -to GPIO1[20]
-set_location_assignment PIN_F10 -to GPIO1[21]
-set_location_assignment PIN_D5 -to GPIO1[22]
-set_location_assignment PIN_G10 -to GPIO1[23]
-set_location_assignment PIN_C5 -to GPIO1[24]
-set_location_assignment PIN_J12 -to GPIO1[25]
-set_location_assignment PIN_D6 -to GPIO1[26]
-set_location_assignment PIN_K12 -to GPIO1[27]
-set_location_assignment PIN_F6 -to GPIO1[28]
-set_location_assignment PIN_G11 -to GPIO1[29]
-set_location_assignment PIN_G7 -to GPIO1[30]
-set_location_assignment PIN_G12 -to GPIO1[31]
-set_location_assignment PIN_D7 -to GPIO1[32]
-set_location_assignment PIN_A8 -to GPIO1[33]
-set_location_assignment PIN_E8 -to GPIO1[34]
-set_location_assignment PIN_A9 -to GPIO1[35]
-set_location_assignment PIN_D1 -to hsmc_tx_n8
-set_location_assignment PIN_E1 -to hsmc_tx_p8
-set_location_assignment PIN_E11 -to hsmc_rx_n8
-set_location_assignment PIN_F11 -to hsmc_rx_p8
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-set_instance_assignment -name PARTITION_HIERARCHY u0_ef7d1 -to "soc_system:u0" -section_id "soc_system:u0"
\ No newline at end of file
diff --git a/HW/QuartusProjects/SoCkit_GHRD/soc_system.qsys b/HW/QuartusProjects/SoCkit_GHRD/soc_system.qsys
deleted file mode 100644
index dc0cd84f..00000000
--- a/HW/QuartusProjects/SoCkit_GHRD/soc_system.qsys
+++ /dev/null
@@ -1,1532 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<system name="$${FILENAME}">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags=""
-   categories="System" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element button_pio
-   {
-      datum _sortIndex
-      {
-         value = "12";
-         type = "int";
-      }
-   }
-   element button_pio.s1
-   {
-      datum _lockedAddress
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element clk_0
-   {
-      datum _sortIndex
-      {
-         value = "10";
-         type = "int";
-      }
-   }
-   element dipsw_pio
-   {
-      datum _sortIndex
-      {
-         value = "7";
-         type = "int";
-      }
-   }
-   element dipsw_pio.external_connection
-   {
-      datum _tags
-      {
-         value = "";
-         type = "String";
-      }
-   }
-   element dipsw_pio.s1
-   {
-      datum _lockedAddress
-      {
-         value = "1";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "65664";
-         type = "String";
-      }
-   }
-   element f2sdram_only_master
-   {
-      datum _sortIndex
-      {
-         value = "4";
-         type = "int";
-      }
-   }
-   element fpga_only_master
-   {
-      datum _sortIndex
-      {
-         value = "3";
-         type = "int";
-      }
-   }
-   element hm2reg_io_0
-   {
-      datum _sortIndex
-      {
-         value = "13";
-         type = "int";
-      }
-   }
-   element hm2reg_io_0.slave
-   {
-      datum baseAddress
-      {
-         value = "262144";
-         type = "String";
-      }
-   }
-   element hps_0
-   {
-      datum _sortIndex
-      {
-         value = "1";
-         type = "int";
-      }
-   }
-   element hps_0.f2h_axi_slave
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element hps_only_master
-   {
-      datum _sortIndex
-      {
-         value = "2";
-         type = "int";
-      }
-   }
-   element intr_capturer_0
-   {
-      datum _sortIndex
-      {
-         value = "9";
-         type = "int";
-      }
-   }
-   element intr_capturer_0.avalon_slave_0
-   {
-      datum _lockedAddress
-      {
-         value = "1";
-         type = "boolean";
-      }
-      datum _tags
-      {
-         value = "";
-         type = "String";
-      }
-      datum baseAddress
-      {
-         value = "196608";
-         type = "String";
-      }
-   }
-   element intr_capturer_0.interrupt_receiver
-   {
-      datum _tags
-      {
-         value = "";
-         type = "String";
-      }
-   }
-   element jtag_uart
-   {
-      datum _sortIndex
-      {
-         value = "6";
-         type = "int";
-      }
-   }
-   element jtag_uart.avalon_jtag_slave
-   {
-      datum _lockedAddress
-      {
-         value = "1";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "131072";
-         type = "String";
-      }
-   }
-   element led_pio
-   {
-      datum _sortIndex
-      {
-         value = "11";
-         type = "int";
-      }
-   }
-   element led_pio.s1
-   {
-      datum _lockedAddress
-      {
-         value = "1";
-         type = "boolean";
-      }
-   }
-   element mm_bridge_0
-   {
-      datum _sortIndex
-      {
-         value = "5";
-         type = "int";
-      }
-   }
-   element onchip_memory2_0
-   {
-      datum _sortIndex
-      {
-         value = "8";
-         type = "int";
-      }
-   }
-   element onchip_memory2_0.s1
-   {
-      datum baseAddress
-      {
-         value = "0";
-         type = "String";
-      }
-   }
-   element soc_system
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
-   element sysid_qsys
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-   element sysid_qsys.control_slave
-   {
-      datum _lockedAddress
-      {
-         value = "1";
-         type = "boolean";
-      }
-      datum baseAddress
-      {
-         value = "65536";
-         type = "String";
-      }
-   }
-}
-]]></parameter>
- <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="5CSXFC6D6F31C8ES" />
- <parameter name="deviceFamily" value="Cyclone V" />
- <parameter name="deviceSpeedGrade" value="8_H6" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="maxAdditionalLatency" value="1" />
- <parameter name="projectName" value="soc_system.qpf" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="button_pio_external_connection"
-   internal="button_pio.external_connection"
-   type="conduit"
-   dir="end" />
- <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
- <interface
-   name="clk_100mhz_out"
-   internal="hps_0.h2f_user0_clock"
-   type="clock"
-   dir="start" />
- <interface
-   name="clk_200mhz_out"
-   internal="hps_0.h2f_user2_clock"
-   type="clock"
-   dir="start" />
- <interface
-   name="dipsw_pio_external_connection"
-   internal="dipsw_pio.external_connection"
-   type="conduit"
-   dir="end" />
- <interface
-   name="hps_0_f2h_cold_reset_req"
-   internal="hps_0.f2h_cold_reset_req"
-   type="reset"
-   dir="end" />
- <interface
-   name="hps_0_f2h_debug_reset_req"
-   internal="hps_0.f2h_debug_reset_req"
-   type="reset"
-   dir="end" />
- <interface
-   name="hps_0_f2h_stm_hw_events"
-   internal="hps_0.f2h_stm_hw_events"
-   type="conduit"
-   dir="end" />
- <interface
-   name="hps_0_f2h_warm_reset_req"
-   internal="hps_0.f2h_warm_reset_req"
-   type="reset"
-   dir="end" />
- <interface
-   name="hps_0_h2f_reset"
-   internal="hps_0.h2f_reset"
-   type="reset"
-   dir="start" />
- <interface name="hps_0_hps_io" internal="hps_0.hps_io" type="conduit" dir="end" />
- <interface
-   name="led_pio_external_connection"
-   internal="led_pio.external_connection"
-   type="conduit"
-   dir="end" />
- <interface name="memory" internal="hps_0.memory" type="conduit" dir="end" />
- <interface name="mk_io" internal="hm2reg_io_0.pins" type="conduit" dir="end" />
- <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
- <module name="button_pio" kind="altera_avalon_pio" version="15.1" enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="true" />
-  <parameter name="clockRate" value="50000000" />
-  <parameter name="direction" value="Input" />
-  <parameter name="edgeType" value="FALLING" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="EDGE" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="4" />
- </module>
- <module name="clk_0" kind="clock_source" version="15.1" enabled="1">
-  <parameter name="clockFrequency" value="50000000" />
-  <parameter name="clockFrequencyKnown" value="true" />
-  <parameter name="inputClockFrequency" value="0" />
-  <parameter name="resetSynchronousEdges" value="NONE" />
- </module>
- <module name="dipsw_pio" kind="altera_avalon_pio" version="15.1" enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="true" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="true" />
-  <parameter name="clockRate" value="50000000" />
-  <parameter name="direction" value="Input" />
-  <parameter name="edgeType" value="ANY" />
-  <parameter name="generateIRQ" value="true" />
-  <parameter name="irqType" value="EDGE" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="4" />
- </module>
- <module
-   name="f2sdram_only_master"
-   kind="altera_jtag_avalon_master"
-   version="15.1"
-   enabled="1">
-  <parameter name="AUTO_DEVICE" value="5CSXFC6D6F31C8ES" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
-  <parameter name="COMPONENT_CLOCK" value="0" />
-  <parameter name="FAST_VER" value="0" />
-  <parameter name="FIFO_DEPTHS" value="2" />
-  <parameter name="PLI_PORT" value="50000" />
-  <parameter name="USE_PLI" value="0" />
- </module>
- <module
-   name="fpga_only_master"
-   kind="altera_jtag_avalon_master"
-   version="15.1"
-   enabled="1">
-  <parameter name="AUTO_DEVICE" value="5CSXFC6D6F31C8ES" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
-  <parameter name="COMPONENT_CLOCK" value="0" />
-  <parameter name="FAST_VER" value="0" />
-  <parameter name="FIFO_DEPTHS" value="2" />
-  <parameter name="PLI_PORT" value="50000" />
-  <parameter name="USE_PLI" value="0" />
- </module>
- <module name="hm2reg_io_0" kind="hm2reg_io" version="1.0" enabled="1">
-  <parameter name="ADDRESS_WIDTH" value="14" />
-  <parameter name="DATA_WIDTH" value="32" />
- </module>
- <module name="hps_0" kind="altera_hps" version="15.1" enabled="1">
-  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
-  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
-  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
-  <parameter name="AC_PACKAGE_DESKEW" value="false" />
-  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
-  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
-  <parameter name="ADDR_ORDER" value="0" />
-  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
-  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
-  <parameter name="ADVANCED_CK_PHASES" value="false" />
-  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
-  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
-  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
-  <parameter name="AP_MODE" value="false" />
-  <parameter name="AP_MODE_EN" value="0" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
-  <parameter name="AUTO_PD_CYCLES" value="0" />
-  <parameter name="AUTO_POWERDN_EN" value="false" />
-  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
-  <parameter name="AVL_MAX_SIZE" value="4" />
-  <parameter name="BONDING_OUT_ENABLED" value="false" />
-  <parameter name="BOOTFROMFPGA_Enable" value="false" />
-  <parameter name="BSEL" value="1" />
-  <parameter name="BSEL_EN" value="false" />
-  <parameter name="BYTE_ENABLE" value="true" />
-  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
-  <parameter name="CALIBRATION_MODE" value="Skip" />
-  <parameter name="CALIB_REG_WIDTH" value="8" />
-  <parameter name="CAN0_Mode" value="N/A" />
-  <parameter name="CAN0_PinMuxing" value="Unused" />
-  <parameter name="CAN1_Mode" value="N/A" />
-  <parameter name="CAN1_PinMuxing" value="Unused" />
-  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
-  <parameter name="CFG_REORDER_DATA" value="true" />
-  <parameter name="CFG_TCCD_NS" value="2.5" />
-  <parameter name="COMMAND_PHASE" value="0.0" />
-  <parameter name="CONTROLLER_LATENCY" value="5" />
-  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
-  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
-  <parameter name="CSEL" value="0" />
-  <parameter name="CSEL_EN" value="false" />
-  <parameter name="CTI_Enable" value="false" />
-  <parameter name="CTL_AUTOPCH_EN" value="false" />
-  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
-  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
-  <parameter name="CTL_CSR_ENABLED" value="false" />
-  <parameter name="CTL_CSR_READ_ONLY" value="1" />
-  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
-  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
-  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
-  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
-  <parameter name="CTL_ECC_ENABLED" value="false" />
-  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="true" />
-  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="true" />
-  <parameter name="CTL_HRB_ENABLED" value="false" />
-  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
-  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
-  <parameter name="CTL_USR_REFRESH_EN" value="false" />
-  <parameter name="CTL_ZQCAL_EN" value="false" />
-  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
-  <parameter name="DAT_DATA_WIDTH" value="32" />
-  <parameter name="DEBUGAPB_Enable" value="false" />
-  <parameter name="DEBUG_MODE" value="false" />
-  <parameter name="DEVICE_DEPTH" value="1" />
-  <parameter name="DEVICE_FAMILY_PARAM" value="" />
-  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
-  <parameter name="DISCRETE_FLY_BY" value="true" />
-  <parameter name="DLL_SHARING_MODE" value="None" />
-  <parameter name="DMA_Enable">No,No,No,No,No,No,No,No</parameter>
-  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
-  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
-  <parameter name="DUPLICATE_AC" value="false" />
-  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
-  <parameter name="EMAC0_Mode" value="N/A" />
-  <parameter name="EMAC0_PinMuxing" value="Unused" />
-  <parameter name="EMAC1_Mode" value="RGMII" />
-  <parameter name="EMAC1_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
-  <parameter name="ENABLE_BONDING" value="false" />
-  <parameter name="ENABLE_BURST_MERGE" value="false" />
-  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
-  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
-  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
-  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
-  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
-  <parameter name="ENABLE_ISS_PROBES" value="false" />
-  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
-  <parameter name="ENABLE_NON_DES_CAL" value="false" />
-  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
-  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
-  <parameter name="ENABLE_USER_ECC" value="false" />
-  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
-  <parameter name="EXTRA_SETTINGS" value="" />
-  <parameter name="F2H_AXI_CLOCK_FREQ" value="50000000" />
-  <parameter name="F2H_SDRAM0_CLOCK_FREQ" value="50000000" />
-  <parameter name="F2H_SDRAM1_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM2_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" />
-  <parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" />
-  <parameter name="F2SCLK_COLDRST_Enable" value="true" />
-  <parameter name="F2SCLK_DBGRST_Enable" value="true" />
-  <parameter name="F2SCLK_PERIPHCLK_Enable" value="false" />
-  <parameter name="F2SCLK_PERIPHCLK_FREQ" value="0" />
-  <parameter name="F2SCLK_SDRAMCLK_Enable" value="false" />
-  <parameter name="F2SCLK_SDRAMCLK_FREQ" value="0" />
-  <parameter name="F2SCLK_WARMRST_Enable" value="true" />
-  <parameter name="F2SDRAM_Type">Avalon-MM Bidirectional</parameter>
-  <parameter name="F2SDRAM_Width" value="256" />
-  <parameter name="F2SINTERRUPT_Enable" value="true" />
-  <parameter name="F2S_Width" value="2" />
-  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
-  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
-  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
-  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
-  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
-  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
-  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN" value="100" />
-  <parameter
-     name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK"
-     value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SDIO_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK" value="100.0" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK" value="100.0" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT" value="100" />
-  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT" value="100" />
-  <parameter name="GPIO_Enable">Yes,No,No,No,No,No,No,No,No,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,Yes,Yes,Yes,Yes,No,No,No,No,Yes,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
-  <parameter name="GP_Enable" value="false" />
-  <parameter name="H2F_AXI_CLOCK_FREQ" value="50000000" />
-  <parameter name="H2F_CTI_CLOCK_FREQ" value="100" />
-  <parameter name="H2F_DEBUG_APB_CLOCK_FREQ" value="100" />
-  <parameter name="H2F_LW_AXI_CLOCK_FREQ" value="50000000" />
-  <parameter name="H2F_TPIU_CLOCK_IN_FREQ" value="100" />
-  <parameter name="HARD_EMIF" value="true" />
-  <parameter name="HCX_COMPAT_MODE" value="false" />
-  <parameter name="HHP_HPS" value="true" />
-  <parameter name="HHP_HPS_SIMULATION" value="false" />
-  <parameter name="HHP_HPS_VERIFICATION" value="false" />
-  <parameter name="HLGPI_Enable" value="false" />
-  <parameter name="HPS_PROTOCOL" value="DDR3" />
-  <parameter name="I2C0_Mode" value="N/A" />
-  <parameter name="I2C0_PinMuxing" value="Unused" />
-  <parameter name="I2C1_Mode" value="I2C" />
-  <parameter name="I2C1_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="I2C2_Mode" value="N/A" />
-  <parameter name="I2C2_PinMuxing" value="Unused" />
-  <parameter name="I2C3_Mode" value="N/A" />
-  <parameter name="I2C3_PinMuxing" value="Unused" />
-  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
-  <parameter name="IS_ES_DEVICE" value="false" />
-  <parameter name="LOANIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
-  <parameter name="LOCAL_ID_WIDTH" value="8" />
-  <parameter name="LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
-  <parameter name="LWH2F_Enable" value="true" />
-  <parameter name="MARGIN_VARIATION_TEST" value="false" />
-  <parameter name="MAX_PENDING_RD_CMD" value="16" />
-  <parameter name="MAX_PENDING_WR_CMD" value="8" />
-  <parameter name="MEM_ASR" value="Manual" />
-  <parameter name="MEM_ATCL" value="Disabled" />
-  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
-  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
-  <parameter name="MEM_BL" value="OTF" />
-  <parameter name="MEM_BT" value="Sequential" />
-  <parameter name="MEM_CK_PHASE" value="0.0" />
-  <parameter name="MEM_CK_WIDTH" value="1" />
-  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
-  <parameter name="MEM_CLK_FREQ" value="400.0" />
-  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
-  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
-  <parameter name="MEM_CS_WIDTH" value="1" />
-  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
-  <parameter name="MEM_DLL_EN" value="true" />
-  <parameter name="MEM_DQ_PER_DQS" value="8" />
-  <parameter name="MEM_DQ_WIDTH" value="32" />
-  <parameter name="MEM_DRV_STR" value="RZQ/6" />
-  <parameter name="MEM_FORMAT" value="DISCRETE" />
-  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
-  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
-  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
-  <parameter name="MEM_IF_DQSN_EN" value="true" />
-  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
-  <parameter name="MEM_INIT_EN" value="false" />
-  <parameter name="MEM_INIT_FILE" value="" />
-  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
-  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
-  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
-  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
-  <parameter name="MEM_PD" value="DLL off" />
-  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
-  <parameter name="MEM_ROW_ADDR_WIDTH" value="15" />
-  <parameter name="MEM_RTT_NOM" value="RZQ/6" />
-  <parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
-  <parameter name="MEM_SRT" value="Normal" />
-  <parameter name="MEM_TCL" value="7" />
-  <parameter name="MEM_TFAW_NS" value="30.0" />
-  <parameter name="MEM_TINIT_US" value="500" />
-  <parameter name="MEM_TMRD_CK" value="4" />
-  <parameter name="MEM_TRAS_NS" value="35.0" />
-  <parameter name="MEM_TRCD_NS" value="13.75" />
-  <parameter name="MEM_TREFI_US" value="7.8" />
-  <parameter name="MEM_TRFC_NS" value="260.0" />
-  <parameter name="MEM_TRP_NS" value="13.75" />
-  <parameter name="MEM_TRRD_NS" value="10.0" />
-  <parameter name="MEM_TRTP_NS" value="10.0" />
-  <parameter name="MEM_TWR_NS" value="15.0" />
-  <parameter name="MEM_TWTR" value="4" />
-  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
-  <parameter name="MEM_VENDOR" value="JEDEC" />
-  <parameter name="MEM_VERBOSE" value="true" />
-  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
-  <parameter name="MEM_WTCL" value="6" />
-  <parameter name="MPU_EVENTS_Enable" value="false" />
-  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
-  <parameter name="MULTICAST_EN" value="false" />
-  <parameter name="NAND_Mode" value="N/A" />
-  <parameter name="NAND_PinMuxing" value="Unused" />
-  <parameter name="NEXTGEN" value="true" />
-  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
-  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
-  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
-  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
-  <parameter name="NUM_OF_PORTS" value="1" />
-  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
-  <parameter name="OCT_SHARING_MODE" value="None" />
-  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
-  <parameter name="PACKAGE_DESKEW" value="false" />
-  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
-  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
-  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
-  <parameter name="PHY_CSR_ENABLED" value="false" />
-  <parameter name="PHY_ONLY" value="false" />
-  <parameter name="PINGPONGPHY_EN" value="false" />
-  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
-  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_LOCATION" value="Top_Bottom" />
-  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_SHARING_MODE" value="None" />
-  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
-  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
-  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
-  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
-  <parameter name="POWER_OF_TWO_BUS" value="false" />
-  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
-  <parameter name="QSPI_Mode" value="1 SS" />
-  <parameter name="QSPI_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="RATE" value="Full" />
-  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
-  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
-  <parameter name="READ_FIFO_SIZE" value="8" />
-  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
-  <parameter name="REFRESH_INTERVAL" value="15000" />
-  <parameter name="REF_CLK_FREQ" value="25.0" />
-  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
-  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
-  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
-  <parameter name="S2FCLK_COLDRST_Enable" value="false" />
-  <parameter name="S2FCLK_PENDINGRST_Enable" value="false" />
-  <parameter name="S2FCLK_USER0CLK_Enable" value="true" />
-  <parameter name="S2FCLK_USER1CLK_Enable" value="true" />
-  <parameter name="S2FCLK_USER1CLK_FREQ" value="40.0" />
-  <parameter name="S2FCLK_USER2CLK" value="3" />
-  <parameter name="S2FCLK_USER2CLK_Enable" value="true" />
-  <parameter name="S2FCLK_USER2CLK_FREQ" value="100.0" />
-  <parameter name="S2FINTERRUPT_CAN_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_CLOCKPERIPHERAL_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_CTI_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_DMA_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_EMAC_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_FPGAMANAGER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_GPIO_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_I2CEMAC_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_I2CPERIPHERAL_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_L4TIMER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_NAND_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_OSCTIMER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_QSPI_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SDMMC_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SPIMASTER_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_SPISLAVE_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_UART_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_USB_Enable" value="false" />
-  <parameter name="S2FINTERRUPT_WATCHDOG_Enable" value="false" />
-  <parameter name="S2F_Width" value="2" />
-  <parameter name="SDIO_Mode" value="4-bit Data" />
-  <parameter name="SDIO_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="SEQUENCER_TYPE" value="NIOS" />
-  <parameter name="SEQ_MODE" value="0" />
-  <parameter name="SKIP_MEM_INIT" value="true" />
-  <parameter name="SOPC_COMPAT_RESET" value="false" />
-  <parameter name="SPEED_GRADE" value="7" />
-  <parameter name="SPIM0_Mode" value="Single Slave Select" />
-  <parameter name="SPIM0_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="SPIM1_Mode" value="Single Slave Select" />
-  <parameter name="SPIM1_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="SPIS0_Mode" value="N/A" />
-  <parameter name="SPIS0_PinMuxing" value="Unused" />
-  <parameter name="SPIS1_Mode" value="N/A" />
-  <parameter name="SPIS1_PinMuxing" value="Unused" />
-  <parameter name="STARVE_LIMIT" value="10" />
-  <parameter name="STM_Enable" value="true" />
-  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Cyclone V" />
-  <parameter name="TEST_Enable" value="false" />
-  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
-  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
-  <parameter name="TIMING_BOARD_AC_SKEW" value="0.03" />
-  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
-  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
-  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
-  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
-  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
-  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
-  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
-  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
-  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
-  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
-  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
-  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.03" />
-  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.02" />
-  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
-  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
-  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.08" />
-  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.16" />
-  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.09" />
-  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01" />
-  <parameter name="TIMING_BOARD_TDH" value="0.0" />
-  <parameter name="TIMING_BOARD_TDS" value="0.0" />
-  <parameter name="TIMING_BOARD_TIH" value="0.0" />
-  <parameter name="TIMING_BOARD_TIS" value="0.0" />
-  <parameter name="TIMING_TDH" value="65" />
-  <parameter name="TIMING_TDQSCK" value="255" />
-  <parameter name="TIMING_TDQSCKDL" value="1200" />
-  <parameter name="TIMING_TDQSCKDM" value="900" />
-  <parameter name="TIMING_TDQSCKDS" value="450" />
-  <parameter name="TIMING_TDQSH" value="0.35" />
-  <parameter name="TIMING_TDQSQ" value="125" />
-  <parameter name="TIMING_TDQSS" value="0.25" />
-  <parameter name="TIMING_TDS" value="30" />
-  <parameter name="TIMING_TDSH" value="0.2" />
-  <parameter name="TIMING_TDSS" value="0.2" />
-  <parameter name="TIMING_TIH" value="140" />
-  <parameter name="TIMING_TIS" value="180" />
-  <parameter name="TIMING_TQH" value="0.38" />
-  <parameter name="TIMING_TQHS" value="300" />
-  <parameter name="TIMING_TQSH" value="0.4" />
-  <parameter name="TPIUFPGA_Enable" value="false" />
-  <parameter name="TPIUFPGA_alt" value="false" />
-  <parameter name="TRACE_Mode" value="N/A" />
-  <parameter name="TRACE_PinMuxing" value="Unused" />
-  <parameter name="TRACKING_ERROR_TEST" value="false" />
-  <parameter name="TRACKING_WATCH_TEST" value="false" />
-  <parameter name="TREFI" value="35100" />
-  <parameter name="TRFC" value="350" />
-  <parameter name="UART0_Mode" value="No Flow Control" />
-  <parameter name="UART0_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="UART1_Mode" value="N/A" />
-  <parameter name="UART1_PinMuxing" value="Unused" />
-  <parameter name="USB0_Mode" value="N/A" />
-  <parameter name="USB0_PinMuxing" value="Unused" />
-  <parameter name="USB1_Mode" value="SDR" />
-  <parameter name="USB1_PinMuxing" value="HPS I/O Set 0" />
-  <parameter name="USER_DEBUG_LEVEL" value="1" />
-  <parameter name="USE_AXI_ADAPTOR" value="false" />
-  <parameter name="USE_FAKE_PHY" value="false" />
-  <parameter name="USE_MEM_CLK_FREQ" value="false" />
-  <parameter name="USE_MM_ADAPTOR" value="true" />
-  <parameter name="USE_SEQUENCER_BFM" value="false" />
-  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
-  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
-  <parameter name="can0_clk_div" value="1" />
-  <parameter name="can1_clk_div" value="1" />
-  <parameter name="configure_advanced_parameters" value="false" />
-  <parameter name="customize_device_pll_info" value="false" />
-  <parameter name="dbctrl_stayosc1" value="true" />
-  <parameter name="dbg_at_clk_div" value="0" />
-  <parameter name="dbg_clk_div" value="1" />
-  <parameter name="dbg_trace_clk_div" value="0" />
-  <parameter name="desired_can0_clk_mhz" value="100.0" />
-  <parameter name="desired_can1_clk_mhz" value="100.0" />
-  <parameter name="desired_cfg_clk_mhz" value="100.0" />
-  <parameter name="desired_emac0_clk_mhz" value="250.0" />
-  <parameter name="desired_emac1_clk_mhz" value="250.0" />
-  <parameter name="desired_gpio_db_clk_hz" value="32000" />
-  <parameter name="desired_l4_mp_clk_mhz" value="100.0" />
-  <parameter name="desired_l4_sp_clk_mhz" value="100.0" />
-  <parameter name="desired_mpu_clk_mhz" value="800.0" />
-  <parameter name="desired_nand_clk_mhz" value="12.5" />
-  <parameter name="desired_qspi_clk_mhz" value="400.0" />
-  <parameter name="desired_sdmmc_clk_mhz" value="200.0" />
-  <parameter name="desired_spi_m_clk_mhz" value="200.0" />
-  <parameter name="desired_usb_mp_clk_mhz" value="200.0" />
-  <parameter name="device_name" value="5CSXFC6D6F31C8ES" />
-  <parameter name="device_pll_info_manual">{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}</parameter>
-  <parameter name="eosc1_clk_mhz" value="25.0" />
-  <parameter name="eosc2_clk_mhz" value="25.0" />
-  <parameter name="gpio_db_clk_div" value="6249" />
-  <parameter name="l3_mp_clk_div" value="1" />
-  <parameter name="l3_sp_clk_div" value="1" />
-  <parameter name="l4_mp_clk_div" value="1" />
-  <parameter name="l4_mp_clk_source" value="1" />
-  <parameter name="l4_sp_clk_div" value="1" />
-  <parameter name="l4_sp_clk_source" value="1" />
-  <parameter name="main_pll_c3" value="3" />
-  <parameter name="main_pll_c4" value="3" />
-  <parameter name="main_pll_c5" value="15" />
-  <parameter name="main_pll_m" value="63" />
-  <parameter name="main_pll_n" value="0" />
-  <parameter name="nand_clk_source" value="2" />
-  <parameter name="periph_pll_c0" value="3" />
-  <parameter name="periph_pll_c1" value="3" />
-  <parameter name="periph_pll_c2" value="1" />
-  <parameter name="periph_pll_c3" value="19" />
-  <parameter name="periph_pll_c4" value="4" />
-  <parameter name="periph_pll_c5" value="9" />
-  <parameter name="periph_pll_m" value="79" />
-  <parameter name="periph_pll_n" value="1" />
-  <parameter name="periph_pll_source" value="0" />
-  <parameter name="qspi_clk_source" value="1" />
-  <parameter name="quartus_ini_hps_emif_pll" value="false" />
-  <parameter
-     name="quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces"
-     value="false" />
-  <parameter name="quartus_ini_hps_ip_enable_bsel_csel" value="false" />
-  <parameter
-     name="quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface"
-     value="false" />
-  <parameter
-     name="quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces"
-     value="false" />
-  <parameter name="quartus_ini_hps_ip_enable_test_interface" value="false" />
-  <parameter name="quartus_ini_hps_ip_f2sdram_bonding_out" value="false" />
-  <parameter name="quartus_ini_hps_ip_fast_f2sdram_sim_model" value="false" />
-  <parameter name="quartus_ini_hps_ip_suppress_sdram_synth" value="false" />
-  <parameter name="sdmmc_clk_source" value="2" />
-  <parameter name="show_advanced_parameters" value="false" />
-  <parameter name="show_debug_info_as_warning_msg" value="false" />
-  <parameter name="show_warning_as_error_msg" value="false" />
-  <parameter name="spi_m_clk_div" value="0" />
-  <parameter name="usb_mp_clk_div" value="0" />
-  <parameter name="use_default_mpu_clk" value="true" />
- </module>
- <module
-   name="hps_only_master"
-   kind="altera_jtag_avalon_master"
-   version="15.1"
-   enabled="1">
-  <parameter name="AUTO_DEVICE" value="5CSXFC6D6F31C8ES" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
-  <parameter name="COMPONENT_CLOCK" value="0" />
-  <parameter name="FAST_VER" value="0" />
-  <parameter name="FIFO_DEPTHS" value="2" />
-  <parameter name="PLI_PORT" value="50000" />
-  <parameter name="USE_PLI" value="0" />
- </module>
- <module
-   name="intr_capturer_0"
-   kind="intr_capturer"
-   version="100.99.98.97"
-   enabled="1">
-  <parameter name="AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED" value="7" />
-  <parameter name="NUM_INTR" value="32" />
- </module>
- <module
-   name="jtag_uart"
-   kind="altera_avalon_jtag_uart"
-   version="15.1"
-   enabled="1">
-  <parameter name="allowMultipleConnections" value="true" />
-  <parameter name="avalonSpec" value="2.0" />
-  <parameter name="clkFreq" value="50000000" />
-  <parameter name="hubInstanceID" value="0" />
-  <parameter name="readBufferDepth" value="64" />
-  <parameter name="readIRQThreshold" value="8" />
-  <parameter name="simInputCharacterStream" value="" />
-  <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
-  <parameter name="useRegistersForReadBuffer" value="false" />
-  <parameter name="useRegistersForWriteBuffer" value="false" />
-  <parameter name="useRelativePathForSimFile" value="false" />
-  <parameter name="writeBufferDepth" value="64" />
-  <parameter name="writeIRQThreshold" value="8" />
- </module>
- <module name="led_pio" kind="altera_avalon_pio" version="15.1" enabled="1">
-  <parameter name="bitClearingEdgeCapReg" value="false" />
-  <parameter name="bitModifyingOutReg" value="false" />
-  <parameter name="captureEdge" value="false" />
-  <parameter name="clockRate" value="50000000" />
-  <parameter name="direction" value="Output" />
-  <parameter name="edgeType" value="RISING" />
-  <parameter name="generateIRQ" value="false" />
-  <parameter name="irqType" value="LEVEL" />
-  <parameter name="resetValue" value="0" />
-  <parameter name="simDoTestBenchWiring" value="false" />
-  <parameter name="simDrivenValue" value="0" />
-  <parameter name="width" value="4" />
- </module>
- <module
-   name="mm_bridge_0"
-   kind="altera_avalon_mm_bridge"
-   version="15.1"
-   enabled="1">
-  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
-  <parameter name="ADDRESS_WIDTH" value="10" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
-  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
-  <parameter name="DATA_WIDTH" value="32" />
-  <parameter name="LINEWRAPBURSTS" value="0" />
-  <parameter name="MAX_BURST_SIZE" value="1" />
-  <parameter name="MAX_PENDING_RESPONSES" value="4" />
-  <parameter name="PIPELINE_COMMAND" value="1" />
-  <parameter name="PIPELINE_RESPONSE" value="1" />
-  <parameter name="SYMBOL_WIDTH" value="8" />
-  <parameter name="SYSINFO_ADDR_WIDTH" value="19" />
-  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="1" />
-  <parameter name="USE_RESPONSE" value="0" />
- </module>
- <module
-   name="onchip_memory2_0"
-   kind="altera_avalon_onchip_memory2"
-   version="15.1"
-   enabled="1">
-  <parameter name="allowInSystemMemoryContentEditor" value="false" />
-  <parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter>
-  <parameter name="blockType" value="AUTO" />
-  <parameter name="copyInitFile" value="false" />
-  <parameter name="dataWidth" value="64" />
-  <parameter name="deviceFamily" value="Cyclone V" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
-  <parameter name="dualPort" value="false" />
-  <parameter name="ecc_enabled" value="false" />
-  <parameter name="initMemContent" value="true" />
-  <parameter name="initializationFileName" value="onchip_memory2_0" />
-  <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="65536" />
-  <parameter name="readDuringWriteMode" value="DONT_CARE" />
-  <parameter name="resetrequest_enabled" value="true" />
-  <parameter name="simAllowMRAMContentsFile" value="false" />
-  <parameter name="simMemInitOnlyFilename" value="0" />
-  <parameter name="singleClockOperation" value="false" />
-  <parameter name="slave1Latency" value="1" />
-  <parameter name="slave2Latency" value="1" />
-  <parameter name="useNonDefaultInitFile" value="false" />
-  <parameter name="useShallowMemBlocks" value="false" />
-  <parameter name="writable" value="true" />
- </module>
- <module
-   name="sysid_qsys"
-   kind="altera_avalon_sysid_qsys"
-   version="15.1"
-   enabled="1">
-  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
-  <parameter name="id" value="5584" />
- </module>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="hps_0.h2f_lw_axi_master"
-   end="mm_bridge_0.s0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="mm_bridge_0.m0"
-   end="jtag_uart.avalon_jtag_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00020000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="mm_bridge_0.m0"
-   end="intr_capturer_0.avalon_slave_0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00030000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="mm_bridge_0.m0"
-   end="sysid_qsys.control_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00010000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="mm_bridge_0.m0"
-   end="dipsw_pio.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00010080" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="mm_bridge_0.m0"
-   end="onchip_memory2_0.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection kind="avalon" version="15.1" start="mm_bridge_0.m0" end="led_pio.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00010040" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="mm_bridge_0.m0"
-   end="button_pio.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x000100c0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="mm_bridge_0.m0"
-   end="hm2reg_io_0.slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00040000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="fpga_only_master.master"
-   end="jtag_uart.avalon_jtag_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00020000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="fpga_only_master.master"
-   end="intr_capturer_0.avalon_slave_0">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00030000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="fpga_only_master.master"
-   end="sysid_qsys.control_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00010000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="hps_only_master.master"
-   end="hps_0.f2h_axi_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="f2sdram_only_master.master"
-   end="hps_0.f2h_sdram0_data">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="fpga_only_master.master"
-   end="dipsw_pio.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00010080" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="fpga_only_master.master"
-   end="onchip_memory2_0.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="fpga_only_master.master"
-   end="led_pio.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00010040" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="fpga_only_master.master"
-   end="button_pio.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x000100c0" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="15.1"
-   start="fpga_only_master.master"
-   end="hm2reg_io_0.slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00040000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="clock"
-   version="15.1"
-   start="clk_0.clk"
-   end="hps_only_master.clk" />
- <connection kind="clock" version="15.1" start="clk_0.clk" end="sysid_qsys.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="clk_0.clk"
-   end="fpga_only_master.clk" />
- <connection kind="clock" version="15.1" start="clk_0.clk" end="dipsw_pio.clk" />
- <connection kind="clock" version="15.1" start="clk_0.clk" end="jtag_uart.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="clk_0.clk"
-   end="f2sdram_only_master.clk" />
- <connection kind="clock" version="15.1" start="clk_0.clk" end="mm_bridge_0.clk" />
- <connection kind="clock" version="15.1" start="clk_0.clk" end="led_pio.clk" />
- <connection kind="clock" version="15.1" start="clk_0.clk" end="button_pio.clk" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="clk_0.clk"
-   end="onchip_memory2_0.clk1" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="clk_0.clk"
-   end="intr_capturer_0.clock" />
- <connection kind="clock" version="15.1" start="clk_0.clk" end="hm2reg_io_0.clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="clk_0.clk"
-   end="hps_0.f2h_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="clk_0.clk"
-   end="hps_0.f2h_sdram0_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="clk_0.clk"
-   end="hps_0.h2f_axi_clock" />
- <connection
-   kind="clock"
-   version="15.1"
-   start="clk_0.clk"
-   end="hps_0.h2f_lw_axi_clock" />
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="hps_0.f2h_irq0"
-   end="jtag_uart.irq">
-  <parameter name="irqNumber" value="2" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="hps_0.f2h_irq0"
-   end="dipsw_pio.irq">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="hps_0.f2h_irq0"
-   end="button_pio.irq">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="intr_capturer_0.interrupt_receiver"
-   end="dipsw_pio.irq">
-  <parameter name="irqNumber" value="0" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="intr_capturer_0.interrupt_receiver"
-   end="jtag_uart.irq">
-  <parameter name="irqNumber" value="2" />
- </connection>
- <connection
-   kind="interrupt"
-   version="15.1"
-   start="intr_capturer_0.interrupt_receiver"
-   end="button_pio.irq">
-  <parameter name="irqNumber" value="1" />
- </connection>
- <connection
-   kind="reset"
-   version="15.1"
-   start="clk_0.clk_reset"
-   end="hps_only_master.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="clk_0.clk_reset"
-   end="fpga_only_master.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="clk_0.clk_reset"
-   end="f2sdram_only_master.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="clk_0.clk_reset"
-   end="sysid_qsys.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="clk_0.clk_reset"
-   end="dipsw_pio.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="clk_0.clk_reset"
-   end="jtag_uart.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="clk_0.clk_reset"
-   end="mm_bridge_0.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="clk_0.clk_reset"
-   end="led_pio.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="clk_0.clk_reset"
-   end="button_pio.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="clk_0.clk_reset"
-   end="hm2reg_io_0.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="clk_0.clk_reset"
-   end="onchip_memory2_0.reset1" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="clk_0.clk_reset"
-   end="intr_capturer_0.reset_sink" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="f2sdram_only_master.master_reset"
-   end="f2sdram_only_master.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="fpga_only_master.master_reset"
-   end="f2sdram_only_master.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="hps_only_master.master_reset"
-   end="f2sdram_only_master.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="f2sdram_only_master.master_reset"
-   end="fpga_only_master.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="fpga_only_master.master_reset"
-   end="fpga_only_master.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="hps_only_master.master_reset"
-   end="fpga_only_master.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="f2sdram_only_master.master_reset"
-   end="hps_only_master.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="fpga_only_master.master_reset"
-   end="hps_only_master.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="hps_only_master.master_reset"
-   end="hps_only_master.clk_reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="f2sdram_only_master.master_reset"
-   end="button_pio.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="fpga_only_master.master_reset"
-   end="button_pio.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="hps_only_master.master_reset"
-   end="button_pio.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="f2sdram_only_master.master_reset"
-   end="dipsw_pio.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="fpga_only_master.master_reset"
-   end="dipsw_pio.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="hps_only_master.master_reset"
-   end="dipsw_pio.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="f2sdram_only_master.master_reset"
-   end="jtag_uart.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="fpga_only_master.master_reset"
-   end="jtag_uart.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="hps_only_master.master_reset"
-   end="jtag_uart.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="f2sdram_only_master.master_reset"
-   end="led_pio.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="fpga_only_master.master_reset"
-   end="led_pio.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="hps_only_master.master_reset"
-   end="led_pio.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="f2sdram_only_master.master_reset"
-   end="mm_bridge_0.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="fpga_only_master.master_reset"
-   end="mm_bridge_0.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="hps_only_master.master_reset"
-   end="mm_bridge_0.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="f2sdram_only_master.master_reset"
-   end="sysid_qsys.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="fpga_only_master.master_reset"
-   end="sysid_qsys.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="hps_only_master.master_reset"
-   end="sysid_qsys.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="f2sdram_only_master.master_reset"
-   end="hm2reg_io_0.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="fpga_only_master.master_reset"
-   end="hm2reg_io_0.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="hps_only_master.master_reset"
-   end="hm2reg_io_0.reset" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="f2sdram_only_master.master_reset"
-   end="onchip_memory2_0.reset1" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="fpga_only_master.master_reset"
-   end="onchip_memory2_0.reset1" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="hps_only_master.master_reset"
-   end="onchip_memory2_0.reset1" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="f2sdram_only_master.master_reset"
-   end="intr_capturer_0.reset_sink" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="fpga_only_master.master_reset"
-   end="intr_capturer_0.reset_sink" />
- <connection
-   kind="reset"
-   version="15.1"
-   start="hps_only_master.master_reset"
-   end="intr_capturer_0.reset_sink" />
- <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
- <interconnectRequirement for="hps_only_master.master" name="qsys_mm.security" value="SECURE" />
-</system>
diff --git a/HW/QuartusProjects/SoCkit_GHRD/soc_system_board_info.xml b/HW/QuartusProjects/SoCkit_GHRD/soc_system_board_info.xml
deleted file mode 100755
index b2e043f8..00000000
--- a/HW/QuartusProjects/SoCkit_GHRD/soc_system_board_info.xml
+++ /dev/null
@@ -1,118 +0,0 @@
-<BoardInfo pov="hps_0_arm_a9_0">
-<!--
-This file is intended to be used when building device trees
-for the ArrowSoCKit Evaluation board.
-This board info file and hps_clock_info.xml are required input
-to sopc2dts to create a device tree suitable for the 3.9 version
-of the Linux kernel.  One typically executes sopc2dts as follows:
-
-	sopc2dts -i soc_system.sopcinfo -b soc_system_board_info.xml
-		-b hps_clock_info.xml -b hps_common_board_info.xml -o soc_system.dts
-
--->
-
-<DTAppend name="model" type="string" parentlabel="" val="Altera SOCFPGA Cyclone V"/>
-<DTAppend name="compatible" parentlabel="" >
-	<val type="string">altr,socfpga-cyclone5</val>
-	<val type="string">altr,socfpga</val>
-</DTAppend>
-
-<alias name="ethernet0" value="/sopc@0/ethernet@0xff702000"/>
-<alias name="spi0" value="/sopc@0/spi@0xfff00000"/>
-<alias name="spi1" value="/sopc@0/spi@0xfff01000"/>
-
-<!--<DTAppend name="master-ref-clk" type="number" parentlabel="hps_0_qspi" val="400000000"/>-->
-<DTAppend name="ext-decoder" type="number" parentlabel="hps_0_qspi" val="0"/>
-<DTAppend name="n25q00@0" type="node" parentlabel="hps_0_qspi" newlabel="flash0"/>
-<DTAppend name="#address-cells" type="number" parentlabel="hps_0_qspi" val="1"/>
-<DTAppend name="#size-cells" type="number" parentlabel="hps_0_qspi" val="0"/>
-<DTAppend name="#address-cells" type="number" parentlabel="flash0" val="1"/>
-<DTAppend name="#size-cells" type="number" parentlabel="flash0" val="1"/>
-<DTAppend name="compatible" type="string" parentlabel="flash0" val="n25q00"/>
-<DTAppend name="reg" type="number" parentlabel="flash0" val="0"/>
-<DTAppend name="spi-max-frequency" type="number" parentlabel="flash0" val="1000000"/>
-<DTAppend name="page-size" type="number" parentlabel="flash0" val="256"/>
-<DTAppend name="block-size" type="number" parentlabel="flash0" val="16"/>
-<DTAppend name="m25p,fast-read" type="bool" parentlabel="flash0" val="true"/>
-<DTAppend name="read-delay" type="number" parentlabel="flash0" val="4"/>
-<DTAppend name="tshsl-ns" type="number" parentlabel="flash0" val="50"/>
-<DTAppend name="tsd2d-ns" type="number" parentlabel="flash0" val="50"/>
-<DTAppend name="tchsh-ns" type="number" parentlabel="flash0" val="4"/>
-<DTAppend name="tslch-ns" type="number" parentlabel="flash0" val="4"/>
-<DTAppend name="partition@0" type="node" parentlabel="flash0" newlabel="part0"/>
-<DTAppend name="label" type="string" parentlabel="part0" val="Flash 0 Raw Data"/>
-<DTAppend name="reg" parentlabel="part0" >
-<val type="hex">0x0</val>
-<val type="hex">0x800000</val>
-</DTAppend>
-<DTAppend name="partition@800000" type="node" parentlabel="flash0" newlabel="part1"/>
-<DTAppend name="label" type="string" parentlabel="part1" val="Flash 1 jffs2 Filesystem"/>
-<DTAppend name="reg" parentlabel="part1">
-<val type="hex">0x800000</val>
-<val type="hex">0x800000</val>
-</DTAppend>
-
-<!--<DTAppend name="status" type="string" parentlabel="hps_0_spi0" val="disabled"/>
-<DTAppend name="status" type="string" parentlabel="hps_0_spi1" val="disabled"/>-->
-
-
-<DTAppend name="phy-mode" type="string" parentlabel="hps_0_gmac1" val="rgmii"/>
-
-<!--<DTAppend name="snps,multicast-filter-bins" type="number" parentlabel="hps_0_gmac1" val="256"/>
-<DTAppend name="snps,perfect-filter-entries" type="number" parentlabel="hps_0_gmac1" val="128"/>-->
-<DTAppend name="snps,phy-addr" type="hex" parentlabel="hps_0_gmac1" val="0xffffffff"/>
-<DTAppend name="phy-addr" type="hex" parentlabel="hps_0_gmac1" val="0xffffffff"/>
-<DTAppend name="txc-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="rxc-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="txen-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="rxdv-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="rxd0-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="rxd1-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="rxd2-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="rxd3-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="txd0-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="txd1-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="txd2-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="txd3-skew-ps" type="number" parentlabel="hps_0_gmac1" val="0"/>
-<DTAppend name="max-frame-size" type="number" parentlabel="hps_0_gmac1" val="3800"/>
-
-
-<DTAppend name="usbphy@0" type="node" parentlabel="sopc0" newlabel="usbphy0" />
-<DTAppend name="#phy-cells" type="number" val="0" parentlabel="usbphy0" />
-<DTAppend name="compatible" type="string" val="usb-nop-xceiv" parentlabel="usbphy0" />
-<DTAppend name="status" type="string" val="okay" parentlabel="usbphy0" />
-
-<DTAppend name="phys" type="phandle" parentlabel="hps_0_usb1" val="usbphy0" />
-
-
-<DTAppend name="#address-cells" type="number" parentlabel="hps_0_sdmmc" val="1"/>
-<DTAppend name="#size-cells" type="number" parentlabel="hps_0_sdmmc" val="0"/>
-<DTAppend name="supports-highspeed"  parentlabel="hps_0_sdmmc" />
-<DTAppend name="broken-cd" type="bool" parentlabel="hps_0_sdmmc" val="true"/>
-<DTAppend name="compatible" type="string" parentlabel="hps_0_sdmmc" val="altr,socfpga-dw-mshc" action="replace"/>
-<DTAppend name="altr,dw-mshc-ciu-div" type="number" parentlabel="hps_0_sdmmc" val="3"/>
-<DTAppend name="altr,dw-mshc-sdr-timing"  parentlabel="hps_0_sdmmc" >
-<val type="number">0</val>
-<val type="number">3</val>
-</DTAppend>
-<DTAppend name="slot@0" type="node" parentlabel="hps_0_sdmmc" newlabel="slot_0"/>
-<DTAppend name="reg" type="number" parentlabel="slot_0" val="0"/>
-<DTAppend name="bus-width" type="number" parentlabel="slot_0" val="4"/>
-
-
-<DTAppend name="spidev@0" type="node" parentlabel="hps_0_spim0" newlabel="spidev0"/>
-<DTAppend name="compatible" type="string" parentlabel="spidev0" val="spidev"/>
-<DTAppend name="reg" type="number" parentlabel="spidev0" val="0"/>
-<DTAppend name="spi-max-frequency" type="number" parentlabel="spidev0" val="1000000"/>
-<DTAppend name="enable-dma" type="number" parentlabel="spidev0" val="1"/>
-
-<DTAppend name="spidev@0" type="node" parentlabel="hps_0_spim1" newlabel="spidev1"/>
-<DTAppend name="compatible" type="string" parentlabel="spidev1" val="spidev"/>
-<DTAppend name="reg" type="number" parentlabel="spidev1" val="0"/>
-<DTAppend name="spi-max-frequency" type="number" parentlabel="spidev1" val="1000000"/>
-<DTAppend name="enable-dma" type="number" parentlabel="spidev1" val="1"/>
-
-<Chosen>
-        <Bootargs val="console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"></Bootargs>
-</Chosen>
-</BoardInfo>
diff --git a/HW/QuartusProjects/SoCkit_GHRD/soc_system_timing.sdc b/HW/QuartusProjects/SoCkit_GHRD/soc_system_timing.sdc
deleted file mode 100644
index acd29af2..00000000
--- a/HW/QuartusProjects/SoCkit_GHRD/soc_system_timing.sdc
+++ /dev/null
@@ -1,126 +0,0 @@
-# 50MHz board input clock
-create_clock -period 20 [get_ports clk_bot1]
-create_clock -period 40 [get_ports hps_i2c1_SCL]
-create_clock -period 40 [get_ports hps_usb1_CLK]
-
-# for enhancing USB BlasterII to be reliable, 25MHz
-create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
-set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi]
-set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms]
-set_output_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdo]
-
-# FPGA IO port constraints
-set_false_path -from [get_ports {user_pb_fpga[0]}] -to *
-set_false_path -from [get_ports {user_pb_fpga[1]}] -to *
-set_false_path -from [get_ports {user_pb_fpga[2]}] -to *
-set_false_path -from [get_ports {user_pb_fpga[3]}] -to *
-set_false_path -from [get_ports {user_dipsw_fpga[0]}] -to *
-set_false_path -from [get_ports {user_dipsw_fpga[1]}] -to *
-set_false_path -from [get_ports {user_dipsw_fpga[2]}] -to *
-set_false_path -from [get_ports {user_dipsw_fpga[3]}] -to *
-set_false_path -from * -to [get_ports {user_led_fpga[0]}]
-set_false_path -from * -to [get_ports {user_led_fpga[1]}]
-set_false_path -from * -to [get_ports {user_led_fpga[2]}]
-set_false_path -from * -to [get_ports {user_led_fpga[3]}]
-
-# HPS peripherals port false path setting to workaround the unconstraint path (setting false_path for hps_0 ports will not affect the routing as it is hard silicon)
-
-set_false_path -from * -to [get_ports {hps_usb1_CLK}]
-set_false_path -from * -to [get_ports {hps_emac1_TX_CLK}] 
-set_false_path -from * -to [get_ports {hps_emac1_TXD0}] 
-set_false_path -from * -to [get_ports {hps_emac1_TXD1}] 
-set_false_path -from * -to [get_ports {hps_emac1_TXD2}] 
-set_false_path -from * -to [get_ports {hps_emac1_TXD3}] 
-set_false_path -from * -to [get_ports {hps_emac1_MDC}] 
-set_false_path -from * -to [get_ports {hps_emac1_TX_CTL}] 
-set_false_path -from * -to [get_ports {hps_qspi_SS0}] 
-set_false_path -from * -to [get_ports {hps_qspi_CLK}] 
-set_false_path -from * -to [get_ports {hps_sdio_CLK}] 
-set_false_path -from * -to [get_ports {hps_usb1_STP}] 
-set_false_path -from * -to [get_ports {hps_spim0_CLK}] 
-set_false_path -from * -to [get_ports {hps_spim0_MOSI}] 
-set_false_path -from * -to [get_ports {hps_spim0_SS0}] 
-set_false_path -from * -to [get_ports {hps_spim1_CLK}] 
-set_false_path -from * -to [get_ports {hps_spim1_MOSI}] 
-set_false_path -from * -to [get_ports {hps_spim1_SS0}] 
-set_false_path -from * -to [get_ports {hps_spim1_MISO}] 
-set_false_path -from * -to [get_ports {hps_uart0_TX}] 
-set_false_path -from * -to [get_ports {hps_can0_TX}] 
-
-set_false_path -from * -to [get_ports {hps_emac1_MDIO}] 
-set_false_path -from * -to [get_ports {hps_qspi_IO0}] 
-set_false_path -from * -to [get_ports {hps_qspi_IO1}] 
-set_false_path -from * -to [get_ports {hps_qspi_IO2}] 
-set_false_path -from * -to [get_ports {hps_qspi_IO3}] 
-set_false_path -from * -to [get_ports {hps_sdio_CMD}] 
-set_false_path -from * -to [get_ports {hps_sdio_D0}] 
-set_false_path -from * -to [get_ports {hps_sdio_D1}] 
-set_false_path -from * -to [get_ports {hps_sdio_D2}] 
-set_false_path -from * -to [get_ports {hps_sdio_D3}] 
-set_false_path -from * -to [get_ports {hps_usb1_D0}] 
-set_false_path -from * -to [get_ports {hps_usb1_D1}] 
-set_false_path -from * -to [get_ports {hps_usb1_D2}] 
-set_false_path -from * -to [get_ports {hps_usb1_D3}] 
-set_false_path -from * -to [get_ports {hps_usb1_D4}] 
-set_false_path -from * -to [get_ports {hps_usb1_D5}] 
-set_false_path -from * -to [get_ports {hps_usb1_D6}] 
-set_false_path -from * -to [get_ports {hps_usb1_D7}] 
-set_false_path -from * -to [get_ports {hps_i2c0_SDA}] 
-set_false_path -from * -to [get_ports {hps_i2c1_SDA}] 
-set_false_path -from * -to [get_ports {hps_i2c1_SCL}] 
-set_false_path -from * -to [get_ports {hps_gpio_GPIO00}] 
-set_false_path -from * -to [get_ports {hps_gpio_GPIO09}] 
-set_false_path -from * -to [get_ports {hps_gpio_GPIO35}] 
-set_false_path -from * -to [get_ports {hps_gpio_GPIO48}] 
-set_false_path -from * -to [get_ports {hps_gpio_GPIO53}] 
-set_false_path -from * -to [get_ports {hps_gpio_GPIO54}] 
-set_false_path -from * -to [get_ports {hps_gpio_GPIO55}] 
-set_false_path -from * -to [get_ports {hps_gpio_GPIO56}] 
-set_false_path -from * -to [get_ports {hps_gpio_GPIO61}] 
-set_false_path -from * -to [get_ports {hps_gpio_GPIO62}] 
-
-set_false_path -from [get_ports {hps_emac1_MDIO}] -to *
-set_false_path -from [get_ports {hps_qspi_IO0}] -to *
-set_false_path -from [get_ports {hps_qspi_IO1}] -to *
-set_false_path -from [get_ports {hps_qspi_IO2}] -to *
-set_false_path -from [get_ports {hps_qspi_IO3}] -to *
-set_false_path -from [get_ports {hps_sdio_CMD}] -to *
-set_false_path -from [get_ports {hps_sdio_D0}] -to *
-set_false_path -from [get_ports {hps_sdio_D1}] -to *
-set_false_path -from [get_ports {hps_sdio_D2}] -to *
-set_false_path -from [get_ports {hps_sdio_D3}] -to *
-set_false_path -from [get_ports {hps_usb1_D0}] -to *
-set_false_path -from [get_ports {hps_usb1_D1}] -to *
-set_false_path -from [get_ports {hps_usb1_D2}] -to *
-set_false_path -from [get_ports {hps_usb1_D3}] -to *
-set_false_path -from [get_ports {hps_usb1_D4}] -to *
-set_false_path -from [get_ports {hps_usb1_D5}] -to *
-set_false_path -from [get_ports {hps_usb1_D6}] -to *
-set_false_path -from [get_ports {hps_usb1_D7}] -to *
-set_false_path -from [get_ports {hps_i2c0_SCL}] -to *
-set_false_path -from [get_ports {hps_i2c1_SCL}] -to *
-set_false_path -from [get_ports {hps_i2c1_SDA}] -to *
-set_false_path -from [get_ports {hps_gpio_GPIO00}] -to *
-set_false_path -from [get_ports {hps_gpio_GPIO09}] -to *
-set_false_path -from [get_ports {hps_gpio_GPIO35}] -to *
-set_false_path -from [get_ports {hps_gpio_GPIO48}] -to *
-set_false_path -from [get_ports {hps_gpio_GPIO53}] -to *
-set_false_path -from [get_ports {hps_gpio_GPIO54}] -to *
-set_false_path -from [get_ports {hps_gpio_GPIO55}] -to *
-set_false_path -from [get_ports {hps_gpio_GPIO56}] -to *
-set_false_path -from [get_ports {hps_gpio_GPIO61}] -to *
-set_false_path -from [get_ports {hps_gpio_GPIO62}] -to *
-
-set_false_path -from [get_ports {hps_emac1_RX_CTL}] -to *
-set_false_path -from [get_ports {hps_emac1_RX_CLK}] -to *
-set_false_path -from [get_ports {hps_emac1_RXD0}] -to *
-set_false_path -from [get_ports {hps_emac1_RXD1}] -to *
-set_false_path -from [get_ports {hps_emac1_RXD2}] -to *
-set_false_path -from [get_ports {hps_emac1_RXD3}] -to *
-set_false_path -from [get_ports {hps_usb1_CLK}] -to *
-set_false_path -from [get_ports {hps_usb1_DIR}] -to *
-set_false_path -from [get_ports {hps_usb1_NXT}] -to *
-set_false_path -from [get_ports {hps_spim0_MISO}] -to *
-set_false_path -from [get_ports {hps_spim1_MISO}] -to *
-set_false_path -from [get_ports {hps_uart0_RX}] -to *
-set_false_path -from [get_ports {hps_can0_RX}] -to *
diff --git a/HW/QuartusProjects/SoCkit_GHRD/sockit_set_hsmc_to_THDB-HTG_gpio.tcl b/HW/QuartusProjects/SoCkit_GHRD/sockit_set_hsmc_to_THDB-HTG_gpio.tcl
deleted file mode 100644
index 31beec79..00000000
--- a/HW/QuartusProjects/SoCkit_GHRD/sockit_set_hsmc_to_THDB-HTG_gpio.tcl
+++ /dev/null
@@ -1,438 +0,0 @@
-# Load Quartus II Tcl Project package
-package require ::quartus::project
-
-set need_to_close_project 0
-set make_assignments 1
-
-
-set make_assignments 1
-
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[9]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[13]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[14]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[15]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[16]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[17]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[18]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[19]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[20]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[21]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[22]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[23]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[24]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[25]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[26]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[27]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[28]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[29]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[30]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[31]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[32]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[33]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[34]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO0[35]
-
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[9]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[13]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[14]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[15]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[16]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[17]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[18]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[19]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[20]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[21]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[22]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[23]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[24]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[25]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[26]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[27]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[28]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[29]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[30]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[31]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[32]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[33]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[34]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIO1[35]
-
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n8
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p8
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n8
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p8
-
-
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clk_in0
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clk_out0
-
-set_instance_assignment -name IO_STANDARD HCSL -to hsmc_ref_clk_n
-set_instance_assignment -name IO_STANDARD HCSL -to hsmc_ref_clk_p
-
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_scl
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_sda
-
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkin_n[1]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkin_n[2]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkin_p[1]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkin_p[2]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkout_n[1]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkout_n[2]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkout_p[1]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkout_p[2]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clk_in0
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clk_out0
-#
-# set_instance_assignment -name IO_STANDARD HCSL -to hsmc_ref_clk_n
-# set_instance_assignment -name IO_STANDARD HCSL -to hsmc_ref_clk_p
-#
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[0]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[1]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[2]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[3]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[4]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[5]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[6]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[7]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[8]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[9]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[10]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[11]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[12]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[13]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[14]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[15]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[16]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[0]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[1]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[2]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[3]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[4]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[5]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[6]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[7]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[8]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[9]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[10]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[11]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[12]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[13]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[14]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[15]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[16]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_scl
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_sda
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[0]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[1]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[2]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[3]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[4]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[5]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[6]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[7]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[8]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[9]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[10]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[11]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[12]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[13]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[14]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[15]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[16]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[0]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[1]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[2]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[3]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[4]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[5]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[6]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[7]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[8]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[9]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[10]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[11]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[12]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[13]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[14]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[15]
-# set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[16]
-
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[0]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[1]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[2]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[3]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[4]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[5]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[6]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[7]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[0]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[1]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[2]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[3]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[4]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[5]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[6]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[7]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[0]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[1]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[2]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[3]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[4]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[5]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[6]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[7]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[0]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[1]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[2]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[3]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[4]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[5]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[6]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[7]
-
-set_location_assignment PIN_G15 -to GPIO0[0]
-set_location_assignment PIN_F14 -to GPIO0[1]
-set_location_assignment PIN_H15 -to GPIO0[2]
-set_location_assignment PIN_F15 -to GPIO0[3]
-set_location_assignment PIN_A13 -to GPIO0[4]
-set_location_assignment PIN_G13 -to GPIO0[5]
-set_location_assignment PIN_B13 -to GPIO0[6]
-set_location_assignment PIN_H14 -to GPIO0[7]
-set_location_assignment PIN_B11 -to GPIO0[8]
-set_location_assignment PIN_E13 -to GPIO0[9]
-set_location_assignment PIN_C12 -to GPIO0[10]
-set_location_assignment PIN_F13 -to GPIO0[11]
-set_location_assignment PIN_B8 -to GPIO0[12]
-set_location_assignment PIN_B12 -to GPIO0[13]
-set_location_assignment PIN_C8 -to GPIO0[14]
-set_location_assignment PIN_C13 -to GPIO0[15]
-set_location_assignment PIN_A10 -to GPIO0[16]
-set_location_assignment PIN_D10 -to GPIO0[17]
-set_location_assignment PIN_A11 -to GPIO0[18]
-set_location_assignment PIN_D11 -to GPIO0[19]
-set_location_assignment PIN_B7 -to GPIO0[20]
-set_location_assignment PIN_D12 -to GPIO0[21]
-set_location_assignment PIN_C7 -to GPIO0[22]
-set_location_assignment PIN_E12 -to GPIO0[23]
-set_location_assignment PIN_A5 -to GPIO0[24]
-set_location_assignment PIN_D9 -to GPIO0[25]
-set_location_assignment PIN_A6 -to GPIO0[26]
-set_location_assignment PIN_E9 -to GPIO0[27]
-set_location_assignment PIN_A3 -to GPIO0[28]
-set_location_assignment PIN_B5 -to GPIO0[29]
-set_location_assignment PIN_A4 -to GPIO0[30]
-set_location_assignment PIN_B6 -to GPIO0[31]
-set_location_assignment PIN_B2 -to GPIO0[32]
-set_location_assignment PIN_C2 -to GPIO0[33]
-set_location_assignment PIN_B1 -to GPIO0[34]
-set_location_assignment PIN_D2 -to GPIO0[35]
-
-set_location_assignment PIN_AB27 -to GPIO1[0]
-set_location_assignment PIN_F8 -to GPIO1[1]
-set_location_assignment PIN_AA26 -to GPIO1[2]
-set_location_assignment PIN_F9 -to GPIO1[3]
-set_location_assignment PIN_B3 -to GPIO1[4]
-set_location_assignment PIN_G8 -to GPIO1[5]
-set_location_assignment PIN_C3 -to GPIO1[6]
-set_location_assignment PIN_H8 -to GPIO1[7]
-set_location_assignment PIN_D4 -to GPIO1[8]
-set_location_assignment PIN_H7 -to GPIO1[9]
-set_location_assignment PIN_E4 -to GPIO1[10]
-set_location_assignment PIN_J7 -to GPIO1[11]
-set_location_assignment PIN_E2 -to GPIO1[12]
-set_location_assignment PIN_K8 -to GPIO1[13]
-set_location_assignment PIN_E3 -to GPIO1[14]
-set_location_assignment PIN_K7 -to GPIO1[15]
-set_location_assignment PIN_E6 -to GPIO1[16]
-set_location_assignment PIN_J9 -to GPIO1[17]
-set_location_assignment PIN_E7 -to GPIO1[18]
-set_location_assignment PIN_J10 -to GPIO1[19]
-set_location_assignment PIN_C4 -to GPIO1[20]
-set_location_assignment PIN_F10 -to GPIO1[21]
-set_location_assignment PIN_D5 -to GPIO1[22]
-set_location_assignment PIN_G10 -to GPIO1[23]
-set_location_assignment PIN_C5 -to GPIO1[24]
-set_location_assignment PIN_J12 -to GPIO1[25]
-set_location_assignment PIN_D6 -to GPIO1[26]
-set_location_assignment PIN_K12 -to GPIO1[27]
-set_location_assignment PIN_F6 -to GPIO1[28]
-set_location_assignment PIN_G11 -to GPIO1[29]
-set_location_assignment PIN_G7 -to GPIO1[30]
-set_location_assignment PIN_G12 -to GPIO1[31]
-set_location_assignment PIN_D7 -to GPIO1[32]
-set_location_assignment PIN_A8 -to GPIO1[33]
-set_location_assignment PIN_E8 -to GPIO1[34]
-set_location_assignment PIN_A9 -to GPIO1[35]
-
-set_location_assignment PIN_D1 -to hsmc_tx_n8
-set_location_assignment PIN_E1 -to hsmc_tx_p8
-set_location_assignment PIN_E11 -to hsmc_rx_n8
-set_location_assignment PIN_F11 -to hsmc_rx_p8
-
-set_location_assignment PIN_C10 -to hsmc_d[0]
-set_location_assignment PIN_C9 -to hsmc_d[2]
-set_location_assignment PIN_H13 -to hsmc_d[1]
-set_location_assignment PIN_H12 -to hsmc_d[3]
-
-set_location_assignment PIN_J14 -to hsmc_clk_in0
-set_location_assignment PIN_AD29 -to hsmc_clk_out0
-
-
-set_location_assignment PIN_AA28 -to hsmc_scl
-set_location_assignment PIN_AE29 -to hsmc_sda
-
-# set_location_assignment PIN_AB27 -to hsmc_clkin_n[1]
-# set_location_assignment PIN_AA26 -to hsmc_clkin_p[1]
-# set_location_assignment PIN_G15 -to hsmc_clkin_n[2]
-# set_location_assignment PIN_H15 -to hsmc_clkin_p[2]
-# set_location_assignment PIN_E6 -to hsmc_clkout_n[1]
-# set_location_assignment PIN_E7 -to hsmc_clkout_p[1]
-# set_location_assignment PIN_A10 -to hsmc_clkout_n[2]
-# set_location_assignment PIN_A11 -to hsmc_clkout_p[2]
-# set_location_assignment PIN_J14 -to hsmc_clk_in0
-# set_location_assignment PIN_AD29 -to hsmc_clk_out0
-#
-#
-# set_location_assignment PIN_AE1 -to hsmc_gxb_rx_n[0]
-# set_location_assignment PIN_AC1 -to hsmc_gxb_rx_n[1]
-# set_location_assignment PIN_AA1 -to hsmc_gxb_rx_n[2]
-# set_location_assignment PIN_W1 -to hsmc_gxb_rx_n[3]
-# set_location_assignment PIN_U1 -to hsmc_gxb_rx_n[4]
-# set_location_assignment PIN_R1 -to hsmc_gxb_rx_n[5]
-# set_location_assignment PIN_N1 -to hsmc_gxb_rx_n[6]
-# set_location_assignment PIN_L1 -to hsmc_gxb_rx_n[7]
-# set_location_assignment PIN_AE2 -to hsmc_gxb_rx_p[0]
-# set_location_assignment PIN_AC2 -to hsmc_gxb_rx_p[1]
-# set_location_assignment PIN_AA2 -to hsmc_gxb_rx_p[2]
-# set_location_assignment PIN_W2 -to hsmc_gxb_rx_p[3]
-# set_location_assignment PIN_U2 -to hsmc_gxb_rx_p[4]
-# set_location_assignment PIN_R2 -to hsmc_gxb_rx_p[5]
-# set_location_assignment PIN_N2 -to hsmc_gxb_rx_p[6]
-# set_location_assignment PIN_L2 -to hsmc_gxb_rx_p[7]
-# set_location_assignment PIN_AD3 -to hsmc_gxb_tx_n[0]
-# set_location_assignment PIN_AB3 -to hsmc_gxb_tx_n[1]
-# set_location_assignment PIN_Y3 -to hsmc_gxb_tx_n[2]
-# set_location_assignment PIN_V3 -to hsmc_gxb_tx_n[3]
-# set_location_assignment PIN_T3 -to hsmc_gxb_tx_n[4]
-# set_location_assignment PIN_P3 -to hsmc_gxb_tx_n[5]
-# set_location_assignment PIN_M3 -to hsmc_gxb_tx_n[6]
-# set_location_assignment PIN_K3 -to hsmc_gxb_tx_n[7]
-# set_location_assignment PIN_AD4 -to hsmc_gxb_tx_p[0]
-# set_location_assignment PIN_AB4 -to hsmc_gxb_tx_p[1]
-# set_location_assignment PIN_Y4 -to hsmc_gxb_tx_p[2]
-# set_location_assignment PIN_V4 -to hsmc_gxb_tx_p[3]
-# set_location_assignment PIN_T4 -to hsmc_gxb_tx_p[4]
-# set_location_assignment PIN_P4 -to hsmc_gxb_tx_p[5]
-# set_location_assignment PIN_M4 -to hsmc_gxb_tx_p[6]
-# set_location_assignment PIN_K4 -to hsmc_gxb_tx_p[7]
-# set_location_assignment PIN_W7 -to hsmc_ref_clk_n
-# set_location_assignment PIN_W8 -to hsmc_ref_clk_p
-#
-# set_location_assignment PIN_G12 -to hsmc_rx_p[0]
-# set_location_assignment PIN_G11 -to hsmc_rx_n[0]
-# set_location_assignment PIN_K12 -to hsmc_rx_p[1]
-# set_location_assignment PIN_J12 -to hsmc_rx_n[1]
-# set_location_assignment PIN_G10 -to hsmc_rx_p[2]
-# set_location_assignment PIN_F10 -to hsmc_rx_n[2]
-# set_location_assignment PIN_J10 -to hsmc_rx_p[3]
-# set_location_assignment PIN_J9 -to hsmc_rx_n[3]
-# set_location_assignment PIN_K7 -to hsmc_rx_p[4]
-# set_location_assignment PIN_K8 -to hsmc_rx_n[4]
-# set_location_assignment PIN_J7 -to hsmc_rx_p[5]
-# set_location_assignment PIN_H7 -to hsmc_rx_n[5]
-# set_location_assignment PIN_H8 -to hsmc_rx_p[6]
-# set_location_assignment PIN_G8 -to hsmc_rx_n[6]
-# set_location_assignment PIN_F9 -to hsmc_rx_p[7]
-# set_location_assignment PIN_F8 -to hsmc_rx_n[7]
-# set_location_assignment PIN_F11 -to hsmc_rx_p[8]
-# set_location_assignment PIN_E11 -to hsmc_rx_n[8]
-# set_location_assignment PIN_B6 -to hsmc_rx_p[9]
-# set_location_assignment PIN_B5 -to hsmc_rx_n[9]
-# set_location_assignment PIN_E9 -to hsmc_rx_p[10]
-# set_location_assignment PIN_D9 -to hsmc_rx_n[10]
-# set_location_assignment PIN_E12 -to hsmc_rx_p[11]
-# set_location_assignment PIN_D12 -to hsmc_rx_n[11]
-# set_location_assignment PIN_D11 -to hsmc_rx_p[12]
-# set_location_assignment PIN_D10 -to hsmc_rx_n[12]
-# set_location_assignment PIN_C13 -to hsmc_rx_p[13]
-# set_location_assignment PIN_B12 -to hsmc_rx_n[13]
-# set_location_assignment PIN_F13 -to hsmc_rx_p[14]
-# set_location_assignment PIN_E13 -to hsmc_rx_n[14]
-# set_location_assignment PIN_H14 -to hsmc_rx_p[15]
-# set_location_assignment PIN_G13 -to hsmc_rx_n[15]
-# set_location_assignment PIN_F15 -to hsmc_rx_p[16]
-# set_location_assignment PIN_F14 -to hsmc_rx_n[16]
-#
-#
-# set_location_assignment PIN_A9 -to hsmc_tx_p[0]
-# set_location_assignment PIN_A8 -to hsmc_tx_n[0]
-# set_location_assignment PIN_E8 -to hsmc_tx_p[1]
-# set_location_assignment PIN_D7 -to hsmc_tx_n[1]
-# set_location_assignment PIN_G7 -to hsmc_tx_p[2]
-# set_location_assignment PIN_F6 -to hsmc_tx_n[2]
-# set_location_assignment PIN_D6 -to hsmc_tx_p[3]
-# set_location_assignment PIN_C5 -to hsmc_tx_n[3]
-# set_location_assignment PIN_D5 -to hsmc_tx_p[4]
-# set_location_assignment PIN_C4 -to hsmc_tx_n[4]
-# set_location_assignment PIN_E3 -to hsmc_tx_p[5]
-# set_location_assignment PIN_E2 -to hsmc_tx_n[5]
-# set_location_assignment PIN_E4 -to hsmc_tx_p[6]
-# set_location_assignment PIN_D4 -to hsmc_tx_n[6]
-# set_location_assignment PIN_C3 -to hsmc_tx_p[7]
-# set_location_assignment PIN_B3 -to hsmc_tx_n[7]
-# set_location_assignment PIN_D1 -to hsmc_tx_n[8]
-# set_location_assignment PIN_E1 -to hsmc_tx_p[8]
-# set_location_assignment PIN_D2 -to hsmc_tx_p[9]
-# set_location_assignment PIN_C2 -to hsmc_tx_n[9]
-# set_location_assignment PIN_B1 -to hsmc_tx_p[10]
-# set_location_assignment PIN_B2 -to hsmc_tx_n[10]
-# set_location_assignment PIN_A4 -to hsmc_tx_p[11]
-# set_location_assignment PIN_A3 -to hsmc_tx_n[11]
-# set_location_assignment PIN_A6 -to hsmc_tx_p[12]
-# set_location_assignment PIN_A5 -to hsmc_tx_n[12]
-# set_location_assignment PIN_C7 -to hsmc_tx_p[13]
-# set_location_assignment PIN_B7 -to hsmc_tx_n[13]
-# set_location_assignment PIN_C8 -to hsmc_tx_p[14]
-# set_location_assignment PIN_B8 -to hsmc_tx_n[14]
-# set_location_assignment PIN_C12 -to hsmc_tx_p[15]
-# set_location_assignment PIN_B11 -to hsmc_tx_n[15]
-# set_location_assignment PIN_B13 -to hsmc_tx_p[16]
-# set_location_assignment PIN_A13 -to hsmc_tx_n[16]
-#
-# set_location_assignment PIN_C10 -to hsmc_d[0]
-# set_location_assignment PIN_C9 -to hsmc_d[2]
-# set_location_assignment PIN_H13 -to hsmc_d[1]
-# set_location_assignment PIN_H12 -to hsmc_d[3]
-#
-# set_location_assignment PIN_AA28 -to hsmc_scl
-# set_location_assignment PIN_AE29 -to hsmc_sda
-
-
-
-	# Commit assignments
-	export_assignments
-
diff --git a/HW/QuartusProjects/SoCkit_GHRD/top/arrow_gold_fpga_top_pins.tcl b/HW/QuartusProjects/SoCkit_GHRD/top/arrow_gold_fpga_top_pins.tcl
deleted file mode 100755
index aaf9cba7..00000000
--- a/HW/QuartusProjects/SoCkit_GHRD/top/arrow_gold_fpga_top_pins.tcl
+++ /dev/null
@@ -1,471 +0,0 @@
-# Load Quartus II Tcl Project package
-package require ::quartus::project
-
-set need_to_close_project 0
-set make_assignments 1
-
-
-set make_assignments 1
-set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_100m_fpga
-set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_50m_fpga
-set_location_assignment PIN_Y26 -to clk_100m_fpga
-set_location_assignment PIN_K14 -to clk_50m_fpga
-
-set_instance_assignment -name IO_STANDARD "1.5 V" -to clk_top1
-set_instance_assignment -name IO_STANDARD "1.5 V" -to clk_bot1
-set_location_assignment PIN_AA16 -to clk_top1
-set_location_assignment PIN_AF14 -to clk_bot1	
-
-#	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cpu_resetn	
-#	set_location_assignment PIN_AD27 -to cpu_resetn
-	
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_a
-set_location_assignment PIN_AJ14 -to ddr3_fpga_a[0]
-set_location_assignment PIN_AK14 -to ddr3_fpga_a[1]
-set_location_assignment PIN_AH12 -to ddr3_fpga_a[2]
-set_location_assignment PIN_AJ12 -to ddr3_fpga_a[3]
-set_location_assignment PIN_AG15 -to ddr3_fpga_a[4]
-set_location_assignment PIN_AH15 -to ddr3_fpga_a[5]
-set_location_assignment PIN_AK12 -to ddr3_fpga_a[6]
-set_location_assignment PIN_AK13 -to ddr3_fpga_a[7]
-set_location_assignment PIN_AH13 -to ddr3_fpga_a[8]
-set_location_assignment PIN_AH14 -to ddr3_fpga_a[9]
-set_location_assignment PIN_AJ9 -to ddr3_fpga_a[10]
-set_location_assignment PIN_AK9 -to ddr3_fpga_a[11]
-set_location_assignment PIN_AK7 -to ddr3_fpga_a[12]
-set_location_assignment PIN_AK8 -to ddr3_fpga_a[13]
-set_location_assignment PIN_AG12 -to ddr3_fpga_a[14]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_ba
-set_location_assignment PIN_AH10 -to ddr3_fpga_ba[0]
-set_location_assignment PIN_AJ11 -to ddr3_fpga_ba[1]
-set_location_assignment PIN_AK11 -to ddr3_fpga_ba[2]
-set_location_assignment PIN_AH7 -to ddr3_fpga_casn
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_casn
-set_location_assignment PIN_AJ21 -to ddr3_fpga_cke
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_cke
-set_location_assignment PIN_AA15 -to ddr3_fpga_clk_n
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_clk_n
-set_location_assignment PIN_AA14 -to ddr3_fpga_clk_p
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_clk_p
-set_location_assignment PIN_AB15 -to ddr3_fpga_csn
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_csn
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_dm
-set_location_assignment PIN_AH17 -to ddr3_fpga_dm[0]
-set_location_assignment PIN_AG23 -to ddr3_fpga_dm[1]
-set_location_assignment PIN_AK23 -to ddr3_fpga_dm[2]
-set_location_assignment PIN_AJ27 -to ddr3_fpga_dm[3]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_dq
-set_location_assignment PIN_AF18 -to ddr3_fpga_dq[0]
-set_location_assignment PIN_AE17 -to ddr3_fpga_dq[1]
-set_location_assignment PIN_AG16 -to ddr3_fpga_dq[2]
-set_location_assignment PIN_AF16 -to ddr3_fpga_dq[3]
-set_location_assignment PIN_AH20 -to ddr3_fpga_dq[4]
-set_location_assignment PIN_AG21 -to ddr3_fpga_dq[5]
-set_location_assignment PIN_AJ16 -to ddr3_fpga_dq[6]
-set_location_assignment PIN_AH18 -to ddr3_fpga_dq[7]
-set_location_assignment PIN_AK18 -to ddr3_fpga_dq[8]
-set_location_assignment PIN_AJ17 -to ddr3_fpga_dq[9]
-set_location_assignment PIN_AG18 -to ddr3_fpga_dq[10]
-set_location_assignment PIN_AK19 -to ddr3_fpga_dq[11]
-set_location_assignment PIN_AG20 -to ddr3_fpga_dq[12]
-set_location_assignment PIN_AF19 -to ddr3_fpga_dq[13]
-set_location_assignment PIN_AJ20 -to ddr3_fpga_dq[14]
-set_location_assignment PIN_AH24 -to ddr3_fpga_dq[15]
-set_location_assignment PIN_AE19 -to ddr3_fpga_dq[16]
-set_location_assignment PIN_AE18 -to ddr3_fpga_dq[17]
-set_location_assignment PIN_AG22 -to ddr3_fpga_dq[18]
-set_location_assignment PIN_AK22 -to ddr3_fpga_dq[19]
-set_location_assignment PIN_AF21 -to ddr3_fpga_dq[20]
-set_location_assignment PIN_AF20 -to ddr3_fpga_dq[21]
-set_location_assignment PIN_AH23 -to ddr3_fpga_dq[22]
-set_location_assignment PIN_AK24 -to ddr3_fpga_dq[23]
-set_location_assignment PIN_AF24 -to ddr3_fpga_dq[24]
-set_location_assignment PIN_AF23 -to ddr3_fpga_dq[25]
-set_location_assignment PIN_AJ24 -to ddr3_fpga_dq[26]
-set_location_assignment PIN_AK26 -to ddr3_fpga_dq[27]
-set_location_assignment PIN_AE23 -to ddr3_fpga_dq[28]
-set_location_assignment PIN_AE22 -to ddr3_fpga_dq[29]
-set_location_assignment PIN_AG25 -to ddr3_fpga_dq[30]
-set_location_assignment PIN_AK27 -to ddr3_fpga_dq[31]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_dqs_n
-set_location_assignment PIN_W16 -to ddr3_fpga_dqs_n[0]
-set_location_assignment PIN_W17 -to ddr3_fpga_dqs_n[1]
-set_location_assignment PIN_AA18 -to ddr3_fpga_dqs_n[2]
-set_location_assignment PIN_AD19 -to ddr3_fpga_dqs_n[3]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_dqs_p
-set_location_assignment PIN_V16 -to ddr3_fpga_dqs_p[0]
-set_location_assignment PIN_V17 -to ddr3_fpga_dqs_p[1]
-set_location_assignment PIN_Y17 -to ddr3_fpga_dqs_p[2]
-set_location_assignment PIN_AC20 -to ddr3_fpga_dqs_p[3]
-set_location_assignment PIN_AE16 -to ddr3_fpga_odt
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_odt
-set_location_assignment PIN_AH8 -to ddr3_fpga_rasn
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_rasn
-set_location_assignment PIN_AK21 -to ddr3_fpga_resetn
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_resetn
-set_location_assignment PIN_AJ6 -to ddr3_fpga_wen
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_wen
-set_location_assignment PIN_AG17 -to ddr3_fpga_rzq
-set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_fpga_rzq
-
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blank_n
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_clk
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_hs
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_sync_n
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" to vga_vs 	
-	
-set_location_assignment PIN_AE28 -to vga_b[0]
-set_location_assignment PIN_Y23 -to vga_b[1]
-set_location_assignment PIN_Y24 -to vga_b[2]
-set_location_assignment PIN_AG28 -to vga_b[3]
-set_location_assignment PIN_AF28 -to vga_b[4]
-set_location_assignment PIN_V23 -to vga_b[5]
-set_location_assignment PIN_W24 -to vga_b[6]
-set_location_assignment PIN_AF29 -to vga_b[7]
-set_location_assignment PIN_AH3 -to vga_blank_n
-set_location_assignment PIN_W20 -to vga_clk
-set_location_assignment PIN_Y21 -to vga_g[0]
-set_location_assignment PIN_AA25 -to vga_g[1]
-set_location_assignment PIN_AB26 -to vga_g[2]
-set_location_assignment PIN_AB22 -to vga_g[3]
-set_location_assignment PIN_AB23 -to vga_g[4]
-set_location_assignment PIN_AA24 -to vga_g[5]
-set_location_assignment PIN_AB25 -to vga_g[6]
-set_location_assignment PIN_AE27 -to vga_g[7]
-set_location_assignment PIN_AD12 -to vga_hs
-set_location_assignment PIN_AA12 -to vga_r[0]
-set_location_assignment PIN_AB12 -to vga_r[1]
-set_location_assignment PIN_AF6 -to vga_r[2]
-set_location_assignment PIN_AG6 -to vga_r[3]
-set_location_assignment PIN_AG5 -to vga_r[4]
-set_location_assignment PIN_AH5 -to vga_r[5]
-set_location_assignment PIN_AJ1 -to vga_r[6]
-set_location_assignment PIN_AJ2 -to vga_r[7]
-set_location_assignment PIN_AG2 -to vga_sync_n
-set_location_assignment PIN_AC12 -to vga_vs 
-
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_adcdat
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_adclrck
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_bclk
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_dacdat
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_daclrck
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_i2c_sclk
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_i2c_sdat
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_mute
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to aud_xck
-
-set_location_assignment PIN_AC27 -to aud_adcdat
-set_location_assignment PIN_AG30 -to aud_adclrck
-set_location_assignment PIN_AE7 -to aud_bclk
-set_location_assignment PIN_AG3 -to aud_dacdat
-set_location_assignment PIN_AH4 -to aud_daclrck
-set_location_assignment PIN_AH30 -to aud_i2c_sclk
-set_location_assignment PIN_AF30 -to aud_i2c_sdat
-set_location_assignment PIN_AD26 -to aud_mute
-set_location_assignment PIN_AC9 -to aud_xck
-
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fan_ctrl	
-set_location_assignment PIN_AG27 -to fan_ctrl
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to irda_rxd	
-set_location_assignment PIN_AH2 -to irda_rxd
-	
-	
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkin_n[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkin_n[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkin_p[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkin_p[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkout_n[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkout_n[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkout_p[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkout_p[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clk_in0
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clk_out0	
-
-set_instance_assignment -name IO_STANDARD HCSL -to hsmc_ref_clk_n
-set_instance_assignment -name IO_STANDARD HCSL -to hsmc_ref_clk_p
-
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[9]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[13]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[14]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[15]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[16]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[7]
-set_instance_assignment -name IO_STANDARD "2.5 V"-to hsmc_rx_p[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[9]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[13]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[14]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[15]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[16]	
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_scl
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_sda	
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[9]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[13]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[14]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[15]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[16]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[4]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[5]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[6]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[7]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[8]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[9]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[10]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[11]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[12]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[13]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[14]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[15]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[16]	
-
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[0]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[1]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[2]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[3]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[4]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[5]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[6]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_n[7]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[0]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[1]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[2]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[3]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[4]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[5]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[6]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_rx_p[7]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[0]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[1]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[2]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[3]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[4]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[5]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[6]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_n[7]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[0]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[1]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[2]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[3]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[4]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[5]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[6]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmc_gxb_tx_p[7]
-
-set_location_assignment PIN_AB27 -to hsmc_clkin_n[1]
-set_location_assignment PIN_AA26 -to hsmc_clkin_p[1]
-set_location_assignment PIN_G15 -to hsmc_clkin_n[2]
-set_location_assignment PIN_H15 -to hsmc_clkin_p[2]
-set_location_assignment PIN_E6 -to hsmc_clkout_n[1]
-set_location_assignment PIN_E7 -to hsmc_clkout_p[1]
-set_location_assignment PIN_A10 -to hsmc_clkout_n[2]
-set_location_assignment PIN_A11 -to hsmc_clkout_p[2]
-set_location_assignment PIN_J14 -to hsmc_clk_in0
-set_location_assignment PIN_AD29 -to hsmc_clk_out0
-
-
-set_location_assignment PIN_AE1 -to hsmc_gxb_rx_n[0]
-set_location_assignment PIN_AC1 -to hsmc_gxb_rx_n[1]
-set_location_assignment PIN_AA1 -to hsmc_gxb_rx_n[2]
-set_location_assignment PIN_W1 -to hsmc_gxb_rx_n[3]
-set_location_assignment PIN_U1 -to hsmc_gxb_rx_n[4]
-set_location_assignment PIN_R1 -to hsmc_gxb_rx_n[5]
-set_location_assignment PIN_N1 -to hsmc_gxb_rx_n[6]
-set_location_assignment PIN_L1 -to hsmc_gxb_rx_n[7]
-set_location_assignment PIN_AE2 -to hsmc_gxb_rx_p[0]
-set_location_assignment PIN_AC2 -to hsmc_gxb_rx_p[1]
-set_location_assignment PIN_AA2 -to hsmc_gxb_rx_p[2]
-set_location_assignment PIN_W2 -to hsmc_gxb_rx_p[3]
-set_location_assignment PIN_U2 -to hsmc_gxb_rx_p[4]
-set_location_assignment PIN_R2 -to hsmc_gxb_rx_p[5]
-set_location_assignment PIN_N2 -to hsmc_gxb_rx_p[6]
-set_location_assignment PIN_L2 -to hsmc_gxb_rx_p[7]
-set_location_assignment PIN_AD3 -to hsmc_gxb_tx_n[0]
-set_location_assignment PIN_AB3 -to hsmc_gxb_tx_n[1]
-set_location_assignment PIN_Y3 -to hsmc_gxb_tx_n[2]
-set_location_assignment PIN_V3 -to hsmc_gxb_tx_n[3]
-set_location_assignment PIN_T3 -to hsmc_gxb_tx_n[4]
-set_location_assignment PIN_P3 -to hsmc_gxb_tx_n[5]
-set_location_assignment PIN_M3 -to hsmc_gxb_tx_n[6]
-set_location_assignment PIN_K3 -to hsmc_gxb_tx_n[7]
-set_location_assignment PIN_AD4 -to hsmc_gxb_tx_p[0]
-set_location_assignment PIN_AB4 -to hsmc_gxb_tx_p[1]
-set_location_assignment PIN_Y4 -to hsmc_gxb_tx_p[2]
-set_location_assignment PIN_V4 -to hsmc_gxb_tx_p[3]
-set_location_assignment PIN_T4 -to hsmc_gxb_tx_p[4]
-set_location_assignment PIN_P4 -to hsmc_gxb_tx_p[5]
-set_location_assignment PIN_M4 -to hsmc_gxb_tx_p[6]
-set_location_assignment PIN_K4 -to hsmc_gxb_tx_p[7]
-set_location_assignment PIN_W7 -to hsmc_ref_clk_n
-set_location_assignment PIN_W8 -to hsmc_ref_clk_p
-
-set_location_assignment PIN_G12 -to hsmc_rx_p[0]
-set_location_assignment PIN_G11 -to hsmc_rx_n[0]	
-set_location_assignment PIN_K12 -to hsmc_rx_p[1]
-set_location_assignment PIN_J12 -to hsmc_rx_n[1]	
-set_location_assignment PIN_G10 -to hsmc_rx_p[2]
-set_location_assignment PIN_F10 -to hsmc_rx_n[2]			
-set_location_assignment PIN_J10 -to hsmc_rx_p[3]	
-set_location_assignment PIN_J9 -to hsmc_rx_n[3]	
-set_location_assignment PIN_K7 -to hsmc_rx_p[4]		
-set_location_assignment PIN_K8 -to hsmc_rx_n[4]	
-set_location_assignment PIN_J7 -to hsmc_rx_p[5]		
-set_location_assignment PIN_H7 -to hsmc_rx_n[5]	
-set_location_assignment PIN_H8 -to hsmc_rx_p[6]
-set_location_assignment PIN_G8 -to hsmc_rx_n[6]	
-set_location_assignment PIN_F9 -to hsmc_rx_p[7]
-set_location_assignment PIN_F8 -to hsmc_rx_n[7]
-set_location_assignment PIN_F11 -to hsmc_rx_p[8]
-set_location_assignment PIN_E11 -to hsmc_rx_n[8]
-set_location_assignment PIN_B6 -to hsmc_rx_p[9]	
-set_location_assignment PIN_B5 -to hsmc_rx_n[9]	
-set_location_assignment PIN_E9 -to hsmc_rx_p[10]	
-set_location_assignment PIN_D9 -to hsmc_rx_n[10]		
-set_location_assignment PIN_E12 -to hsmc_rx_p[11]	
-set_location_assignment PIN_D12 -to hsmc_rx_n[11]		
-set_location_assignment PIN_D11 -to hsmc_rx_p[12]	
-set_location_assignment PIN_D10 -to hsmc_rx_n[12]	
-set_location_assignment PIN_C13 -to hsmc_rx_p[13]	
-set_location_assignment PIN_B12 -to hsmc_rx_n[13]	
-set_location_assignment PIN_F13 -to hsmc_rx_p[14]	
-set_location_assignment PIN_E13 -to hsmc_rx_n[14]	
-set_location_assignment PIN_H14 -to hsmc_rx_p[15]	
-set_location_assignment PIN_G13 -to hsmc_rx_n[15]
-set_location_assignment PIN_F15 -to hsmc_rx_p[16]	
-set_location_assignment PIN_F14 -to hsmc_rx_n[16]	
-
-
-set_location_assignment PIN_A9 -to hsmc_tx_p[0]
-set_location_assignment PIN_A8 -to hsmc_tx_n[0]	
-set_location_assignment PIN_E8 -to hsmc_tx_p[1]
-set_location_assignment PIN_D7 -to hsmc_tx_n[1]	
-set_location_assignment PIN_G7 -to hsmc_tx_p[2]
-set_location_assignment PIN_F6 -to hsmc_tx_n[2]	
-set_location_assignment PIN_D6 -to hsmc_tx_p[3]	
-set_location_assignment PIN_C5 -to hsmc_tx_n[3]		
-set_location_assignment PIN_D5 -to hsmc_tx_p[4]	
-set_location_assignment PIN_C4 -to hsmc_tx_n[4]	
-set_location_assignment PIN_E3 -to hsmc_tx_p[5]	
-set_location_assignment PIN_E2 -to hsmc_tx_n[5]
-set_location_assignment PIN_E4 -to hsmc_tx_p[6]
-set_location_assignment PIN_D4 -to hsmc_tx_n[6]
-set_location_assignment PIN_C3 -to hsmc_tx_p[7]	
-set_location_assignment PIN_B3 -to hsmc_tx_n[7]
-set_location_assignment PIN_D1 -to hsmc_tx_n[8]
-set_location_assignment PIN_E1 -to hsmc_tx_p[8]
-set_location_assignment PIN_D2 -to hsmc_tx_p[9]
-set_location_assignment PIN_C2 -to hsmc_tx_n[9]	
-set_location_assignment PIN_B1 -to hsmc_tx_p[10]
-set_location_assignment PIN_B2 -to hsmc_tx_n[10]
-set_location_assignment PIN_A4 -to hsmc_tx_p[11]
-set_location_assignment PIN_A3 -to hsmc_tx_n[11]		
-set_location_assignment PIN_A6 -to hsmc_tx_p[12]
-set_location_assignment PIN_A5 -to hsmc_tx_n[12]	
-set_location_assignment PIN_C7 -to hsmc_tx_p[13]
-set_location_assignment PIN_B7 -to hsmc_tx_n[13]		
-set_location_assignment PIN_C8 -to hsmc_tx_p[14]
-set_location_assignment PIN_B8 -to hsmc_tx_n[14]	
-set_location_assignment PIN_C12 -to hsmc_tx_p[15]
-set_location_assignment PIN_B11 -to hsmc_tx_n[15]		
-set_location_assignment PIN_B13 -to hsmc_tx_p[16]
-set_location_assignment PIN_A13 -to hsmc_tx_n[16]		
-
-set_location_assignment PIN_C10 -to hsmc_d[0]
-set_location_assignment PIN_C9 -to hsmc_d[2]
-set_location_assignment PIN_H13 -to hsmc_d[1]
-set_location_assignment PIN_H12 -to hsmc_d[3]
-
-set_location_assignment PIN_AA28 -to hsmc_scl
-set_location_assignment PIN_AE29 -to hsmc_sda
-	
-set_location_assignment PIN_W25 -to user_dipsw_fpga[0]
-set_location_assignment PIN_V25 -to user_dipsw_fpga[1]
-set_location_assignment PIN_AC28 -to user_dipsw_fpga[2]
-set_location_assignment PIN_AC29 -to user_dipsw_fpga[3]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to user_dipsw_fpga[0]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to user_dipsw_fpga[1]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to user_dipsw_fpga[2]
-set_instance_assignment -name IO_STANDARD "2.5 V" -to user_dipsw_fpga[3]
-set_location_assignment PIN_AF10 -to user_led_fpga[0]
-set_location_assignment PIN_AD10 -to user_led_fpga[1]
-set_location_assignment PIN_AE11 -to user_led_fpga[2]
-set_location_assignment PIN_AD7 -to user_led_fpga[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_led_fpga[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_led_fpga[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_led_fpga[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_led_fpga[3]
-set_location_assignment PIN_AE9 -to user_pb_fpga[0]
-set_location_assignment PIN_AE12 -to user_pb_fpga[1]
-set_location_assignment PIN_AD9 -to user_pb_fpga[2]
-set_location_assignment PIN_AD11 -to user_pb_fpga[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_pb_fpga[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_pb_fpga[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_pb_fpga[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_pb_fpga[1]
-    
-    
-	# Commit assignments
-	export_assignments
-    
-}   
-    
\ No newline at end of file
diff --git a/HW/QuartusProjects/SoCkit_GHRD/top/arrow_gold_top_pins.tcl b/HW/QuartusProjects/SoCkit_GHRD/top/arrow_gold_top_pins.tcl
deleted file mode 100755
index b099e311..00000000
--- a/HW/QuartusProjects/SoCkit_GHRD/top/arrow_gold_top_pins.tcl
+++ /dev/null
@@ -1,927 +0,0 @@
-# Copyright (C) 1991-2012 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-
-# Quartus II: Generate Tcl File for Project
-# File: 
-# Generated on: Thu Jan 10 12:11:48 2013
-
-# Load Quartus II Tcl Project package
-package require ::quartus::project
-
-set need_to_close_project 0
-set make_assignments 1
-
-# Check that the right project is open
-if {[is_project_open]} {
-	if {[string compare $quartus(project) "c5sx_soc"]} {
-		puts "Project c5sx_soc is not open"
-		set make_assignments 0
-	}
-} else {
-	# Only open if not already open
-	if {[project_exists c5sx_soc]} {
-		project_open -revision c5sx_soc c5sx_soc_top
-	} else {
-		project_new -revision c5sx_soc c5sx_soc
-	}
-	set need_to_close_project 1
-}
-
-# Make assignments
-if {$make_assignments} {
-
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_rzq -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[0] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[0] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[0] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[1] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[1] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[1] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[2] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[2] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[2] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[3] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[3] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[3] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[4] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[4] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[4] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[5] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[5] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[5] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[6] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[6] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[6] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[7] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[7] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[7] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[8] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[8] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[8] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[9] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[9] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[9] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[10] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[10] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[10] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[11] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[11] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[11] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[12] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[12] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[12] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[13] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[13] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[13] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[14] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[14] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[14] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[15] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[15] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[15] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[16] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[16] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[16] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[17] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[17] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[17] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[18] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[18] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[18] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[19] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[19] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[19] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[20] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[20] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[20] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[21] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[21] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[21] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[22] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[22] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[22] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[23] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[23] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[23] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[24] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[24] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[24] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[25] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[25] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[25] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[26] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[26] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[26] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[27] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[27] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[27] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[28] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[28] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[28] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[29] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[29] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[29] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[30] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[30] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[30] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[31] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[31] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[31] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[32] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[32] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[32] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[33] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[33] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[33] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[34] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[34] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[34] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[35] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[35] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[35] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[36] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[36] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[36] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[37] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[37] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[37] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[38] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[38] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[38] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[39] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[39] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[39] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs_p[0] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_p[0] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_p[0] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs_p[1] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_p[1] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_p[1] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs_p[2] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_p[2] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_p[2] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs_p[3] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_p[3] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_p[3] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs_p[4] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_p[4] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_p[4] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs_n[0] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[0] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[0] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs_n[1] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[1] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[1] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs_n[2] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[2] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[2] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs_n[3] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[3] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[3] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs_n[4] -tag __hps_sdram_p0
-	set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[4] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[4] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_clk_p -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_hps_clk_p -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_clk_n -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_hps_clk_n -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[0] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[0] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[10] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[10] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[11] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[11] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[12] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[12] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[13] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[13] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[14] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[14] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[1] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[1] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[2] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[2] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[3] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[3] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[4] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[4] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[5] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[5] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[6] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[6] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[7] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[7] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[8] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[8] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[9] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[9] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_ba[0] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_ba[0] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_ba[1] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_ba[1] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_ba[2] -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_ba[2] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_casn -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_casn -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_cke -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_cke -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_csn -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_csn -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_odt -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_odt -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_rasn -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_rasn -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_wen -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_wen -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_resetn -tag __hps_sdram_p0
-	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_resetn -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dm[0] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dm[0] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dm[1] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dm[1] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dm[2] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dm[2] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dm[3] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dm[3] -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dm[4] -tag __hps_sdram_p0
-	set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dm[4] -tag __hps_sdram_p0
-	set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_mem_stable_n -tag __hps_sdram_p0
-	set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_n -tag __hps_sdram_p0
-	set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer -tag __hps_sdram_p0
-	set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] -tag __hps_sdram_p0
-	set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __hps_sdram_p0
-	set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer -tag __hps_sdram_p0
-	set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1] -tag __hps_sdram_p0
-	set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -tag __hps_sdram_p0
-	set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer -tag __hps_sdram_p0
-	set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2] -tag __hps_sdram_p0
-	set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2] -tag __hps_sdram_p0
-	set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer -tag __hps_sdram_p0
-	set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3] -tag __hps_sdram_p0
-	set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3] -tag __hps_sdram_p0
-	set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].read_capture_clk_buffer -tag __hps_sdram_p0
-	set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[4] -tag __hps_sdram_p0
-	set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[4] -tag __hps_sdram_p0
-	set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to u0|hps_0|hps_io|border|hps_sdram_inst -tag __hps_sdram_p0
-	set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to u0|hps_0|hps_io|border|hps_sdram_inst|pll0|fbout -tag __hps_sdram_p0
-	set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_hps_a
-	set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_hps_ba
-	set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_hps_dm
-	set_location_assignment PIN_F26 -to ddr3_hps_a[0]
-	set_location_assignment PIN_G30 -to ddr3_hps_a[1]
-	set_location_assignment PIN_F28 -to ddr3_hps_a[2]
-	set_location_assignment PIN_F30 -to ddr3_hps_a[3]
-	set_location_assignment PIN_J25 -to ddr3_hps_a[4]
-	set_location_assignment PIN_J27 -to ddr3_hps_a[5]
-	set_location_assignment PIN_F29 -to ddr3_hps_a[6]
-	set_location_assignment PIN_E28 -to ddr3_hps_a[7]
-	set_location_assignment PIN_H27 -to ddr3_hps_a[8]
-	set_location_assignment PIN_G26 -to ddr3_hps_a[9]
-	set_location_assignment PIN_D29 -to ddr3_hps_a[10]
-	set_location_assignment PIN_C30 -to ddr3_hps_a[11]
-	set_location_assignment PIN_B30 -to ddr3_hps_a[12]
-	set_location_assignment PIN_C29 -to ddr3_hps_a[13]
-	set_location_assignment PIN_H25 -to ddr3_hps_a[14]
-	set_location_assignment PIN_E29 -to ddr3_hps_ba[0]
-	set_location_assignment PIN_J24 -to ddr3_hps_ba[1]
-	set_location_assignment PIN_J23 -to ddr3_hps_ba[2]
-	set_location_assignment PIN_K28 -to ddr3_hps_dm[0]
-	set_location_assignment PIN_M28 -to ddr3_hps_dm[1]
-	set_location_assignment PIN_R28 -to ddr3_hps_dm[2]
-	set_location_assignment PIN_W30 -to ddr3_hps_dm[3]
-#	set_location_assignment PIN_W27 -to ddr3_hps_dm[4]
-	set_location_assignment PIN_K23 -to ddr3_hps_dq[0]
-	set_location_assignment PIN_K22 -to ddr3_hps_dq[1]
-	set_location_assignment PIN_H30 -to ddr3_hps_dq[2]
-	set_location_assignment PIN_G28 -to ddr3_hps_dq[3]
-	set_location_assignment PIN_L25 -to ddr3_hps_dq[4]
-	set_location_assignment PIN_L24 -to ddr3_hps_dq[5]
-	set_location_assignment PIN_J30 -to ddr3_hps_dq[6]
-	set_location_assignment PIN_J29 -to ddr3_hps_dq[7]
-	set_location_assignment PIN_K26 -to ddr3_hps_dq[8]
-	set_location_assignment PIN_L26 -to ddr3_hps_dq[9]
-	set_location_assignment PIN_K29 -to ddr3_hps_dq[10]
-	set_location_assignment PIN_K27 -to ddr3_hps_dq[11]
-	set_location_assignment PIN_M26 -to ddr3_hps_dq[12]
-	set_location_assignment PIN_M27 -to ddr3_hps_dq[13]
-	set_location_assignment PIN_L28 -to ddr3_hps_dq[14]
-	set_location_assignment PIN_M30 -to ddr3_hps_dq[15]
-	set_location_assignment PIN_U26 -to ddr3_hps_dq[16]
-	set_location_assignment PIN_T26 -to ddr3_hps_dq[17]
-	set_location_assignment PIN_N29 -to ddr3_hps_dq[18]
-	set_location_assignment PIN_N28 -to ddr3_hps_dq[19]
-	set_location_assignment PIN_P26 -to ddr3_hps_dq[20]
-	set_location_assignment PIN_P27 -to ddr3_hps_dq[21]
-	set_location_assignment PIN_N27 -to ddr3_hps_dq[22]
-	set_location_assignment PIN_R29 -to ddr3_hps_dq[23]
-	set_location_assignment PIN_P24 -to ddr3_hps_dq[24]
-	set_location_assignment PIN_P25 -to ddr3_hps_dq[25]
-	set_location_assignment PIN_T29 -to ddr3_hps_dq[26]
-	set_location_assignment PIN_T28 -to ddr3_hps_dq[27]
-	set_location_assignment PIN_R27 -to ddr3_hps_dq[28]
-	set_location_assignment PIN_R26 -to ddr3_hps_dq[29]
-	set_location_assignment PIN_V30 -to ddr3_hps_dq[30]
-	set_location_assignment PIN_W29 -to ddr3_hps_dq[31]
-	set_location_assignment PIN_N18 -to ddr3_hps_dqs_p[0]
-	set_location_assignment PIN_N25 -to ddr3_hps_dqs_p[1]
-	set_location_assignment PIN_R19 -to ddr3_hps_dqs_p[2]
-	set_location_assignment PIN_R22 -to ddr3_hps_dqs_p[3]
-	set_location_assignment PIN_E27 -to ddr3_hps_casn
-	set_location_assignment PIN_L29 -to ddr3_hps_cke
-	set_location_assignment PIN_L23 -to ddr3_hps_clk_n
-	set_location_assignment PIN_M23 -to ddr3_hps_clk_p
-	set_location_assignment PIN_H24 -to ddr3_hps_csn
-	set_location_assignment PIN_H28 -to ddr3_hps_odt
-	set_location_assignment PIN_D30 -to ddr3_hps_rasn
-	set_location_assignment PIN_P30 -to ddr3_hps_resetn
-	set_location_assignment PIN_C28 -to ddr3_hps_wen
-	set_location_assignment PIN_D27 -to ddr3_hps_rzq
-	
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk_50_hps
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk_25_hps
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rst_n_hps
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to warm_rst_n_hps
-	
-	set_location_assignment PIN_D25 -to clk_50_hps
-	set_location_assignment PIN_F25 -to clk_25_hps
-	set_location_assignment PIN_C27 -to warm_rst_n_hps	
-	set_location_assignment PIN_F23 -to rst_n_hps
-	
-	set_instance_assignment -name IO_STANDARD "1.5-V" -to user_dipsw_hps
-	set_location_assignment PIN_V20 -to user_dipsw_hps[0]
-	set_location_assignment PIN_P22 -to user_dipsw_hps[1]
-	set_location_assignment PIN_P29 -to user_dipsw_hps[2]
-	set_location_assignment PIN_N30 -to user_dipsw_hps[3]
-	
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to user_led_hps
-	set_location_assignment PIN_A24 -to user_led_hps[0]
-	set_location_assignment PIN_G21 -to user_led_hps[1]
-	set_location_assignment PIN_C24 -to user_led_hps[2]
-	set_location_assignment PIN_E23 -to user_led_hps[3]
-
-	set_instance_assignment -name IO_STANDARD "1.5-V" -to user_pb_hps
-	set_location_assignment PIN_T30 -to user_pb_hps[0]
-	set_location_assignment PIN_U28 -to user_pb_hps[1]
-	set_location_assignment PIN_T21 -to user_pb_hps[2]
-	set_location_assignment PIN_U20 -to user_pb_hps[3]
-	
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart_rx
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart_tx
-	set_location_assignment PIN_B25 -to uart_rx
-	set_location_assignment PIN_C25 -to uart_tx
-
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i2c_scl_hps
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i2c_sda_hps	
-	set_location_assignment PIN_H23 -to i2c_scl_hps
-	set_location_assignment PIN_A25 -to i2c_sda_hps
-
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi1_csn	
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_csn
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_miso
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_mosi
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_sck	
-	set_location_assignment PIN_B22 -to hps_gsensor_int
-	set_location_assignment PIN_H20 -to spi_csn
-	set_location_assignment PIN_B23 -to spi_miso
-	set_location_assignment PIN_C22 -to spi_mosi
-	set_location_assignment PIN_A23 -to spi_sck
-
-	
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_clk
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_ss0
-	set_location_assignment PIN_D19 -to qspi_clk
-	set_location_assignment PIN_C20 -to qspi_io[0]
-	set_location_assignment PIN_H18 -to qspi_io[1]
-	set_location_assignment PIN_A19 -to qspi_io[2]
-	set_location_assignment PIN_E19 -to qspi_io[3]
-	set_location_assignment PIN_A18 -to qspi_ss0
-
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sd_clk
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sd_cmd
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sd_pwren
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sd_dat	
-	set_location_assignment PIN_B16 -to sd_dat[3]
-	set_location_assignment PIN_A16 -to sd_clk
-	set_location_assignment PIN_F18 -to sd_cmd
-	set_location_assignment PIN_G18 -to sd_dat[0]
-	set_location_assignment PIN_C17 -to sd_dat[1]
-	set_location_assignment PIN_D17 -to sd_dat[2]
-	set_location_assignment PIN_B17 -to sd_pwren
-
-	
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to usb_clk
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to usb_data
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to usb_nxt
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to usb_stp
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to usb_dir
-	
-	set_location_assignment PIN_N16 -to usb_clk
-	set_location_assignment PIN_E16 -to usb_data[0]
-	set_location_assignment PIN_G16 -to usb_data[1]
-	set_location_assignment PIN_D16 -to usb_data[2]
-	set_location_assignment PIN_D14 -to usb_data[3]
-	set_location_assignment PIN_A15 -to usb_data[4]
-	set_location_assignment PIN_C14 -to usb_data[5]
-	set_location_assignment PIN_D15 -to usb_data[6]
-	set_location_assignment PIN_M17 -to usb_data[7]
-	set_location_assignment PIN_A14 -to usb_nxt
-	set_location_assignment PIN_E14 -to usb_dir
-	set_location_assignment PIN_C15 -to usb_stp
-	
-	
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_hps_gtx_clk
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_hps_mdc
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_hps_mdio
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_hps_rx_clk
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_hps_rx_dv
-
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_hps_rxd
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_hps_tx_en
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_hps_txd	
-	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_hps_intn
-	
-	set_location_assignment PIN_H19 -to enet_hps_gtx_clk
-	set_location_assignment PIN_F20 -to enet_hps_txd[0]
-	set_location_assignment PIN_J19 -to enet_hps_txd[1]
-	set_location_assignment PIN_F21 -to enet_hps_txd[2]
-	set_location_assignment PIN_F19 -to enet_hps_txd[3]
-	set_location_assignment PIN_A21 -to enet_hps_rxd[0]	
-	set_location_assignment PIN_E21 -to enet_hps_mdio
-	set_location_assignment PIN_B21 -to enet_hps_mdc
-	set_location_assignment PIN_K17 -to enet_hps_rx_dv	
-	set_location_assignment PIN_A20 -to enet_hps_tx_en	
-	set_location_assignment PIN_G20 -to enet_hps_rx_clk
-	set_location_assignment PIN_B20 -to enet_hps_rxd[1]
-	set_location_assignment PIN_B18 -to enet_hps_rxd[2]
-	set_location_assignment PIN_D21 -to enet_hps_rxd[3]
-	set_location_assignment PIN_C19 -to enet_hps_intn	
-
-
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_100m_fpga
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_50m_fpga
-	set_location_assignment PIN_Y26 -to clk_100m_fpga
-	set_location_assignment PIN_K14 -to clk_50m_fpga
-
-	set_instance_assignment -name IO_STANDARD "1.5 V" -to clk_top1
-	set_instance_assignment -name IO_STANDARD "1.5 V" -to clk_bot1
-	set_location_assignment PIN_AA16 -to clk_top1
-	set_location_assignment PIN_AF14 -to clk_bot1	
-
-#	set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cpu_resetn	
-#	set_location_assignment PIN_AD27 -to cpu_resetn
-	
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_a
-	set_location_assignment PIN_AJ14 -to ddr3_fpga_a[0]
-	set_location_assignment PIN_AK14 -to ddr3_fpga_a[1]
-	set_location_assignment PIN_AH12 -to ddr3_fpga_a[2]
-	set_location_assignment PIN_AJ12 -to ddr3_fpga_a[3]
-	set_location_assignment PIN_AG15 -to ddr3_fpga_a[4]
-	set_location_assignment PIN_AH15 -to ddr3_fpga_a[5]
-	set_location_assignment PIN_AK12 -to ddr3_fpga_a[6]
-	set_location_assignment PIN_AK13 -to ddr3_fpga_a[7]
-	set_location_assignment PIN_AH13 -to ddr3_fpga_a[8]
-	set_location_assignment PIN_AH14 -to ddr3_fpga_a[9]
-	set_location_assignment PIN_AJ9 -to ddr3_fpga_a[10]
-	set_location_assignment PIN_AK9 -to ddr3_fpga_a[11]
-	set_location_assignment PIN_AK7 -to ddr3_fpga_a[12]
-	set_location_assignment PIN_AK8 -to ddr3_fpga_a[13]
-	set_location_assignment PIN_AG12 -to ddr3_fpga_a[14]
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_ba
-	set_location_assignment PIN_AH10 -to ddr3_fpga_ba[0]
-	set_location_assignment PIN_AJ11 -to ddr3_fpga_ba[1]
-	set_location_assignment PIN_AK11 -to ddr3_fpga_ba[2]
-	set_location_assignment PIN_AH7 -to ddr3_fpga_casn
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_casn
-	set_location_assignment PIN_AJ21 -to ddr3_fpga_cke
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_cke
-	set_location_assignment PIN_AA15 -to ddr3_fpga_clk_n
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_clk_n
-	set_location_assignment PIN_AA14 -to ddr3_fpga_clk_p
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_clk_p
-	set_location_assignment PIN_AB15 -to ddr3_fpga_csn
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_csn
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_dm
-	set_location_assignment PIN_AH17 -to ddr3_fpga_dm[0]
-	set_location_assignment PIN_AG23 -to ddr3_fpga_dm[1]
-	set_location_assignment PIN_AK23 -to ddr3_fpga_dm[2]
-	set_location_assignment PIN_AJ27 -to ddr3_fpga_dm[3]
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_dq
-	set_location_assignment PIN_AF18 -to ddr3_fpga_dq[0]
-	set_location_assignment PIN_AE17 -to ddr3_fpga_dq[1]
-	set_location_assignment PIN_AG16 -to ddr3_fpga_dq[2]
-	set_location_assignment PIN_AF16 -to ddr3_fpga_dq[3]
-	set_location_assignment PIN_AH20 -to ddr3_fpga_dq[4]
-	set_location_assignment PIN_AG21 -to ddr3_fpga_dq[5]
-	set_location_assignment PIN_AJ16 -to ddr3_fpga_dq[6]
-	set_location_assignment PIN_AH18 -to ddr3_fpga_dq[7]
-	set_location_assignment PIN_AK18 -to ddr3_fpga_dq[8]
-	set_location_assignment PIN_AJ17 -to ddr3_fpga_dq[9]
-	set_location_assignment PIN_AG18 -to ddr3_fpga_dq[10]
-	set_location_assignment PIN_AK19 -to ddr3_fpga_dq[11]
-	set_location_assignment PIN_AG20 -to ddr3_fpga_dq[12]
-	set_location_assignment PIN_AF19 -to ddr3_fpga_dq[13]
-	set_location_assignment PIN_AJ20 -to ddr3_fpga_dq[14]
-	set_location_assignment PIN_AH24 -to ddr3_fpga_dq[15]
-	set_location_assignment PIN_AE19 -to ddr3_fpga_dq[16]
-	set_location_assignment PIN_AE18 -to ddr3_fpga_dq[17]
-	set_location_assignment PIN_AG22 -to ddr3_fpga_dq[18]
-	set_location_assignment PIN_AK22 -to ddr3_fpga_dq[19]
-	set_location_assignment PIN_AF21 -to ddr3_fpga_dq[20]
-	set_location_assignment PIN_AF20 -to ddr3_fpga_dq[21]
-	set_location_assignment PIN_AH23 -to ddr3_fpga_dq[22]
-	set_location_assignment PIN_AK24 -to ddr3_fpga_dq[23]
-	set_location_assignment PIN_AF24 -to ddr3_fpga_dq[24]
-	set_location_assignment PIN_AF23 -to ddr3_fpga_dq[25]
-	set_location_assignment PIN_AJ24 -to ddr3_fpga_dq[26]
-	set_location_assignment PIN_AK26 -to ddr3_fpga_dq[27]
-	set_location_assignment PIN_AE23 -to ddr3_fpga_dq[28]
-	set_location_assignment PIN_AE22 -to ddr3_fpga_dq[29]
-	set_location_assignment PIN_AG25 -to ddr3_fpga_dq[30]
-	set_location_assignment PIN_AK27 -to ddr3_fpga_dq[31]
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_dqs_n
-	set_location_assignment PIN_W16 -to ddr3_fpga_dqs_n[0]
-	set_location_assignment PIN_W17 -to ddr3_fpga_dqs_n[1]
-	set_location_assignment PIN_AA18 -to ddr3_fpga_dqs_n[2]
-	set_location_assignment PIN_AD19 -to ddr3_fpga_dqs_n[3]
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_dqs_p
-	set_location_assignment PIN_V16 -to ddr3_fpga_dqs_p[0]
-	set_location_assignment PIN_V17 -to ddr3_fpga_dqs_p[1]
-	set_location_assignment PIN_Y17 -to ddr3_fpga_dqs_p[2]
-	set_location_assignment PIN_AC20 -to ddr3_fpga_dqs_p[3]
-	set_location_assignment PIN_AE16 -to ddr3_fpga_odt
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_odt
-	set_location_assignment PIN_AH8 -to ddr3_fpga_rasn
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_rasn
-	set_location_assignment PIN_AK21 -to ddr3_fpga_resetn
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_resetn
-	set_location_assignment PIN_AJ6 -to ddr3_fpga_wen
-	set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_fpga_wen
-	set_location_assignment PIN_AG17 -to ddr3_fpga_rzq
-	set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_fpga_rzq
-	
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_b[0]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_b[1]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_b[2]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_b[3]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_b[4]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_b[5]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_b[6]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_b[7]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_blank_n
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_clk
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_g[0]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_g[1]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_g[2]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_g[3]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_g[4]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_g[5]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_g[6]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_g[7]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_hs
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_r[0]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_r[1]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_r[2]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_r[3]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_r[4]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_r[5]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_r[6]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_r[7]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to  -to vga_sync_n
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to -to vga_vs 	
-	
-	set_location_assignment PIN_AE28 -to vga_b[0]
-	set_location_assignment PIN_Y23 -to vga_b[1]
-	set_location_assignment PIN_Y24 -to vga_b[2]
-	set_location_assignment PIN_AG28 -to vga_b[3]
-	set_location_assignment PIN_AF28 -to vga_b[4]
-	set_location_assignment PIN_V23 -to vga_b[5]
-	set_location_assignment PIN_W24 -to vga_b[6]
-	set_location_assignment PIN_AF29 -to vga_b[7]
-	set_location_assignment PIN_AH3 -to vga_blank_n
-	set_location_assignment PIN_W20 -to vga_clk
-	set_location_assignment PIN_Y21 -to vga_g[0]
-	set_location_assignment PIN_AA25 -to vga_g[1]
-	set_location_assignment PIN_AB26 -to vga_g[2]
-	set_location_assignment PIN_AB22 -to vga_g[3]
-	set_location_assignment PIN_AB23 -to vga_g[4]
-	set_location_assignment PIN_AA24 -to vga_g[5]
-	set_location_assignment PIN_AB25 -to vga_g[6]
-	set_location_assignment PIN_AE27 -to vga_g[7]
-	set_location_assignment PIN_AD12 -to vga_hs
-	set_location_assignment PIN_AA12 -to vga_r[0]
-	set_location_assignment PIN_AB12 -to vga_r[1]
-	set_location_assignment PIN_AF6 -to vga_r[2]
-	set_location_assignment PIN_AG6 -to vga_r[3]
-	set_location_assignment PIN_AG5 -to vga_r[4]
-	set_location_assignment PIN_AH5 -to vga_r[5]
-	set_location_assignment PIN_AJ1 -to vga_r[6]
-	set_location_assignment PIN_AJ2 -to vga_r[7]
-	set_location_assignment PIN_AG2 -to vga_sync_n
-	set_location_assignment PIN_AC12 -to vga_vs 
-
-	set_location_assignment PIN_AC27 -to aud_adcdat
-	set_location_assignment PIN_AG30 -to aud_adclrck
-	set_location_assignment PIN_AE7 -to aud_bclk
-	set_location_assignment PIN_AG3 -to aud_dacdat
-	set_location_assignment PIN_AH4 -to aud_daclrck
-	set_location_assignment PIN_AH30 -to aud_i2c_sclk
-	set_location_assignment PIN_AF30 -to aud_i2c_sdat
-	set_location_assignment PIN_AD26 -to aud_mute
-	set_location_assignment PIN_AC9 -to aud_xck
-
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to fan_ctrl	
-	set_location_assignment PIN_AG27 -to fan_ctrl
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to irda_rxd	
-	set_location_assignment PIN_AH2 -to irda_rxd
-	
-	
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkin_n[1]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkin_n[2]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkin_p[1]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkin_p[2]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkout_n[1]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkout_n[2]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkout_p[1]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clkout_p[2]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clk_in0
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_clk_out0	
-	
-	set_instance_assignment -name IO_STANDARD HCSL -to hsmc_ref_clk_n
-	set_instance_assignment -name IO_STANDARD HCSL -to hsmc_ref_clk_p
-	
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[0]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[1]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[2]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[3]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[4]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[5]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[6]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[7]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[8]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[9]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[10]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[11]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[12]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[13]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[14]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[15]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_n[16]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[0]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[1]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[2]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[3]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[4]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[5]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[6]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[7]
-	set_instance_assignment -name IO_STANDARD "2.5 V"-to hsmc_rx_p[8]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[9]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[10]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[11]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[12]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[13]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[14]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[15]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_rx_p[16]	
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_scl
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_sda	
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[0]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[1]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[2]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[3]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[4]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[5]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[6]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[7]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[8]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[9]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[10]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[11]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[12]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[13]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[14]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[15]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_n[16]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[0]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[1]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[2]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[3]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[4]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[5]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[6]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[7]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[8]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[9]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[10]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[11]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[12]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[13]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[14]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[15]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmc_tx_p[16]	
-	
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_rx_n[0]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_rx_n[1]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_rx_n[2]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_rx_n[3]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_rx_n[4]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_rx_n[5]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_rx_n[6]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_rx_n[7]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_rx_p[0]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_rx_p[1]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_rx_p[2]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_rx_p[3]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_rx_p[4]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_rx_p[5]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_rx_p[6]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_rx_p[7]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_tx_n[0]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_tx_n[1]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_tx_n[2]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_tx_n[3]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_tx_n[4]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_tx_n[5]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_tx_n[6]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_tx_n[7]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_tx_p[0]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_tx_p[1]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_tx_p[2]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_tx_p[3]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_tx_p[4]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_tx_p[5]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_tx_p[6]
-	set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to hsmc_gxb_tx_p[7]
-
-	set_location_assignment PIN_AB27 -to hsmc_clkin_n[1]
-	set_location_assignment PIN_AA26 -to hsmc_clkin_p[1]
-	set_location_assignment PIN_G15 -to hsmc_clkin_n[2]
-	set_location_assignment PIN_H15 -to hsmc_clkin_p[2]
-	set_location_assignment PIN_E6 -to hsmc_clkout_n[1]
-	set_location_assignment PIN_E7 -to hsmc_clkout_p[1]
-	set_location_assignment PIN_A10 -to hsmc_clkout_n[2]
-	set_location_assignment PIN_A11 -to hsmc_clkout_p[2]
-	set_location_assignment PIN_J14 -to hsmc_clk_in0
-	set_location_assignment PIN_AD29 -to hsmc_clk_out0
-
-	
-	set_location_assignment PIN_AE1 -to hsmc_gxb_rx_n[0]
-	set_location_assignment PIN_AC1 -to hsmc_gxb_rx_n[1]
-	set_location_assignment PIN_AA1 -to hsmc_gxb_rx_n[2]
-	set_location_assignment PIN_W1 -to hsmc_gxb_rx_n[3]
-	set_location_assignment PIN_U1 -to hsmc_gxb_rx_n[4]
-	set_location_assignment PIN_R1 -to hsmc_gxb_rx_n[5]
-	set_location_assignment PIN_N1 -to hsmc_gxb_rx_n[6]
-	set_location_assignment PIN_L1 -to hsmc_gxb_rx_n[7]
-	set_location_assignment PIN_AE2 -to hsmc_gxb_rx_p[0]
-	set_location_assignment PIN_AC2 -to hsmc_gxb_rx_p[1]
-	set_location_assignment PIN_AA2 -to hsmc_gxb_rx_p[2]
-	set_location_assignment PIN_W2 -to hsmc_gxb_rx_p[3]
-	set_location_assignment PIN_U2 -to hsmc_gxb_rx_p[4]
-	set_location_assignment PIN_R2 -to hsmc_gxb_rx_p[5]
-	set_location_assignment PIN_N2 -to hsmc_gxb_rx_p[6]
-	set_location_assignment PIN_L2 -to hsmc_gxb_rx_p[7]
-	set_location_assignment PIN_AD3 -to hsmc_gxb_tx_n[0]
-	set_location_assignment PIN_AB3 -to hsmc_gxb_tx_n[1]
-	set_location_assignment PIN_Y3 -to hsmc_gxb_tx_n[2]
-	set_location_assignment PIN_V3 -to hsmc_gxb_tx_n[3]
-	set_location_assignment PIN_T3 -to hsmc_gxb_tx_n[4]
-	set_location_assignment PIN_P3 -to hsmc_gxb_tx_n[5]
-	set_location_assignment PIN_M3 -to hsmc_gxb_tx_n[6]
-	set_location_assignment PIN_K3 -to hsmc_gxb_tx_n[7]
-	set_location_assignment PIN_AD4 -to hsmc_gxb_tx_p[0]
-	set_location_assignment PIN_AB4 -to hsmc_gxb_tx_p[1]
-	set_location_assignment PIN_Y4 -to hsmc_gxb_tx_p[2]
-	set_location_assignment PIN_V4 -to hsmc_gxb_tx_p[3]
-	set_location_assignment PIN_T4 -to hsmc_gxb_tx_p[4]
-	set_location_assignment PIN_P4 -to hsmc_gxb_tx_p[5]
-	set_location_assignment PIN_M4 -to hsmc_gxb_tx_p[6]
-	set_location_assignment PIN_K4 -to hsmc_gxb_tx_p[7]
-	set_location_assignment PIN_W7 -to hsmc_ref_clk_n
-	set_location_assignment PIN_W8 -to hsmc_ref_clk_p
-
-	set_location_assignment PIN_G12 -to hsmc_rx_p[0]
-	set_location_assignment PIN_G11 -to hsmc_rx_n[0]	
-	set_location_assignment PIN_K12 -to hsmc_rx_p[1]
-	set_location_assignment PIN_J12 -to hsmc_rx_n[1]	
-	set_location_assignment PIN_G10 -to hsmc_rx_p[2]
-	set_location_assignment PIN_F10 -to hsmc_rx_n[2]			
-	set_location_assignment PIN_J10 -to hsmc_rx_p[3]	
-	set_location_assignment PIN_J9 -to hsmc_rx_n[3]	
-	set_location_assignment PIN_K7 -to hsmc_rx_p[4]		
-	set_location_assignment PIN_K8 -to hsmc_rx_n[4]	
-	set_location_assignment PIN_J7 -to hsmc_rx_p[5]		
-	set_location_assignment PIN_H7 -to hsmc_rx_n[5]	
-	set_location_assignment PIN_H8 -to hsmc_rx_p[6]
-	set_location_assignment PIN_G8 -to hsmc_rx_n[6]	
-	set_location_assignment PIN_F9 -to hsmc_rx_p[7]
-	set_location_assignment PIN_F8 -to hsmc_rx_n[7]
-	set_location_assignment PIN_F11 -to hsmc_rx_p[8]
-	set_location_assignment PIN_E11 -to hsmc_rx_n[8]
-	set_location_assignment PIN_B6 -to hsmc_rx_p[9]	
-	set_location_assignment PIN_B5 -to hsmc_rx_n[9]	
-	set_location_assignment PIN_E9 -to hsmc_rx_p[10]	
-	set_location_assignment PIN_D9 -to hsmc_rx_n[10]		
-	set_location_assignment PIN_E12 -to hsmc_rx_p[11]	
-	set_location_assignment PIN_D12 -to hsmc_rx_n[11]		
-	set_location_assignment PIN_D11 -to hsmc_rx_p[12]	
-	set_location_assignment PIN_D10 -to hsmc_rx_n[12]	
-	set_location_assignment PIN_C13 -to hsmc_rx_p[13]	
-	set_location_assignment PIN_B12 -to hsmc_rx_n[13]	
-	set_location_assignment PIN_F13 -to hsmc_rx_p[14]	
-	set_location_assignment PIN_E13 -to hsmc_rx_n[14]	
-	set_location_assignment PIN_H14 -to hsmc_rx_p[15]	
-	set_location_assignment PIN_G13 -to hsmc_rx_n[15]
-	set_location_assignment PIN_F15 -to hsmc_rx_p[16]	
-	set_location_assignment PIN_F14 -to hsmc_rx_n[16]	
-	
-	
-	set_location_assignment PIN_A9 -to hsmc_tx_p[0]
-	set_location_assignment PIN_A8 -to hsmc_tx_n[0]	
-	set_location_assignment PIN_E8 -to hsmc_tx_p[1]
-	set_location_assignment PIN_D7 -to hsmc_tx_n[1]	
-	set_location_assignment PIN_G7 -to hsmc_tx_p[2]
-	set_location_assignment PIN_F6 -to hsmc_tx_n[2]	
-	set_location_assignment PIN_D6 -to hsmc_tx_p[3]	
-	set_location_assignment PIN_C5 -to hsmc_tx_n[3]		
-	set_location_assignment PIN_D5 -to hsmc_tx_p[4]	
-	set_location_assignment PIN_C4 -to hsmc_tx_n[4]	
-	set_location_assignment PIN_E3 -to hsmc_tx_p[5]	
-	set_location_assignment PIN_E2 -to hsmc_tx_n[5]
-	set_location_assignment PIN_E4 -to hsmc_tx_p[6]
-	set_location_assignment PIN_D4 -to hsmc_tx_n[6]
-	set_location_assignment PIN_C3 -to hsmc_tx_p[7]	
-	set_location_assignment PIN_B3 -to hsmc_tx_n[7]
-	set_location_assignment PIN_D1 -to hsmc_tx_n[8]
-	set_location_assignment PIN_E1 -to hsmc_tx_p[8]
-	set_location_assignment PIN_D2 -to hsmc_tx_p[9]
-	set_location_assignment PIN_C2 -to hsmc_tx_n[9]	
-	set_location_assignment PIN_B1 -to hsmc_tx_p[10]
-	set_location_assignment PIN_B2 -to hsmc_tx_n[10]
-	set_location_assignment PIN_A4 -to hsmc_tx_p[11]
-	set_location_assignment PIN_A3 -to hsmc_tx_n[11]		
-	set_location_assignment PIN_A6 -to hsmc_tx_p[12]
-	set_location_assignment PIN_A5 -to hsmc_tx_n[12]	
-	set_location_assignment PIN_C7 -to hsmc_tx_p[13]
-	set_location_assignment PIN_B7 -to hsmc_tx_n[13]		
-	set_location_assignment PIN_C8 -to hsmc_tx_p[14]
-	set_location_assignment PIN_B8 -to hsmc_tx_n[14]	
-	set_location_assignment PIN_C12 -to hsmc_tx_p[15]
-	set_location_assignment PIN_B11 -to hsmc_tx_n[15]		
-	set_location_assignment PIN_B13 -to hsmc_tx_p[16]
-	set_location_assignment PIN_A13 -to hsmc_tx_n[16]		
-
-	set_location_assignment PIN_C10 -to hsmc_d[0]
-	set_location_assignment PIN_C9 -to hsmc_d[2]
-	set_location_assignment PIN_H13 -to hsmc_d[1]
-	set_location_assignment PIN_H12 -to hsmc_d[3]
-
-	set_location_assignment PIN_AA28 -to hsmc_scl
-	set_location_assignment PIN_AE29 -to hsmc_sda
-	
-	set_location_assignment PIN_W25 -to user_dipsw_fpga[0]
-	set_location_assignment PIN_V25 -to user_dipsw_fpga[1]
-	set_location_assignment PIN_AC28 -to user_dipsw_fpga[2]
-	set_location_assignment PIN_AC29 -to user_dipsw_fpga[3]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to user_dipsw_fpga[0]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to user_dipsw_fpga[1]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to user_dipsw_fpga[2]
-	set_instance_assignment -name IO_STANDARD "2.5 V" -to user_dipsw_fpga[3]
-	set_location_assignment PIN_AF10 -to user_led_fpga[0]
-	set_location_assignment PIN_AD10 -to user_led_fpga[1]
-	set_location_assignment PIN_AE11 -to user_led_fpga[2]
-	set_location_assignment PIN_AD7 -to user_led_fpga[3]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_led_fpga[0]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_led_fpga[1]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_led_fpga[2]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_led_fpga[3]
-	set_location_assignment PIN_AE9 -to user_pb_fpga[0]
-	set_location_assignment PIN_AE12 -to user_pb_fpga[1]
-	set_location_assignment PIN_AD9 -to user_pb_fpga[2]
-	set_location_assignment PIN_AD11 -to user_pb_fpga[3]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_pb_fpga[0]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_pb_fpga[1]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_pb_fpga[0]
-	set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_pb_fpga[1]
-
-
-	# Commit assignments
-	export_assignments
-
-	# Close project
-	if {$need_to_close_project} {
-		project_close
-	}
-}
diff --git a/HW/QuartusProjects/SoCkit_GHRD/top/config_soc.v b/HW/QuartusProjects/SoCkit_GHRD/top/config_soc.v
deleted file mode 100755
index 8b8a2165..00000000
--- a/HW/QuartusProjects/SoCkit_GHRD/top/config_soc.v
+++ /dev/null
@@ -1,22 +0,0 @@
-// Comment out any `define's below to remove top level interfaces/components that are not required
-// Setting 'define to false does not remove the interface/component from the top level
-
-`define user_peripheral true
-`define irda true
-//`define NO_OF_SDI_IO 2
-//`define sdi_in_1 true
-//`define sdi_in_2 true
-//`define sdi_out_1 true
-//`define sdi_out_2 true
-//`define temp_sense true 
-//`define dvi_in_1 true
-//`define hdmi_out true
-//`define hsma true
-`define htg true
-//`define hsmb true
-//`define bitec_dvi true
-`define ddr3 true
-//`define audio true
-//`define vga	true
-//`define audio true
-//`define HSMC_XCVR true
diff --git a/HW/QuartusProjects/SoCkit_GHRD/top/ghrd_top.v b/HW/QuartusProjects/SoCkit_GHRD/top/ghrd_top.v
deleted file mode 100755
index 0e4e15f8..00000000
--- a/HW/QuartusProjects/SoCkit_GHRD/top/ghrd_top.v
+++ /dev/null
@@ -1,546 +0,0 @@
-// ============================================================================
-// Copyright (c) 2013 by Arrow Electronics, Inc.
-// ============================================================================
-//
-// Permission:
-//
-//   Arrow grants permission to use and modify this code for use
-//   in synthesis for all Arrow Development Boards. Other use of this code,
-//	  including the selling ,duplication, or modification of any portion is
-//   strictly prohibited.
-//
-// Disclaimer:
-//
-//   This VHDL/Verilog or C/C++ source code is intended as a design reference
-//   which illustrates how these types of functions can be implemented.
-//   It is the user's responsibility to verify their design for
-//   consistency and functionality through the use of formal
-//   verification methods.  Arrow provides no warranty regarding the use
-//   or functionality of this code.
-//
-// ============================================================================
-//
-//  Arrow Technologies Inc
-//  Englewood, CO. USA
-//
-//
-//                     web: http://www.Arrow.com/
-//
-//
-// ============================================================================
-// Date:  Mon Mar 27 13:20:22 2013
-// ============================================================================
-//
-// ============================================================================
-// Revision Change list:
-// ============================================================================
-//
-// 								soc_system_20130323
-//
-//	Description: Connected hps_fpga_reset_n output to verilog top level reset.
-//					 Added button debounce circuitry. Bypassed at present. Debug required.
-//					 Used clk_bot1. clk_50m_fpga does not work. Debug required.
-//
-//
-// 								soc_system_20130408
-//
-//	Description: Changed vga_sync_n & vga_blank_n from inputs to outputs
-//					 Changed ddr3_fpga_rasn, ddr3_fpga_resetn, ddr3_fpga_wen from
-//					 inputs to outputs.
-//
-//
-// 								soc_system_20130411
-//
-//	Description: Removed debounce circuit. External 74HC245 performs pushbutton
-//					 debounce.
-//
-//
-// 								soc_system_20131109
-//
-//	Description: Upgrade to release 13.1
-//					 Quartus: Changed top level to ghrd_top
-//					 Quartus: Added Source/Probe Megawizard instances for f2h cold/warm/debug resets
-//					 Quartus: Added system trace connections
-//					 Qsys: Changed naming for jtag_master from master_secure to hps_only_master
-//					 Qsys: Changed naming for jtag_master from master_non_sec to fpga_only_master
-//					 Qsys: hps_component. Enabled input ports for f2h cold/warm/debug resets
-//					 Qsys: hps_component. Enabled system trace ports
-//
-//
-// 								soc_system_20140711
-//
-//	Description: Upgrade to release 14.0
-//					 Quartus: Changed device to 5CSXFC6D6F31C6
-//					 Qsys: hps_component. Enabled f2dram_0, 256 bit bidirectional Avalon-MM FPGA to SDRAM interface
-//					 Qsys: Added f2sdram_only jtag_master
-//
-//
-// 								soc_system_20141225
-//
-//	Description: Upgrade to release 14.1
-//					 Quartus:
-//					 Qsys: Added a mm_bridge between the lw_axi_master and all fpga peripherals
-//					 Qsys: hps_component / hps_clocks_tab. qspi clock freq changed to 333MHz
-//							 from 400MHz
-//					 Qsys: hps_component / hps_clocks_tab. configuration / hps to fpga user 0
-//							 clock frequency changed to 123.333333MHz from 100MHz
-//
-//
-// 								soc_system_20150901
-//
-//	Description: Upgrade to release 15.0
-//					 Quartus:
-//					 Qsys:
-//
-//
-// 								soc_system_20160212
-//
-//	Description: Upgrade to release 15.1
-//					 Quartus:
-//					 Qsys:
-//
-// ============================================================================
-// Qsys System :
-// ============================================================================
-//
-// Description:
-//
-//		To view the Qsys system open Qsys and selected soc_system.qsys.
-//		This system mimics the Altera Development kit GHRD design. The system
-//		console script, "ghrd_sc_script.tcl", which can be found in this projects
-//		root directory, is identical to the Altera script and will implement all
-//		the functionality described in the GHRD Users Guide. All software examples
-//		shown in the users guide will also be fully functional on the Arrow SoCKIT.
-//
-//
-// ============================================================================
-
-`include "top/config_soc.v"
-
-module ghrd_top (
-
-		output wire [14:0] memory_mem_a,
-		output wire [2:0]  memory_mem_ba,
-		output wire        memory_mem_ck,
-		output wire        memory_mem_ck_n,
-		output wire        memory_mem_cke,
-		output wire        memory_mem_cs_n,
-		output wire        memory_mem_ras_n,
-		output wire        memory_mem_cas_n,
-		output wire        memory_mem_we_n,
-		output wire        memory_mem_reset_n,
-		inout  wire [31:0] memory_mem_dq,
-		inout  wire [3:0]  memory_mem_dqs,
-		inout  wire [3:0]  memory_mem_dqs_n,
-		output wire        memory_mem_odt,
-		output wire [3:0]  memory_mem_dm,
-		input  wire        memory_oct_rzqin,
-		output wire        hps_emac1_TX_CLK,
-		output wire        hps_emac1_TXD0,
-		output wire        hps_emac1_TXD1,
-		output wire        hps_emac1_TXD2,
-		output wire        hps_emac1_TXD3,
-		input  wire        hps_emac1_RXD0,
-		inout  wire        hps_emac1_MDIO,
-		output wire        hps_emac1_MDC,
-		input  wire        hps_emac1_RX_CTL,
-		output wire        hps_emac1_TX_CTL,
-		input  wire        hps_emac1_RX_CLK,
-		input  wire        hps_emac1_RXD1,
-		input  wire        hps_emac1_RXD2,
-		input  wire        hps_emac1_RXD3,
-		inout  wire        hps_qspi_IO0,
-		inout  wire        hps_qspi_IO1,
-		inout  wire        hps_qspi_IO2,
-		inout  wire        hps_qspi_IO3,
-		output wire        hps_qspi_SS0,
-		output wire        hps_qspi_CLK,
-		inout  wire        hps_sdio_CMD,
-		inout  wire        hps_sdio_D0,
-		inout  wire        hps_sdio_D1,
-		output wire        hps_sdio_CLK,
-		inout  wire        hps_sdio_D2,
-		inout  wire        hps_sdio_D3,
-		inout  wire        hps_usb1_D0,
-		inout  wire        hps_usb1_D1,
-		inout  wire        hps_usb1_D2,
-		inout  wire        hps_usb1_D3,
-		inout  wire        hps_usb1_D4,
-		inout  wire        hps_usb1_D5,
-		inout  wire        hps_usb1_D6,
-		inout  wire        hps_usb1_D7,
-		input  wire        hps_usb1_CLK,
-		output wire        hps_usb1_STP,
-		input  wire        hps_usb1_DIR,
-		input  wire        hps_usb1_NXT,
-		output wire        hps_spim0_CLK,
-		output wire        hps_spim0_MOSI,
-		input  wire        hps_spim0_MISO,
-		output wire        hps_spim0_SS0,
-		output wire        hps_spim1_CLK,
-		output wire        hps_spim1_MOSI,
-		input  wire        hps_spim1_MISO,
-		output wire        hps_spim1_SS0,
-		input  wire        hps_uart0_RX,
-		output wire        hps_uart0_TX,
-		inout  wire        hps_i2c1_SDA,
-		inout  wire        hps_i2c1_SCL,
-		inout  wire        hps_gpio_GPIO00,
-		inout  wire        hps_gpio_GPIO09,
-		inout  wire        hps_gpio_GPIO35,
-		inout  wire        hps_gpio_GPIO48,
-		inout  wire        hps_gpio_GPIO53,
-		inout  wire        hps_gpio_GPIO54,
-		inout  wire        hps_gpio_GPIO55,
-		inout  wire        hps_gpio_GPIO56,
-		inout  wire        hps_gpio_GPIO61,
-		inout  wire        hps_gpio_GPIO62,
-
-
-////////////////////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////////////////////
-////////////////////		FPGA Interface			////////////////////////////
-////////////////////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////////////////////
-
-	//FPGA-GPLL-CLK------------------------//X pins
-   input          clk_100m_fpga,       // 2.5V    //50 MHz ajustable from SiLabs SI5338
-   input          clk_50m_fpga,        // 2.5V    //50 MHz ajustable from SiLabs SI5338
-	input          clk_top1,            // 2.5V    //50 MHz ajustable from SiLabs SI5338
-   input          clk_bot1,            // 1.5V    //50 MHz ajustable from SiLabs SI5338
-	input          fpga_resetn,         // 2.5V    //FPGA Reset Pushbutton
-
-	//////////////////// SiLabs Clock Generator I/F 	///////////////////
-   output   wire  clk_i2c_sclk,        // I2C Clock
-   inout    wire  clk_i2c_sdat,        // I2C Data
-
-`ifdef user_peripheral
-	//FPGA-User-IO-------------------------//14 pins //--------------------------
- 	input	 [3:0]   user_dipsw_fpga,     //
-	output [3:0]   user_led_fpga,       //
-	input	 [3:0]   user_pb_fpga,        //
-  	input  	wire  irda_rxd,				// IRDA Receive LED
-  	output  	wire  fan_ctrl,				// control for fan
-`endif
-
-`ifdef ddr3
-//FPGA-DDR3-400Mx32--------------------//74 pins //--------------------------
-   output [14:0]  ddr3_fpga_a,         // SSTL15  //Address
-   output [2:0]   ddr3_fpga_ba,        // SSTL15  //Bank Address
-	output         ddr3_fpga_casn,      // SSTL15  //Column Address Strobe
-	output         ddr3_fpga_cke,       // SSTL15  //Clock Enable
-	output         ddr3_fpga_clk_n,     // SSTL15  //Diff Clock - Neg
-	output         ddr3_fpga_clk_p,     // SSTL15  //Diff Clock - Pos
-   output         ddr3_fpga_csn,       // SSTL15  //Chip Select
-   output [3:0]   ddr3_fpga_dm,        // SSTL15  //Data Write Mask
-   inout  [31:0]  ddr3_fpga_dq,        // SSTL15  //Data Bus
-   inout  [3:0]   ddr3_fpga_dqs_n,     // SSTL15  //Diff Data Strobe - Neg
-   inout  [3:0]   ddr3_fpga_dqs_p,     // SSTL15  //Diff Data Strobe - Pos
-   output         ddr3_fpga_odt,       // SSTL15  //On-Die Termination Enable
-   output          ddr3_fpga_rasn,     // SSTL15  //Row Address Strobe
-   output          ddr3_fpga_resetn,   // SSTL15  //Reset
-   output          ddr3_fpga_wen,      // SSTL15  //Write Enable
-	input          ddr3_fpga_rzq,       // OCT_rzqin //On-die termination enable
-//   input          oct_rdn,        	// SSTL15    //On-die termination enable
-//   input          oct_rup,       		// SSTL15    //On-die termination enable
-`endif
-
-`ifdef temp_sense
- 		//////////////////// 	Temp. Sensor I/F 	////////////////////
-		// 							SPI interface								//
-   output   wire  temp_cs_n,				// Chip Select
-   output   wire  temp_sclk,       		// Slave Clock
-   output   wire  temp_mosi,				// Data Out
-   input    wire  temp_miso,				// Data In
-`endif
-
-`ifdef vga
-		////////////////////	VIDEO 	 		////////////////////
-   output 	wire  vga_clk,					// Video Clock
-   output 	wire  vga_hs,					// Horizontal Synch
-   output 	wire  vga_vs,					// Vertical Synch
-   output   wire  [7:0] vga_r,			// Red
-   output   wire  [7:0] vga_g,			// Green
-   output   wire  [7:0] vga_b,			// Blue
-   output 	wire  vga_blank_n,			// Composite Blank Control
-   output 	wire  vga_sync_n,				// Composite Synch Control
-`endif
-
-`ifdef audio
-	////////////////////	AUDIO 	 		////////////////////
-   input 	wire  aud_adcdat,				// ADC Serial Data or I2C_SCLK
-   input 	wire  aud_adclrck, 			// FDDR3e clock
-   input 	wire  aud_bclk,				// Bit Clock
-   output 	wire  aud_dacdat,				// DAC Serial Data
-   inout 	wire  aud_daclrck,			// FDDR3e Clock
-	output   wire  aud_i2c_sclk,
-	inout    wire  aud_i2c_sdat,
-	output   wire  aud_mute,
-	output   wire  aud_xck,
-`endif
-
-`ifdef hsma
-//HSMC-Port-A--------------------------////--------------------------
-	input                         [2:1]        hsmc_clkin_n,
-	input                         [2:1]        hsmc_clkin_p,
-	output                        [2:1]        hsmc_clkout_n,
-	output                        [2:1]        hsmc_clkout_p,
-	input                                      hsmc_clk_in0,
-	output                                     hsmc_clk_out0,
-	inout                         [3:0]        hsmc_d,
-`ifdef HSMC_XCVR
-//	input                         [7:0]        hsmc_gxb_rx_n,
-	input                         [7:0]        hsmc_gxb_rx_p,
-//	output                        [7:0]        hsmc_gxb_tx_n,
-	output                        [7:0]        hsmc_gxb_tx_p,
-//	input                                      hsmc_ref_clk_n,
-	input                                      hsmc_ref_clk_p,
-`endif
-	input                         [16:0]       hsmc_rx_n,
-	input                         [16:0]       hsmc_rx_p,
-	output                                     hsmc_scl,
-	inout                                      hsmc_sda,
-	output                         [16:0]       hsmc_tx_n,
-	output                         [16:0]       hsmc_tx_p
- `endif
-
-`ifdef htg 
-	inout                         [35:0]       GPIO0,
-	inout                         [35:0]       GPIO1,
-	input                                      hsmc_rx_n8,
-	input                                      hsmc_rx_p8,
-	output                                     hsmc_tx_n8,
-	output                                     hsmc_tx_p8,
-	inout                         [3:0]        hsmc_d,
-	input                                      hsmc_clk_in0,
-	output                                     hsmc_clk_out0,
-	inout                                      hsmc_sda,
-	output                                     hsmc_scl
-
-`endif
- 
- 	//////////////////// QSPI Flash I/F 	///////////////////
-//   inout   wire  [3:0] fpga_epqc_data,     // Flash Data
-//   output  wire  fpga_epqc_dclk,           // Data Clock
-//   output  wire  fpga_epqc_ncso            // Chip Select
-
-);
-
-// internal wires and registers declaration
-  wire [3:0]  fpga_led_internal;
-  wire        hps_fpga_reset_n;
-  wire [2:0]  hps_reset_req;
-  wire        hps_cold_reset;
-  wire        hps_warm_reset;
-  wire        hps_debug_reset;
-  wire [27:0] stm_hw_events;
-
-
-// connection of internal logics
-//  assign user_led_fpga = ~fpga_led_internal;
-  assign user_led_fpga = fpga_led_internal;
-  assign stm_hw_events    = {{18{1'b0}}, user_dipsw_fpga, fpga_led_internal, user_pb_fpga};
-
-//  assign hsmc_tx_p = (user_dipsw_fpga[0]) ? 17'b0 : 17'h1FFFF;
-
-    soc_system u0 (
-        .clk_clk                               (clk_bot1),
-        .reset_reset_n                         (hps_fpga_reset_n),
-        .memory_mem_a                          (memory_mem_a),
-        .memory_mem_ba                         (memory_mem_ba),
-        .memory_mem_ck                         (memory_mem_ck),
-        .memory_mem_ck_n                       (memory_mem_ck_n),
-        .memory_mem_cke                        (memory_mem_cke),
-        .memory_mem_cs_n                       (memory_mem_cs_n),
-        .memory_mem_ras_n                      (memory_mem_ras_n),
-        .memory_mem_cas_n                      (memory_mem_cas_n),
-        .memory_mem_we_n                       (memory_mem_we_n),
-        .memory_mem_reset_n                    (memory_mem_reset_n),
-        .memory_mem_dq                         (memory_mem_dq),
-        .memory_mem_dqs                        (memory_mem_dqs),
-        .memory_mem_dqs_n                      (memory_mem_dqs_n),
-        .memory_mem_odt                        (memory_mem_odt),
-        .memory_mem_dm                         (memory_mem_dm),
-        .memory_oct_rzqin                      (memory_oct_rzqin),
-        .hps_0_hps_io_hps_io_emac1_inst_TX_CLK (hps_emac1_TX_CLK),
-        .hps_0_hps_io_hps_io_emac1_inst_TXD0   (hps_emac1_TXD0),
-        .hps_0_hps_io_hps_io_emac1_inst_TXD1   (hps_emac1_TXD1),
-        .hps_0_hps_io_hps_io_emac1_inst_TXD2   (hps_emac1_TXD2),
-        .hps_0_hps_io_hps_io_emac1_inst_TXD3   (hps_emac1_TXD3),
-        .hps_0_hps_io_hps_io_emac1_inst_RXD0   (hps_emac1_RXD0),
-        .hps_0_hps_io_hps_io_emac1_inst_MDIO   (hps_emac1_MDIO),
-        .hps_0_hps_io_hps_io_emac1_inst_MDC    (hps_emac1_MDC),
-        .hps_0_hps_io_hps_io_emac1_inst_RX_CTL (hps_emac1_RX_CTL),
-        .hps_0_hps_io_hps_io_emac1_inst_TX_CTL (hps_emac1_TX_CTL),
-        .hps_0_hps_io_hps_io_emac1_inst_RX_CLK (hps_emac1_RX_CLK),
-        .hps_0_hps_io_hps_io_emac1_inst_RXD1   (hps_emac1_RXD1),
-        .hps_0_hps_io_hps_io_emac1_inst_RXD2   (hps_emac1_RXD2),
-        .hps_0_hps_io_hps_io_emac1_inst_RXD3   (hps_emac1_RXD3),
-        .hps_0_hps_io_hps_io_qspi_inst_IO0     (hps_qspi_IO0),
-        .hps_0_hps_io_hps_io_qspi_inst_IO1     (hps_qspi_IO1),
-        .hps_0_hps_io_hps_io_qspi_inst_IO2     (hps_qspi_IO2),
-        .hps_0_hps_io_hps_io_qspi_inst_IO3     (hps_qspi_IO3),
-        .hps_0_hps_io_hps_io_qspi_inst_SS0     (hps_qspi_SS0),
-        .hps_0_hps_io_hps_io_qspi_inst_CLK     (hps_qspi_CLK),
-        .hps_0_hps_io_hps_io_sdio_inst_CMD     (hps_sdio_CMD),
-        .hps_0_hps_io_hps_io_sdio_inst_D0      (hps_sdio_D0),
-        .hps_0_hps_io_hps_io_sdio_inst_D1      (hps_sdio_D1),
-        .hps_0_hps_io_hps_io_sdio_inst_CLK     (hps_sdio_CLK),
-        .hps_0_hps_io_hps_io_sdio_inst_D2      (hps_sdio_D2),
-        .hps_0_hps_io_hps_io_sdio_inst_D3      (hps_sdio_D3),
-        .hps_0_hps_io_hps_io_usb1_inst_D0      (hps_usb1_D0),
-        .hps_0_hps_io_hps_io_usb1_inst_D1      (hps_usb1_D1),
-        .hps_0_hps_io_hps_io_usb1_inst_D2      (hps_usb1_D2),
-        .hps_0_hps_io_hps_io_usb1_inst_D3      (hps_usb1_D3),
-        .hps_0_hps_io_hps_io_usb1_inst_D4      (hps_usb1_D4),
-        .hps_0_hps_io_hps_io_usb1_inst_D5      (hps_usb1_D5),
-        .hps_0_hps_io_hps_io_usb1_inst_D6      (hps_usb1_D6),
-        .hps_0_hps_io_hps_io_usb1_inst_D7      (hps_usb1_D7),
-        .hps_0_hps_io_hps_io_usb1_inst_CLK     (hps_usb1_CLK),
-        .hps_0_hps_io_hps_io_usb1_inst_STP     (hps_usb1_STP),
-        .hps_0_hps_io_hps_io_usb1_inst_DIR     (hps_usb1_DIR),
-        .hps_0_hps_io_hps_io_usb1_inst_NXT     (hps_usb1_NXT),
-        .hps_0_hps_io_hps_io_spim0_inst_CLK    (hps_spim0_CLK),
-        .hps_0_hps_io_hps_io_spim0_inst_MOSI   (hps_spim0_MOSI),
-        .hps_0_hps_io_hps_io_spim0_inst_MISO   (hps_spim0_MISO),
-        .hps_0_hps_io_hps_io_spim0_inst_SS0    (hps_spim0_SS0),
-        .hps_0_hps_io_hps_io_spim1_inst_CLK    (hps_spim1_CLK),
-        .hps_0_hps_io_hps_io_spim1_inst_MOSI   (hps_spim1_MOSI),
-        .hps_0_hps_io_hps_io_spim1_inst_MISO   (hps_spim1_MISO),
-        .hps_0_hps_io_hps_io_spim1_inst_SS0    (hps_spim1_SS0),
-        .hps_0_hps_io_hps_io_uart0_inst_RX     (hps_uart0_RX),
-        .hps_0_hps_io_hps_io_uart0_inst_TX     (hps_uart0_TX),
-        .hps_0_hps_io_hps_io_i2c1_inst_SDA     (hps_i2c1_SDA),
-        .hps_0_hps_io_hps_io_i2c1_inst_SCL     (hps_i2c1_SCL),
-        .hps_0_hps_io_hps_io_gpio_inst_GPIO00  (hps_gpio_GPIO00),
-        .hps_0_hps_io_hps_io_gpio_inst_GPIO09  (hps_gpio_GPIO09),
-        .hps_0_hps_io_hps_io_gpio_inst_GPIO35  (hps_gpio_GPIO35),
-        .hps_0_hps_io_hps_io_gpio_inst_GPIO48  (hps_gpio_GPIO48),
-        .hps_0_hps_io_hps_io_gpio_inst_GPIO53  (hps_gpio_GPIO53),
-        .hps_0_hps_io_hps_io_gpio_inst_GPIO54  (hps_gpio_GPIO54),
-        .hps_0_hps_io_hps_io_gpio_inst_GPIO55  (hps_gpio_GPIO55),
-        .hps_0_hps_io_hps_io_gpio_inst_GPIO56  (hps_gpio_GPIO56),
-        .hps_0_hps_io_hps_io_gpio_inst_GPIO61  (hps_gpio_GPIO61),
-        .hps_0_hps_io_hps_io_gpio_inst_GPIO62  (hps_gpio_GPIO62),
-		  .hps_0_f2h_stm_hw_events_stm_hwevents  (stm_hw_events),
-        .led_pio_external_connection_export  (fpga_led_internal),
-		  .dipsw_pio_external_connection_export  (user_dipsw_fpga),
-        .button_pio_external_connection_export (user_pb_fpga),
-		  .hps_0_h2f_reset_reset_n               (hps_fpga_reset_n),
-		  .hps_0_f2h_cold_reset_req_reset_n      (~hps_cold_reset),
-		  .hps_0_f2h_warm_reset_req_reset_n      (~hps_warm_reset),
-		  .hps_0_f2h_debug_reset_req_reset_n     (~hps_debug_reset),
-		  .mk_io_hm2_datain                  		(hm_datao),     //   .hm2_datain
-		  .mk_io_hm2_dataout                 	  	(hm_datai),     //    hm2reg.hm2_dataout
-		  .mk_io_hm2_address                 	  	(hm_address),   //   .hm2_address
-		  .mk_io_hm2_write                   		(hm_write),     //   .hm2_write
-		  .mk_io_hm2_read                    		(hm_read),      //   .hm2_read
-		  .mk_io_hm2_chipsel            				(hm_chipsel),   //   .hm2_chipsel
-		  .clk_100mhz_out_clk                    	(hm_clk_med),   //    clk_100mhz_out.clk
-		  .clk_200mhz_out_clk                    	(hm_clk_high)   //    clk_100mhz_out.clk
-    );
-
-
-
-  parameter AddrWidth = 16;
-  parameter IOWidth = 34;
-  parameter LIOWidth = 6;
-  parameter IOPorts = 2;
-
-// hm2
-  wire [AddrWidth-3:0] 	hm_address;
-  wire [31:0] 	hm_datao;
-  wire [31:0] 	hm_datai;
-  wire       	hm_read;
-  wire 			hm_write;
-  wire [3:0]	hm_chipsel;
-  wire			hm_clk_med;
-  wire			hm_clk_high;
-  wire 			clklow_sig;
-  wire 			clkhigh_sig;
-
-  
-//  assign GPIO_1[] = ;
-
- //  assign GPIO_0[] = ;
-
-  
-// Mesa code ------------------------------------------------------//
-
-assign clklow_sig = clk_bot1;
-assign clkhigh_sig = hm_clk_high;
-assign clkmed_sig = hm_clk_med;
-
-//import work::*;
-
-wire [IOWidth-1:0] iobits_sig;
-assign GPIO0[IOWidth-1:0] = iobits_sig;
-
-wire [LIOWidth-1:0] liobits_sig;
-//assign GPIO_1[LIOWidth-1:0] = liobits_sig;
-//assign ARDUINO_IO[LIOWidth-1:0] = liobits_sig;
-assign GPIO1[LIOWidth-1:0] = liobits_sig;
-
-
-//HostMot2 #(.IOWidth(IOWidth),.IOPorts(IOPorts)) HostMot2_inst
-HostMot2 HostMot2_inst
-(
-	.ibus(hm_datai) ,	// input [buswidth-1:0] ibus_sig
-	.obus(hm_datao) ,	// output [buswidth-1:0] obus_sig
-	.addr(hm_address) ,	// input [addrwidth-1:2] addr_sig	-- addr => A(AddrWidth-1 downto 2),
-	.readstb(hm_read ) ,	// input  readstb_sig
-	.writestb(hm_write) ,	// input  writestb_sig
-
-	.clklow(clklow_sig) ,	// input  clklow_sig  				-- PCI clock --> all
-	.clkmed(clkmed_sig) ,	// input  clkmed_sig  				-- Processor clock --> sserialwa, twiddle
-	.clkhigh(clkhigh_sig) ,	// input  clkhigh_sig				-- High speed clock --> most
-//	.int(int_sig) ,	// output  int_sig							--int => LINT, ---> PCI ?
-//	.dreq(dreq_sig) ,	// output  dreq_sig
-//	.demandmode(demandmode_sig) ,	// output  demandmode_sig
-	.iobits(iobits_sig) ,	// inout [IOWidth-1:0] 				--iobits => IOBITS,-- external I/O bits
-	.liobits(liobits_sig) ,	// inout [lIOWidth-1:0] 			--liobits_sig
-//	.rates(rates_sig) ,	// output [4:0] rates_sig
-	.leds(GPIO0[35:34]) 	// output [ledcount-1:0] leds_sig		--leds => LEDS
-);
-
-
-
-// Source/Probe megawizard instance
-hps_reset hps_reset_inst (
-  .source_clk (clk_bot1),
-  .source     (hps_reset_req)
-);
-
-altera_edge_detector pulse_cold_reset (
-  .clk       (clk_bot1),
-  .rst_n     (hps_fpga_reset_n),
-  .signal_in (hps_reset_req[0]),
-  .pulse_out (hps_cold_reset)
-);
-  defparam pulse_cold_reset.PULSE_EXT = 6;
-  defparam pulse_cold_reset.EDGE_TYPE = 1;
-  defparam pulse_cold_reset.IGNORE_RST_WHILE_BUSY = 1;
-
-altera_edge_detector pulse_warm_reset (
-  .clk       (clk_bot1),
-  .rst_n     (hps_fpga_reset_n),
-  .signal_in (hps_reset_req[1]),
-  .pulse_out (hps_warm_reset)
-);
-  defparam pulse_warm_reset.PULSE_EXT = 2;
-  defparam pulse_warm_reset.EDGE_TYPE = 1;
-  defparam pulse_warm_reset.IGNORE_RST_WHILE_BUSY = 1;
-
-altera_edge_detector pulse_debug_reset (
-  .clk       (clk_bot1),
-  .rst_n     (hps_fpga_reset_n),
-  .signal_in (hps_reset_req[2]),
-  .pulse_out (hps_debug_reset)
-);
-  defparam pulse_debug_reset.PULSE_EXT = 32;
-  defparam pulse_debug_reset.EDGE_TYPE = 1;
-  defparam pulse_debug_reset.IGNORE_RST_WHILE_BUSY = 1;
-
-endmodule
diff --git a/SW/MK/configs/hm2-soc-stepper/5i25-soc.ini b/SW/MK/configs/hm2-soc-stepper/5i25-soc.ini
deleted file mode 100644
index 888f525d..00000000
--- a/SW/MK/configs/hm2-soc-stepper/5i25-soc.ini
+++ /dev/null
@@ -1,267 +0,0 @@
-
-#The hm2 sample stepper config should be pretty close. Copy an existing say 
-#5I20.ini file to 5i25-probx.ini or some such, replace the BOARD with 5i25, 
-#delete the firmware string on the loadrt hm2 line and you should be pretty 
-#close. The hm2-soc-stepper file may need some changes as well for any GPIO may not 
-#make sense with the 5i25 config
-
-[HOSTMOT2]
-DRIVER=hm2_soc
-BOARD=5i25
-CONFIG="num_encoders=0 num_pwmgens=0 num_stepgens=3"
-
-
-
-
-[EMC]
-
-# Name of machine, for use with display, etc.
-MACHINE =               HM2-Soc-Stepper
-
-# Debug level, 0 means no messages. See src/emc/nml_int/emcglb.h for others
-#DEBUG =                0x00000003
-#DEBUG =                0x00000007
-DEBUG = 0
-
-
-
-
-[DISPLAY]
-
-# Name of display program, e.g., tkemc
-#DISPLAY =               tkemc
-DISPLAY =              axis
-
-# Cycle time, in seconds, that display will sleep between polls
-CYCLE_TIME =            0.200
-
-# Path to help file
-HELP_FILE =             tklinucnc.txt
-
-# Initial display setting for position, RELATIVE or MACHINE
-POSITION_OFFSET =       RELATIVE
-
-# Initial display setting for position, COMMANDED or ACTUAL
-POSITION_FEEDBACK =     ACTUAL
-
-# Highest value that will be allowed for feed override, 1.0 = 100%
-MAX_FEED_OVERRIDE =     1.5
-
-# Prefix to be used
-PROGRAM_PREFIX = ../../nc_files/
-
-# Introductory graphic
-INTRO_GRAPHIC =         machinekit.gif
-INTRO_TIME =            5
-
-# Increments for the JOG section
-INCREMENTS = 10 1 0.1 0.01
-
-
-#PYVCP = 3D.Temps.panel.xml
-
-[FILTER]
-PROGRAM_EXTENSION = .png,.gif,.jpg Grayscale Depth Image
-PROGRAM_EXTENSION = .py Python Script
-png = image-to-gcode
-gif = image-to-gcode
-jpg = image-to-gcode
-py = python
-
-
-[TASK]
-
-# Name of task controller program, e.g., milltask
-TASK =                  milltask
-
-# Cycle time, in seconds, that task controller will sleep between polls
-CYCLE_TIME =            0.010
-
-
-
-
-[RS274NGC]
-
-# File containing interpreter variables
-PARAMETER_FILE =        hm2-soc-stepper.var
-
-
-
-
-[EMCMOT]
-
-EMCMOT =                motmod
-
-# Timeout for comm to emcmot, in seconds
-COMM_TIMEOUT =          1.0
-
-# Interval between tries to emcmot, in seconds
-COMM_WAIT =             0.010
-
-# Servo task period, in nanoseconds
-SERVO_PERIOD =          1000000
-
-
-
-
-[HAL]
-
-# The run script first uses halcmd to execute any HALFILE
-# files, and then to execute any individual HALCMD commands.
-
-# list of hal config files to run through halcmd
-# files are executed in the order in which they appear
-
-HALFILE =		hm2-soc-stepper-5i25.hal
-
-# list of halcmd commands to execute
-# commands are executed in the order in which they appear
-#HALCMD =               save neta
-
-
-
-
-[TRAJ]
-
-AXES =                  3
-COORDINATES =           X Y Z
-#HOME =                  0 0 0
-LINEAR_UNITS =          inch
-ANGULAR_UNITS =         degree
-CYCLE_TIME =            0.010
-DEFAULT_VELOCITY = 20.00
-MAX_LINEAR_VELOCITY = 200.00
-
-
-
-
-[AXIS_0]
-
-# 
-# Step timing is 40 us steplen + 40 us stepspace
-# That gives 80 us step period = 12.5 KHz step freq
-#
-# Bah, even software stepping can handle that, hm2 doesnt buy you much with
-# such slow steppers.
-#
-# Scale is 200 steps/rev * 5 revs/inch = 1000 steps/inch
-#
-# This gives a maxvel of 12.5/1 = 12.5 ips
-#
-
-
-TYPE =              LINEAR
-MAX_VELOCITY =       10
-MAX_ACCELERATION =   20
-# Set Stepgen max 20% higher than the axis
-STEPGEN_MAX_VEL =    12
-STEPGEN_MAX_ACC =    24
-
-BACKLASH =           0.000
-
-# scale is 200 steps/rev * 5 revs/inch
-SCALE =           1000
-
-MIN_LIMIT =             -10.0
-MAX_LIMIT =             10.0
-
-FERROR =     0.050
-MIN_FERROR = 0.005
-
-#HOME =                  0.000
-#HOME_OFFSET =           0.10
-#HOME_SEARCH_VEL =       0.10
-#HOME_LATCH_VEL =        -0.01
-#HOME_USE_INDEX =        YES
-#HOME_IGNORE_LIMITS =    YES
-
-# these are in nanoseconds
-DIRSETUP   =              200
-DIRHOLD    =              200
-STEPLEN    =              40000
-STEPSPACE  =              40000
-
-
-
-
-[AXIS_1]
-
-TYPE =              LINEAR
-MAX_VELOCITY =       10
-MAX_ACCELERATION =   20
-# Set Stepgen max 20% higher than the axis
-STEPGEN_MAX_VEL =    12
-STEPGEN_MAX_ACC =    24
-
-BACKLASH =           0.000
-
-SCALE = 1000
-
-MIN_LIMIT =             -10.0
-MAX_LIMIT =             10.0
-
-FERROR =     0.050
-MIN_FERROR = 0.005
-
-#HOME =                  0.000
-#HOME_OFFSET =           0.10
-#HOME_SEARCH_VEL =       0.10
-#HOME_LATCH_VEL =        -0.01
-#HOME_USE_INDEX =        YES
-#HOME_IGNORE_LIMITS =    YES
-
-# these are in nanoseconds
-DIRSETUP   =              200
-DIRHOLD    =              200
-STEPLEN    =              40000
-STEPSPACE  =              40000
-
-
-
-
-[AXIS_2]
-
-TYPE =              LINEAR
-MAX_VELOCITY =      10
-MAX_ACCELERATION =  20
-# Set Stepgen max 20% higher than the axis
-STEPGEN_MAX_VEL =    12
-STEPGEN_MAX_ACC =    24
-
-BACKLASH =           0.000
-
-SCALE = 1000
-
-MIN_LIMIT =             -10.0
-MAX_LIMIT =             10.0
-
-FERROR =     0.050
-MIN_FERROR = 0.005
-
-#HOME =                  0.000
-#HOME_OFFSET =           0.10
-#HOME_SEARCH_VEL =       0.10
-#HOME_LATCH_VEL =        -0.01
-#HOME_USE_INDEX =        YES
-#HOME_IGNORE_LIMITS =    YES
-
-# these are in nanoseconds
-DIRSETUP   =              200
-DIRHOLD    =              200
-STEPLEN    =              40000
-STEPSPACE  =              40000
-
-
-
-
-[EMCIO]
-
-# Name of IO controller program, e.g., io
-EMCIO =                 io
-
-# cycle time, in seconds
-CYCLE_TIME =            0.100
-
-# tool table file
-TOOL_TABLE =            tool.tbl
-
diff --git a/SW/MK/configs/hm2-soc-stepper/hm2-soc-stepper-5i25.hal b/SW/MK/configs/hm2-soc-stepper/hm2-soc-stepper-5i25.hal
deleted file mode 100644
index 35e4f9df..00000000
--- a/SW/MK/configs/hm2-soc-stepper/hm2-soc-stepper-5i25.hal
+++ /dev/null
@@ -1,204 +0,0 @@
-# #######################################
-#
-# HAL file for HostMot2 with 3 steppers
-#
-# Derived from Ted Hyde's original hm2-servo config
-#
-# Based up work and discussion with Seb & Peter & Jeff
-# GNU license references - insert here. www.machinekit.io
-#
-#
-# ########################################
-# Firmware files are in /lib/firmware/hm2/7i43/
-# Must symlink the hostmot2 firmware directory of sanbox to
-# /lib/firmware before running EMC2...
-# sudo ln -s $HOME/emc2-sandbox/src/hal/drivers/mesa-hostmot2/firmware /lib/firmware/hm2
-#
-# See also:
-# <http://www.linuxcnc.org/docs/devel/html/man/man9/hostmot2.9.html#config%20modparam>
-# and http://wiki.linuxcnc.org/cgi-bin/emcinfo.pl?HostMot2
-#
-# #####################################################################
-
-
-# ###################################
-# Core EMC/HAL Loads
-# ###################################
-
-# kinematics
-loadrt trivkins
-
-# motion controller, get name and thread periods from ini file
-# trajectory planner
-loadrt tp
-loadrt [EMCMOT]EMCMOT servo_period_nsec=[EMCMOT]SERVO_PERIOD num_joints=[TRAJ]AXES # tp=tp kins=trivkins
-
-# only the 7i43 needs this, but it doesnt hurt the others
-#loadrt probe_parport
-
-# hostmot2 driver
-loadrt hostmot2
-
-# load low-level driver
-loadrt [HOSTMOT2](DRIVER)
-#config=[HOSTMOT2](CONFIG)
-
-
-# ################################################
-# THREADS
-# ################################################
-
-addf hm2_[HOSTMOT2](BOARD).0.read         servo-thread
-addf motion-command-handler               servo-thread
-addf motion-controller                    servo-thread
-# revel in the free time here from not having to run PID
-addf hm2_[HOSTMOT2](BOARD).0.write        servo-thread
-addf hm2_[HOSTMOT2](BOARD).0.pet_watchdog servo-thread
-
-
-# ######################################################
-# Axis-of-motion Specific Configs (not the GUI)
-# ######################################################
-
-
-# ################
-# X [0] Axis
-# ################
-
-# axis enable chain
-newsig emcmot.00.enable bit
-sets emcmot.00.enable FALSE
-
-net emcmot.00.enable <= axis.0.amp-enable-out
-net emcmot.00.enable => hm2_[HOSTMOT2](BOARD).0.stepgen.00.enable
-
-
-# position command and feedback
-net emcmot.00.pos-cmd <= axis.0.motor-pos-cmd
-net emcmot.00.pos-cmd => hm2_[HOSTMOT2](BOARD).0.stepgen.00.position-cmd
-
-net motor.00.pos-fb <= hm2_[HOSTMOT2](BOARD).0.stepgen.00.position-fb
-net motor.00.pos-fb => axis.0.motor-pos-fb
-
-
-# timing parameters
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.00.dirsetup        [AXIS_0]DIRSETUP
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.00.dirhold         [AXIS_0]DIRHOLD
-
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.00.steplen         [AXIS_0]STEPLEN
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.00.stepspace       [AXIS_0]STEPSPACE
-
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.00.position-scale  [AXIS_0]SCALE
-
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.00.maxvel          [AXIS_0]STEPGEN_MAX_VEL
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.00.maxaccel        [AXIS_0]STEPGEN_MAX_ACC
-
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.00.step_type       0
-
-
-# ################
-# Y [1] Axis
-# ################
-
-# axis enable chain
-newsig emcmot.01.enable bit
-sets emcmot.01.enable FALSE
-
-net emcmot.01.enable <= axis.1.amp-enable-out
-net emcmot.01.enable => hm2_[HOSTMOT2](BOARD).0.stepgen.01.enable
-
-
-# position command and feedback
-net emcmot.01.pos-cmd <= axis.1.motor-pos-cmd
-net emcmot.01.pos-cmd => hm2_[HOSTMOT2](BOARD).0.stepgen.01.position-cmd
-
-net motor.01.pos-fb <= hm2_[HOSTMOT2](BOARD).0.stepgen.01.position-fb
-net motor.01.pos-fb => axis.1.motor-pos-fb
-
-
-# timing parameters
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.01.dirsetup        [AXIS_1]DIRSETUP
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.01.dirhold         [AXIS_1]DIRHOLD
-
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.01.steplen         [AXIS_1]STEPLEN
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.01.stepspace       [AXIS_1]STEPSPACE
-
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.01.position-scale  [AXIS_1]SCALE
-
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.01.maxvel          [AXIS_1]STEPGEN_MAX_VEL
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.01.maxaccel        [AXIS_1]STEPGEN_MAX_ACC
-
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.01.step_type       0
-
-
-# ################
-# Z [2] Axis
-# ################
-
-# axis enable chain
-newsig emcmot.02.enable bit
-sets emcmot.02.enable FALSE
-
-net emcmot.02.enable <= axis.2.amp-enable-out
-net emcmot.02.enable => hm2_[HOSTMOT2](BOARD).0.stepgen.02.enable
-
-
-# position command and feedback
-net emcmot.02.pos-cmd <= axis.2.motor-pos-cmd
-net emcmot.02.pos-cmd => hm2_[HOSTMOT2](BOARD).0.stepgen.02.position-cmd
-
-net motor.02.pos-fb <= hm2_[HOSTMOT2](BOARD).0.stepgen.02.position-fb
-net motor.02.pos-fb => axis.2.motor-pos-fb
-
-
-# timing parameters
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.02.dirsetup        [AXIS_2]DIRSETUP
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.02.dirhold         [AXIS_2]DIRHOLD
-
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.02.steplen         [AXIS_2]STEPLEN
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.02.stepspace       [AXIS_2]STEPSPACE
-
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.02.position-scale  [AXIS_2]SCALE
-
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.02.maxvel          [AXIS_2]STEPGEN_MAX_VEL
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.02.maxaccel        [AXIS_2]STEPGEN_MAX_ACC
-
-setp hm2_[HOSTMOT2](BOARD).0.stepgen.02.step_type       0
-
-
-
-
-#
-# The Mesa AnyIO output pins can be in open-drain mode (drive low, float
-# high) or push/pull mode (drive low, drive high).
-#
-# When a logical output is 1 in open-drain mode, the FPGA lets the pin
-# float and it gets pulled high to +5V via a 10K resistor.
-#
-# When a logical output is 1 in push/pull mode, the FPGA pushes the pin
-# high but only to +3.3V.  This is problematic on some kinds of inputs.
-#
-
-#setp hm2_[HOSTMOT2](BOARD).0.gpio.048.is_opendrain 1
-#setp hm2_[HOSTMOT2](BOARD).0.gpio.049.is_opendrain 1
-
-#setp hm2_[HOSTMOT2](BOARD).0.gpio.054.is_opendrain 1
-#setp hm2_[HOSTMOT2](BOARD).0.gpio.055.is_opendrain 1
-
-#setp hm2_[HOSTMOT2](BOARD).0.gpio.060.is_opendrain 1
-#setp hm2_[HOSTMOT2](BOARD).0.gpio.061.is_opendrain 1
-
-
-
-
-# ##################################################
-# Standard I/O Block - EStop, Etc
-# ##################################################
-
-# create a signal for the estop loopback
-net estop-loop iocontrol.0.user-enable-out => iocontrol.0.emc-enable-in
-
-# create signals for tool loading loopback
-net tool-prep-loop iocontrol.0.tool-prepare => iocontrol.0.tool-prepared
-net tool-change-loop iocontrol.0.tool-change => iocontrol.0.tool-changed
-
diff --git a/SW/MK/configs/hm2-soc-stepper/tool.tbl b/SW/MK/configs/hm2-soc-stepper/tool.tbl
deleted file mode 100644
index c0b72de0..00000000
--- a/SW/MK/configs/hm2-soc-stepper/tool.tbl
+++ /dev/null
@@ -1,4 +0,0 @@
-T1 P1 D0.125000 Z+0.511000 ;1/8 end mill
-T2 P2 D0.062500 Z+0.100000 ;1/16 end mill
-T3 P3 D0.201000 Z+1.273000 ;#7 tap drill
-T99999 P99999 Z+0.100000 ;big tool number
diff --git a/SW/MK/hm2_cvsoc.c b/SW/MK/hm2_cvsoc.c
deleted file mode 100644
index 3cbaf37e..00000000
--- a/SW/MK/hm2_cvsoc.c
+++ /dev/null
@@ -1,495 +0,0 @@
-
-//
-//    Copyright (C) 2007-2008 Sebastian Kuzminsky
-//
-//    This program is free software; you can redistribute it and/or modify
-//    it under the terms of the GNU General Public License as published by
-//    the Free Software Foundation; either version 2 of the License, or
-//    (at your option) any later version.
-//
-//    This program is distributed in the hope that it will be useful,
-//    but WITHOUT ANY WARRANTY; without even the implied warranty of
-//    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-//    GNU General Public License for more details.
-//
-//    You should have received a copy of the GNU General Public License
-//    along with this program; if not, write to the Free Software
-//    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-//
-//    Transformed for Machinekit socfpga in 2016 by Michael Brown
-//    Copyright (C) Holotronic 2016-2017
-
-
-//---------------------------------------------------------------------------//
-//  # 
-//  # module assignments (from hm2reg_io_hw.tcl)
-//  # 
-//  set_module_assignment embeddedsw.dts.group hm2-socfpga
-//  set_module_assignment embeddedsw.dts.name hm2reg-io
-//  set_module_assignment embeddedsw.dts.params.address_width 14
-//  set_module_assignment embeddedsw.dts.params.data_width 32
-//  set_module_assignment embeddedsw.dts.vendor machkt
-//---------------------------------------------------------------------------//
-// in device tree (sos_system.dts)
-//
-//  hm2reg_io_0: hm2-socfpga@0x100040000 {
-//      compatible = "machkt,hm2reg-io-1.0";
-//      reg = <0x00000001 0x00040000 0x00010000>;
-//      clocks = <&clk_0>;
-//      address_width = <14>;	/* embeddedsw.dts.params.address_width type NUMBER */
-//      data_width = <32>;	/* embeddedsw.dts.params.data_width type NUMBER */
-//  }; //end hm2-socfpga@0x100040000 (hm2reg_io_0)
-//---------------------------------------------------------------------------//
-// on commandline:
-//  machinekit@mksoc:~$ ls -R /proc/device-tree | grep hm2-socfpga
-//  hm2-socfpga@0x100040000
-//  /proc/device-tree/sopc@0/bridge@0xc0000000/hm2-socfpga@0x100040000:
-//---------------------------------------------------------------------------//
-
-
-#include "config.h"
-
-// this should be an general socfpga #define
-#if !defined(TARGET_PLATFORM_SOCFPGA)
-#error "This driver is for the socfpga platform only"
-#endif
-
-#if !defined(BUILD_SYS_USER_DSO)
-#error "This driver is for usermode threads only"
-#endif
-
-
-#include "rtapi.h"
-#include "rtapi_app.h"
-//#include "rtapi_math.h"
-#include "rtapi_string.h"
-//#include "rtapi_pci.h"
-
-#include "hal.h"
-
-#include <fcntl.h>
-#include <sys/mman.h>
-#include <unistd.h>
-
-
-//#include "hal/drivers/mesa-hostmot2/bitfile.h"
-#include "hal/drivers/mesa-hostmot2/hostmot2-lowlevel.h"
-#include "hm2_cvsoc.h"
-
-//#include "../Include/mksocfpga/hps_0.h"
-#define HM2REG_IO_0_SPAN 65536
-
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Michael Brown");
-MODULE_DESCRIPTION("Driver initially for HostMot2 on the DE0 Nano / Atlas Cyclone V socfpga board from Terasic");
-MODULE_SUPPORTED_DEVICE("Mesa-AnythingIO-5i25");  // FIXME
-
-
-static char *config[HM2_SOC_MAX_BOARDS];
-RTAPI_MP_ARRAY_STRING(config, HM2_SOC_MAX_BOARDS, "config string for the AnyIO boards (see hostmot2(9) manpage)")
-
-static int comp_id;
-static int  uio_fd;
-
-
-// FIXME: should probably have a linked list of boards instead of an array
-static hm2_cvsoc_t hm2_cvsoc_board[HM2_SOC_MAX_BOARDS];
-static int num_boards = 0;
-//static int num_5i20 = 0;
-//static int num_5i21 = 0;
-//static int num_5i22 = 0;
-//static int num_5i23 = 0;
-//static int num_5i24 = 0;
-static int num_5i25 = 0;
-static int num_6i25 = 0;
-//static int num_4i65 = 0;
-//static int num_4i68 = 0;
-//static int num_4i69 = 0;
-//static int num_3x20 = 0;
-static int failed_errno=0; // errno of last failed registration
-
-
-//---------------------------------------------------------------//
-
-
-
-/* // probe string for uio driver
-static const struct of_device_id uio_of_genirq_match[] = {
-    { .compatible = "machkt,hm2reg-io-1.0", },
-    { }
-};
-*/
-
-// this struct contains the hm2 interface ip core info provided in the device-tree
-
-static struct dts_device_id hm2_cvsoc_tbl[] = {
-        
-    // 5i25
-    {
-        .address_width = 14,        //0x0000000E
-        .clocks = 2,                //0x00000002 number of clocks ?
-        .compatible = {
-            .vendor = "machkt",       //6D 61 63 68 6B 74 2C
-            .name = "hm2reg-io",      //68 6D 32 72 65 67 2D 69 6F 2D 31 2E 30 00
-        }, // (machkt,hm2reg-io-1.0.)
-        .data_width = 32,           // 0x00000020
-        .name = "hm2-socfpga",        //68 6D 32 2D 73 6F 63 66 70 67 61 00 (hm2-socfpga.)
-        .reg = {0x00000001, 0x00040000, 0x00010000},// ?, address offset from bridge, address span (= max address +1)
-    },
-    {0,},
-};
-
-//MODULE_DEVICE_TABLE(soc, hm2_cvsoc_tbl);
-
-
-// 
-// these are the "low-level I/O" functions exported up
-//
-
-static int hm2_cvsoc_read(hm2_lowlevel_io_t *this, u32 addr, void *buffer, int size) {
-    hm2_cvsoc_t *board = this->private;
-    int i;
-    u32* src = (u32*) (board->base + addr);
-    u32* dst = (u32*) buffer;
-
-    /* Per Peter Wallace, all hostmot2 access should be 32 bits and 32-bit aligned */
-    /* Check for any address or size values that violate this alignment */
-    if ( ((addr & 0x3) != 0) || ((size & 0x03) != 0) ){
-        u16* dst16 = (u16*) dst;
-        u16* src16 = (u16*) src;
-        /* hm2_read_idrom performs a 16-bit read, which seems to be OK, so let's allow it */
-        if ( ((addr & 0x1) != 0) || (size != 2) ){
-            rtapi_print_msg(RTAPI_MSG_ERR, "hm2_cvsoc_read: Unaligned Access: %08x %04x\n", addr,size);
-            memcpy(dst, src, size);
-            return 1;  // success
-        }
-        dst16[0] = src16[0];
-        return 1;  // success
-    }
-
-//    rtapi_print_msg(RTAPI_MSG_ERR, "pci_read : %08x.%04x", addr,size);
-    for (i=0; i<(size/4); i++) {
-        dst[i] = src[i];
-//        rtapi_print_msg(RTAPI_MSG_ERR, " %08x", dst[i]);
-    }
-//    rtapi_print_msg(RTAPI_MSG_ERR, "\n");
-    return 1;  // success
-}
-
-static int hm2_cvsoc_write(hm2_lowlevel_io_t *this, u32 addr, void *buffer, int size) {
-    hm2_cvsoc_t *board = this->private;
-    int i;
-    u32* src = (u32*) buffer;
-    u32* dst = (u32*) (board->base + addr);
-
-    /* Per Peter Wallace, all hostmot2 access should be 32 bits and 32-bit aligned */
-    /* Check for any address or size values that violate this alignment */
-    if ( ((addr & 0x3) != 0) || ((size & 0x03) != 0) ){
-        rtapi_print_msg(RTAPI_MSG_ERR, "hm2_cvsoc_write: Unaligned Access: %08x %04x\n", addr,size);
-        memcpy(dst, src, size);
-        return 1;  // success
-    }
-
-//    rtapi_print_msg(RTAPI_MSG_ERR, "pci_write: %08x.%04x", addr,size);
-    for (i=0; i<(size/4); i++) {
-//        rtapi_print_msg(RTAPI_MSG_ERR, " %08x", src[i]);
-        dst[i] = src[i];
-    }
-//    rtapi_print_msg(RTAPI_MSG_ERR, "\n");
-    return 1;  // success
-}
-
-
-/*
-static int hm2_cvsoc_program_fpga(hm2_lowlevel_io_t *this, const bitfile_t *bitfile) {
-
-//    disable bridges:  
-    echo 0 > hps2fpga, lwhps2fpga, fpga2hps
-    cat bitfile > /dev/fpga
-    //    enable bridges:  
-    echo 1 > hps2fpga, lwhps2fpga, fpga2hps
-
-    return 0;
-
-
-fail:
-    ???
-    return -EIO;
-}
-*/
-
-
-/*
-static int hm2_cvsoc_reset(hm2_lowlevel_io_t *this) {
-    return 0;
-}
-*/
-// 
-// misc internal functions
-//
-
-/*
-static int hm2_cvsoc_probe(struct cvsoc_dev *dev, const struct dts_device_id *id) {
-    int r;
-    hm2_cvsoc_t *board;
-    hm2_lowlevel_io_t *this;
-
-// could there be more than 1 hm2 interface needed on a soc ?
-//    if (num_boards >= HM2_SOC_MAX_BOARDS) {
-//        LL_PRINT("skipping hm2 soc interface at %s, this driver can only handle %d\n", dts_name(dev), HM2_SOC_MAX_BOARDS);
-//        return -EINVAL;
-//    }
-
-    board = &hm2_cvsoc_board[num_boards];
-    this = &board->llio;
-    memset(this, 0, sizeof(hm2_lowlevel_io_t));
-
-//    switch (dev->name) {
-    switch (dts_device_id->name) {
-            
-        case hm2-socfpga: {
-            if (dts_device_id->compatible->name == hm2reg-io) {
-//                LL_PRINT("discovered hm2reg-io at %s\n", dts_name(dev));
-                LL_PRINT("discovered hm2reg-io at entity (machkt,hm2reg-io-1.0.)\n");                
-//                rtapi_snprintf(board->llio.name, sizeof(board->llio.name), "hm2_5i25.%d", num_5i25);
-                num_5i25 ++;
-            }
-//            else {
-//                LL_PRINT("discovered 6i25 at %s\n", dts_name(dev));
-//                rtapi_snprintf(board->llio.name, sizeof(board->llio.name), "hm2_6i25.%d", num_6i25);
-//                num_6i25 ++;
-//            }
-            board->llio.num_ioport_connectors = 2;
-            board->llio.pins_per_connector = 17;
-            board->llio.ioport_connector_name[0] = "P3";
-            board->llio.ioport_connector_name[1] = "P2";
-            board->llio.fpga_part_number = "6slx9tqg144";
-            board->llio.num_leds = 2;
-            break;
-        }
-
-        default: {
-//            LL_ERR("unknown subsystem device id 0x%04x\n", dev->name);
-            LL_ERR("unknown dts subsystem \n");
-            return failed_errno = -ENODEV;
-        }
-    }
-
-
-    switch (dev->name) {
-//        case HM2_PCI_DEV_MESA5I25:
-        case hm2-socfpga: {
-              // mksocfpga_io_hm2 is 64K mem (32 bit)
-//            board->len = pci_resource_len(dev, 0);
-            board->base = pci_ioremap_bar(dev, 0);
-            if (board->base == NULL) {
-                THIS_ERR("could not map in FPGA address space\n");
-                r = -ENODEV;
-                goto fail0;
-            }
-            break;
-        }
-
-        default: {
-            THIS_ERR("unknown DTS Device ID 0x%04x\n", dev->group);
-            r = -ENODEV;
-            goto fail0;
-        }
-    }
-
-
-    board->dev = dev;
-
-//    pci_set_drvdata(dev, board);
-    cvsoc_set_drvdata(dev, board);
-    
-    board->llio.comp_id = comp_id;
-    board->llio.private = board;
-
-    board->llio.threadsafe = 1;
-
-    board->llio.read = hm2_cvsoc_read;
-    board->llio.write = hm2_cvsoc_write;
-
-    r = hm2_register(&board->llio, config[num_boards]);
-    if (r != 0) {
-        THIS_ERR("board fails HM2 registration\n");
-        goto fail1;
-    }
-
-//    THIS_PRINT("initialized AnyIO board at %s\n", dts_name(dev));
-    THIS_PRINT("initialized AnyIO HM2 core at %s\n", cvsoc_name(dev));
-    
-    num_boards ++;
-    return 0;
-
-
-fail1:
-//    pci_set_drvdata(dev, NULL);
-    cvsoc_set_drvdata(dev, NULL);
-    iounmap(board->base);
-    board->base = NULL;
-
-fail0:
-//    cvsoc_disable_device(dev);
-    return failed_errno = r;
-}
-*/
-/*
-static void hm2_cvsoc_remove(struct cvsoc_dev *dev) {
-    int i;
-
-    for (i = 0; i < num_boards; i++) {
-        hm2_cvsoc_t *board = &hm2_cvsoc_board[i];
-        hm2_lowlevel_io_t *this = &board->llio;
-
-        if (board->dev == dev) {
-            THIS_PRINT("dropping AnyIO board at %s\n", dts_name(dev));
-
-            hm2_unregister(&board->llio);
-
-            // Unmap board memory
-            if (board->base != NULL) {
-                iounmap(board->base);
-                board->base = NULL;
-            }
-
-            pci_disable_device(dev);
-            pci_set_drvdata(dev, NULL);
-            board->dev = NULL;
-        }
-    }
-}
-*/
-/*
-static struct uio_driver hm2_cvsoc_driver = {
-	.name = HM2_LLIO_NAME,
-	.id_table = hm2_cvsoc_tbl,
-	.probe = hm2_cvsoc_probe,
-	.remove = hm2_cvsoc_remove,
-};
-*/
-
-//static int hm2_cvsoc_mmap(const struct dts_device_id *id) {
-//static int hm2_cvsoc_mmap(struct cvsoc_dev *dev, const struct dts_device_id *id) {
-static int hm2_cvsoc_mmap(void) {
-
-    hm2_cvsoc_t *me;
-    hm2_lowlevel_io_t *this;
-    int r = 0;
-
-    /* Open the resource node */
-    uio_fd = open ( "/dev/uio0", ( O_RDWR | O_SYNC ) );
-    if (uio_fd < 0) {
-        rtapi_print_msg(RTAPI_MSG_ERR, "Could not open UIO resource for: hm2_mksocfpga . (%s)\n", strerror(errno));
-        return 0;
-    }
-    // get virtual addr that maps to physical
-    virtual_base = mmap( NULL, HM2REG_IO_0_SPAN, ( PROT_READ | PROT_WRITE ), MAP_SHARED, uio_fd, 0);
-    return (1);
-    
-
-    me = &hm2_cvsoc_board[0];
-    this = &me->llio;
-     rtapi_snprintf(me->llio.name, sizeof(me->llio.name), "hm2_5i25.%d", num_5i25);
-    
-    me->llio.num_ioport_connectors = 2;
-    me->llio.pins_per_connector = 17;
-    me->llio.ioport_connector_name[0] = "P3";
-    me->llio.ioport_connector_name[1] = "P2";
-    me->llio.fpga_part_number = "6slx9tqg144";
-    me->llio.num_leds = 2;
-    
-    me->llio.comp_id = comp_id;
-    me->llio.private = me;
-
-    me->llio.threadsafe = 1;
-
-    me->llio.read = hm2_cvsoc_read;
-    me->llio.write = hm2_cvsoc_write;
-
-    r = hm2_register(&hm2_cvsoc_board->llio, config[num_boards]);
-
-    if (r != 0) {
-        THIS_ERR("hm2_cvsoc_board fails HM2 registration\n");
-        return -EIO;
-    }
-
-    THIS_PRINT("initialized AnyIO hm2_cvsoc_board \n");
-
-    num_boards ++;
-    return 0;
-
-//    close ( fd );
-
-}
-
-static int hm2_cvsoc_munmap(void) {
-  if (virtual_base)
-    munmap((void *) virtual_base, HM2REG_IO_0_SPAN);
-  if (uio_fd > -1)
-      close (uio_fd);
-//  hal_exit(comp_id);
-  return(1);
-
-}
-int rtapi_app_main(void) {
-//    hm2_cvsoc_t *me;
-//    hm2_lowlevel_io_t *this;
-    int r = 0;
-
-    LL_PRINT("loading Mesa AnyIO HostMot2 socfpgs driver version " HM2_SOCFPGA_VERSION "\n");
-
-    comp_id = hal_init(HM2_LLIO_NAME);
-    if (comp_id < 0) return comp_id;
-
-//    me = &hm2_cvsoc_board[0];
-//    this = &me->llio;
-
-//    r = uio_register_driver(&hm2_cvsoc_driver);
-    r = hm2_cvsoc_mmap();
-    
-    if (r != 0) {
-        LL_ERR("error registering UIO driver\n");
-        hal_exit(comp_id);
-        return r;
-    }
-
-    if(failed_errno) {
-	// at least one card registration failed
-	hal_exit(comp_id);
-//	uio_unregister_driver(&hm2_cvsoc_driver);
-//	hm2_cvsoc_munmap(&hm2_cvsoc_driver);
-	r = hm2_cvsoc_munmap();
-//	return failed_errno;
-	return r;
-    }
-
-    if(num_boards == 0) {
-	// no cards were detected
-    LL_PRINT("error no supported cards detected\n");
-	hal_exit(comp_id);
-//	pci_unregister_driver(&hm2_cvsoc_driver);
-	r = hm2_cvsoc_munmap();
-   
-//	return -ENODEV;
-	return r;
-    }
-
-//    me->llio.program_fpga = hm2_test_program_fpga;
-//    me->llio.reset = hm2_test_reset;
-
-
-    hal_ready(comp_id);
-    return 0;
-}
-
-
-void rtapi_app_exit(void) {
-//    uio_unregister_driver(&hm2_cvsoc_driver);
-    hm2_cvsoc_munmap();
-    LL_PRINT("UIO driver unloaded\n");
-    hal_exit(comp_id);
-}
-
diff --git a/SW/MK/hm2_cvsoc.h b/SW/MK/hm2_cvsoc.h
deleted file mode 100644
index dfac8de5..00000000
--- a/SW/MK/hm2_cvsoc.h
+++ /dev/null
@@ -1,84 +0,0 @@
-
-//
-//    Copyright (C) 2007-2008 Sebastian Kuzminsky
-//
-//    This program is free software; you can redistribute it and/or modify
-//    it under the terms of the GNU General Public License as published by
-//    the Free Software Foundation; either version 2 of the License, or
-//    (at your option) any later version.
-//
-//    This program is distributed in the hope that it will be useful,
-//    but WITHOUT ANY WARRANTY; without even the implied warranty of
-//    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-//    GNU General Public License for more details.
-//
-//    You should have received a copy of the GNU General Public License
-//    along with this program; if not, write to the Free Software
-//    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-//
-
-
-#define HM2_SOCFPGA_VERSION "0.8"
-
-#define HM2_LLIO_NAME "hm2_cvsoc"
-
-
-#define HM2_SOC_MAX_BOARDS  1
-
-
-//
-// Programming variables
-//
-// Note: just for the nano / atlas board initially
-//
-
-
-/* how long should we wait for DONE when programming socfpga systems */
-#define DONE_WAIT_CVSOCFPGA			2000 // :-)
-
-// the pci dev would corrospond to the uio dev in the soc system.
-// the only unique thing the uio device provides is easy access to the hardware memory
-// through /dev/uio0 device.
-// A design practice this is is dscuraged for future designs by Denx who provides u-boot
-// among others.   
-// Therefore there is a solid reason for creating an pci --> uio struct containing whats left from there.
-// And adding a dts_device_id for all devices that can benefit from utilising device-tree info.
-// To have a forward way towards partial fpga reconfiguration data structures relating to device tree overlays.
-// could come in handy. Once the soc / embedded systems migrate to 4.x+ kernels.
-
-
-typedef struct {
-//    struct dts_dev *dev;
-    void __iomem *base;
-    int len;
-    unsigned long ctrl_base_addr;
-    unsigned long data_base_addr;
-    hm2_lowlevel_io_t llio;
-} hm2_cvsoc_t;
-
-struct compatible {
-        char vendor[32];
-        char name[32];
-};
-
-struct dts_device_id {
-    unsigned short address_width;           //address width /
-    unsigned short clocks;                  // clocks /
-    struct compatible compatible;
-    unsigned short data_width;       /* (class,subclass,prog-if) triplet */
-    char name[32];
-    unsigned long reg[3];
-};
-
-
-/*
-typedef struct {
-    union {
-        u8 tp8[64 * 1024];
-        u32 tp32[16 * 1024];
-    } test_pattern;
-
-    hm2_lowlevel_io_t llio;
-} hm2_cvsoc_t;
-*/
-volatile void *virtual_base;
diff --git a/SW/MK/hm2_socfpga-mk.patch b/SW/MK/hm2_socfpga-mk.patch
deleted file mode 100644
index 5a74b3a8..00000000
--- a/SW/MK/hm2_socfpga-mk.patch
+++ /dev/null
@@ -1,161 +0,0 @@
-diff --git a/src/Makefile b/src/Makefile
-index 824603e..4b50d42 100755
---- a/src/Makefile
-+++ b/src/Makefile
-@@ -1266,6 +1266,12 @@ obj-$(CONFIG_PEPPER) += pepper.o
- pepper-objs := hal/components/pepper.o $(MATHSTUB)
- endif
- 
-+#ifdef TARGET_PLATFORM_SOCFPGA
-+#ifeq ($(BUILD_SYS),user-dso)
-+#obj-$(CONFIG_HAL_UIO) += ???.o
-+#hm2_cvsoc-uio-objs := hal/drivers/???.o
-+#endif
-+
- ifdef TARGET_PLATFORM_ZEDBOARD
- obj-$(CONFIG_HAL_GPIO) += hal_zed_gpio.o
- hal_zed_gpio-objs := hal/drivers/hal_zed_gpio.o
-@@ -1328,10 +1334,13 @@ endif
- ifeq ($(BUILD_HOSTMOT2),yes)
- obj-$(CONFIG_HOSTMOT2) += hostmot2.o hm2_7i43.o hm2_7i90.o hm2_pci.o hm2_test.o
- ifeq ($(BUILD_SYS),user-dso)
--obj-$(CONFIG_HOSTMOT2) += hm2_eth.o
-+obj-$(CONFIG_HOSTMOT2) += hm2_eth.o hm2_cvsoc.o
- hm2_eth-objs  :=			  \
-     hal/drivers/mesa-hostmot2/hm2_eth.o   \
-     $(MATHSTUB)
-+hm2_cvsoc-objs  :=			  \
-+    hal/drivers/mesa-hostmot2/hm2_cvsoc.o \
-+    $(MATHSTUB)
- endif
- #obj-$(CONFIG_HOSTMOT2) += hostmot2.o hm2_pci.o hm2_7i43.o
- hostmot2-objs +=			  \
-@@ -1600,6 +1609,13 @@ endif
- $(RTLIBDIR)/hm2_test$(MODULE_EXT): $(addprefix $(OBJDIR)/,$(hm2_test-objs))
- endif
- 
-+ifdef TARGET_PLATFORM_SOCFPGA
-+ifeq ($(BUILD_SYS),user-dso)
-+$(RTLIBDIR)/hostmot2$(MODULE_EXT): $(addprefix $(OBJDIR)/,$(hostmot2-objs))
-+$(RTLIBDIR)/hm2_cvsoc$(MODULE_EXT): $(addprefix $(OBJDIR)/,$(hm2_cvsoc-objs))
-+endif
-+endif
-+
- ifdef TARGET_PLATFORM_BEAGLEBONE
- ifeq ($(BUILD_SYS),user-dso)
- $(RTLIBDIR)/hal_pru$(MODULE_EXT): $(addprefix $(OBJDIR)/,$(hal_pru-objs))diff --git a/src/Makefile.inc.in b/src/Makefile.inc.in
-index 2ae1069..68f4c26 100644
---- a/src/Makefile.inc.in
-+++ b/src/Makefile.inc.in
-@@ -191,6 +191,7 @@ BUILD_DRIVERS = @BUILD_DRIVERS@
- USE_PORTABLE_PARPORT_IO = @USE_PORTABLE_PARPORT_IO@
- TARGET_PLATFORM_PC = @TARGET_PLATFORM_PC@
- TARGET_PLATFORM_BEAGLEBONE = @TARGET_PLATFORM_BEAGLEBONE@
-+TARGET_PLATFORM_SOCFPGA = @TARGET_PLATFORM_SOCFPGA@
- TARGET_PLATFORM_RASPBERRY = @TARGET_PLATFORM_RASPBERRY@
- TARGET_PLATFORM_ZEDBOARD = @TARGET_PLATFORM_ZEDBOARD@
- ARCHITECTURE=@ARCHITECTURE@diff --git a/src/configure.ac b/src/configure.ac
-index cc8f1ca..2b7e9f5 100644
---- a/src/configure.ac
-+++ b/src/configure.ac
-@@ -534,6 +534,7 @@ KSOURCE_LOCATION_HINTS=$(echo \
- # PLATFORM
- # TARGET_PLATFORM_PC
- # TARGET_PLATFORM_BEAGLEBONE
-+# TARGET_PLATFORM_SOCFPGA
- # TARGET_PLATFORM_RASPBERRY
- # TARGET_PLATFORM_ZEDBOARD
- #
-@@ -644,6 +645,35 @@ AC_ARG_WITH(platform-beaglebone,
- 	esac
-     ])
- 
-+AC_ARG_WITH(platform-socfpga,
-+    [AS_HELP_STRING(
-+        [--with-platform-socfpga],
-+	[Build for Socfpga platform (default for ARM arch)])],
-+    [
-+        case $with_platform_socfpga in
-+	    (y*)
-+	    	TARGET_PLATFORM_SOCFPGA=true
-+		platform_specified=true
-+		platform_socfpga_reason="$cmdl_enab_msg"
-+		;;
-+	    (*)
-+	    	TARGET_PLATFORM_SOCFPGA=false
-+		platform_socfpga_reason="$cmdl_disab_msg"
-+		;;
-+	esac
-+    ],
-+    [
-+        case $host_cpu in
-+	    (arm*)
-+	        TARGET_PLATFORM_SOCFPGA=unk
-+		;;
-+	    (*)
-+	        TARGET_PLATFORM_SOCFPGA=false
-+		platform_beaglebone_reason="$arch_disab_msg"
-+		;;
-+	esac
-+    ])
-+
- AC_ARG_WITH(platform-raspberry,
-     [AS_HELP_STRING(
-         [--with-platform-raspberry],
-@@ -713,6 +743,10 @@ if $platform_specified; then
- 	TARGET_PLATFORM_BEAGLEBONE=false
- 	platform_beaglebone_reason="$cmdl_notspec_msg"
-     fi
-+    if test $TARGET_PLATFORM_SOCFPGA = unk; then
-+	TARGET_PLATFORM_SOCFPGA=false
-+	platform_socfpga_reason="$cmdl_notspec_msg"
-+    fi
-     if test $TARGET_PLATFORM_RASPBERRY = unk; then
- 	TARGET_PLATFORM_RASPBERRY=false
- 	platform_raspberry_reason="$cmdl_notspec_msg"
-@@ -733,6 +767,10 @@ else
-         TARGET_PLATFORM_BEAGLEBONE=true
- 	platform_beaglebone_reason="$arch_enab_msg"
-     fi
-+    if test $TARGET_PLATFORM_SOCFPGA = unk; then
-+        TARGET_PLATFORM_SOCFPGA=true
-+	platform_socfpga_reason="$arch_enab_msg"
-+    fi
-     if test $TARGET_PLATFORM_RASPBERRY = unk; then
-         TARGET_PLATFORM_RASPBERRY=true
- 	platform_raspberry_reason="$arch_enab_msg"
-@@ -750,6 +788,9 @@ AC_MSG_RESULT([$platform_pc_reason])
- AC_MSG_CHECKING(platform-beaglebone)
- AC_MSG_RESULT([$platform_beaglebone_reason])
- 
-+AC_MSG_CHECKING(platform-socfpga)
-+AC_MSG_RESULT([$platform_socfpga_reason])
-+
- AC_MSG_CHECKING(platform-raspberry)
- AC_MSG_RESULT([$platform_raspberry_reason])
- 
-@@ -1788,7 +1829,12 @@ if $TARGET_PLATFORM_BEAGLEBONE; then
-    AC_DEFINE(TARGET_PLATFORM_BEAGLEBONE, [], [build for BeagleBone platform])
-    target_platform_beaglebone_val=yes
- fi
--AC_SUBST(TARGET_PLATFORM_BEAGLEBONE,$target_platform_beaglebone_val)
-+
-+if $TARGET_PLATFORM_SOCFPGA; then
-+   AC_DEFINE(TARGET_PLATFORM_SOCFPGA, [], [build for Socfpga platform])
-+   target_platform_socfpga_val=yes
-+fi
-+AC_SUBST(TARGET_PLATFORM_SOCFPGA,$target_platform_socfpga_val)
- 
- if $TARGET_PLATFORM_RASPBERRY; then
-    AC_DEFINE(TARGET_PLATFORM_RASPBERRY, [], [build for Raspberry Pi platform])diff --git a/src/machinekitcfg.py-tmp.in b/src/machinekitcfg.py-tmp.in
-index ee7e3d7..697997f 100644
---- a/src/machinekitcfg.py-tmp.in
-+++ b/src/machinekitcfg.py-tmp.in
-@@ -139,6 +139,7 @@ class Config(object):
-         self.USE_PORTABLE_PARPORT_IO = "@USE_PORTABLE_PARPORT_IO@"
-         self.TARGET_PLATFORM_PC = "@TARGET_PLATFORM_PC@"
-         self.TARGET_PLATFORM_BEAGLEBONE = "@TARGET_PLATFORM_BEAGLEBONE@"
-+        self.TARGET_PLATFORM_SOCFPGA = "@TARGET_PLATFORM_SOCFPGA@"
-         self.TARGET_PLATFORM_RASPBERRY = "@TARGET_PLATFORM_RASPBERRY@"
-         self.ARCHITECTURE="@ARCHITECTURE@"
- 
\ No newline at end of file
diff --git a/SW/MK/kernel-drivers/Adc-commands.txt b/SW/MK/kernel-drivers/Adc-commands.txt
deleted file mode 100644
index 2fe7f950..00000000
--- a/SW/MK/kernel-drivers/Adc-commands.txt
+++ /dev/null
@@ -1,216 +0,0 @@
-#------- Added adc-ip-v1-bin-doc - tag -----------------#
-WRite:
-// write for control
-reg 				measure_fifo_start;
-reg  [11:0] 	measure_fifo_num;
-reg	[2:0]		measure_fifo_ch;
-reg				auto_ch_select;
-
-addr 0  `define WRITE_REG_START_CH      0   {measure_fifo_ch, measure_fifo_start} <= slave_writedata[3:0];
-
-addr 1  `define WRITE_REG_MEASURE_NUM   1   {auto_ch_select, measure_fifo_num} <= slave_writedata[12:0];
-
-REad:
-reg measure_fifo_done;
-wire [11:0]	 fifo_q;
-wire [2:0] fifo_ch_q;
-
-addr 0  `define READ_REG_MEASURE_DONE   0   slave_read_status   slave_readdata <= {measure_fifo_ch, measure_fifo_num, measure_fifo_done};
-
-addr 1  `define READ_REG_ADC_VALUE      1   slave_read_data     slave_readdata <= {1'b0, fifo_ch_q, fifo_q};
-
-
-
-#------- quartus files copy ---------------------#
-mib@debian9-ws:~/Development/the-snowwhite-git/mksocfpga-work/mksocfpga/Scripts$ ./inst-rbf-dtb.sh
-
-mib@debian9-ws:~/Development/the-snowwhite-git/mksocfpga-work/mksocfpga/Scripts$ scp boot_files/socfpga.* machinekit@mksocfpga.local:~/
-
-mib@debian9-ws:~/Development/the-snowwhite-git/mksocfpga-work/mksocfpga/Scripts$ ssh -X machinekit@mksocfpga.local
-
-machinekit@mksocfpga:~$ sudo mv socfpga.* /boot
-machinekit@mksocfpga:~$ sudo reboot
-
-sudo mv socfpga.* /boot
-sudo reboot
-
-
-ssh -X machinekit@mksocfpga.local
-
-sudo insmod adcreg.ko
-
-sudo modprobe adcreg
-
-#cat /sys/bus/platform/drivers/adcreg/adcreg > test.dat
-
-#---------- working command sequence example ---------------------------------------#
-sudo insmod adcreg.ko
-
-# set measure number (number of samples = 2047)
-./adcfs w 1 2047  # limit !
-
-
-./adcfs w 1 32  # limit !
-
-
-
-# set sample channel 2 start (ch_nr << 1 | 0x001)
-./adcfs w 0 4
-./adcfs w 0 5
-./adcfs w 0 4
-
-# read and print all sampled values to screen
-./adcfs a
-
-# set sample channel 0 start (ch_nr << 1 | 0x001)
-./adcfs w 0 0
-./adcfs w 0 1
-./adcfs w 0 0
-
-# read and print all sampled values to screen
-./adcfs a
-
-#---------- Auto channel select ----------------#
-# set measure number (number of samples = 16)
-./adcfs w 1 16
-
-# set sample channel 2 ready/start/ready and auto update bit(ch_nr << 1 | 0x00(0/1) | 0x010)
-./adcfs w 0 20
-./adcfs w 0 21
-./adcfs w 0 20
-
-# read and print all sampled values to screen
-./adcfs a
-
-#---------- Single channel select --------------#
-
-./adcfs w 1 16
-
-./adcfs w 0 0
-./adcfs w 0 1
-./adcfs w 0 0
-
-./adcfs a
-
-
-
-
-
-sudo mv socfpga.* /boot
-
-sudo reboot
-
-ssh -X machinekit@mksocfpga.local
-
-
-sudo insmod adcreg.ko
-
-
-set measure counter:
-
-	setdata = 0x202;
-	adr = 0x04;
-	iowrite16(setdata, adcreg_mem + adr);
-
-	setdata = CounterData;
-	adr = 0x04;
-	iowrite16(setdata, adcreg_mem + adr);
-
-
-
-	setdata = 0x100;
-	adr = 0x00;
-	iowrite16(setdata, adcreg_mem + adr);
-
-	setdata = 0x000;
-	adr = 0x02;
-	iowrite16(setdata, adcreg_mem + adr);
-
-	setdata = 0x202;
-	adr = 0x04;
-	iowrite16(setdata, adcreg_mem + adr);
-
-	adr = 0x00;
-	setdata = 0xFFF;
-	iowrite16(setdata, adcreg_mem + adr);
-*/
-
-#set measure ch (0-7 << 1)
-./adcfs w 0 0
-
-#set measurecount (12 bit)
-./adcfs w 4 3
-#sleep 1
-
-# start measurement
-./adcfs w 0 1
-
-#read measurement
-./adcfs a
-
-cat /proc/kallsyms
-
-
-
-#set measurecount (12 bit)
-./adcfs w 4 3
-
-#set measure ch (0-7 << 1)
-./adcfs w 0 0
-
-# start measurement
-./adcfs w 0 1
-
-
-#-------------------------------------------------#
-
-./adcfs w 0 0
-./adcfs r 0
-./adcfs w 0 1
-
-./adcfs w 0 0
-sleep 0.15
-./adcfs w 0 1
-
-#--------------------------------------#
-
-sudo insmod adcreg.ko
-
-# set write channel to 2 (ch_nr >> 1)
-./adcfs w 0 4
-
-# set measure number (number of samples = 2)
-./adcfs w 1 10
-
-# set sample channel 2 start (ch_nr << 1 | 0x011)
-./adcfs w 0 4
-./adcfs w 0 5
-./adcfs w 0 4
-
-# read values
-./adcfs a
-
-
-
-
-
-#sudo chmod 666 /sys/bus/platform/drivers/adcreg/adcreg
-
-sudo modinfo adcreg.ko
-
-machinekit@mksocfpga:~$ sudo modinfo adcreg.ko
-filename:       /home/machinekit/adcreg.ko
-license:        Dual BSD/GPL
-license:        Dual BSD/GPL
-depends:
-vermagic:       3.10.37-ltsi-rt37-05839-gd0c5abc SMP preempt mod_unload ARMv7 p2v8
-
-machinekit@mksocfpga:~$ sudo modinfo hm2reg_uio_module
-filename:       /lib/modules/3.10.37-ltsi-rt37-05839-gd0c5abc/extra/home/mib/Development/the-snowwhite-git/mksocfpga-work/mksocfpga/SW/MK/kernel-drivers/hm2reg_uio-module/hm2reg_uio-module.ko
-alias:          platform:hm2cvsoc
-license:        GPL v2
-description:    CVSoc Userspace I/O platform driver with generic IRQ handling developed for Machinekit use
-author:         Michael Brown
-alias:          of:N*T*Cmachkt,hm2reg-io-1.0*
-depends:
-vermagic:       3.10.37-ltsi-rt37-05839-gd0c5abc SMP preempt mod_unload ARMv7 p2v8
diff --git a/SW/MK/kernel-drivers/README.md b/SW/MK/kernel-drivers/README.md
index ba5009c1..bb78eb4f 100644
--- a/SW/MK/kernel-drivers/README.md
+++ b/SW/MK/kernel-drivers/README.md
@@ -3,49 +3,61 @@ the hm2adc_uio-module is for now redundant. (not of use).
 
 hm2reg_uio-module is currently implemented in Machinekit via the hostmot2 hm2_soc driver.
 
-This documents the:
+This documents the inner ADC functionality:
 
-adcreg:  Driver module for the modded Nano Soc adc ip core. [relative link here](../../../HW/ip/ADC_LTC2308_FIFO/)
 
-adcfs:   c++ adc read test app:
+HAL hostmot2_ol:  Builtin Nano Soc adc ip core. [relative link here](../../../HW/QuartusProjects/Common/adc_ltc2308_fifo.s)
 
+when running the hm2_soc_ol driver with _adc=1
 
-usage examples:
+adc values show up as:
+hm2_5i25.0.nano_soc_adc.ch.0.out
+hm2_5i25.0.nano_soc_adc.ch.1.out
+hm2_5i25.0.nano_soc_adc.ch.2.out
+hm2_5i25.0.nano_soc_adc.ch.3.out
+hm2_5i25.0.nano_soc_adc.ch.4.out
+hm2_5i25.0.nano_soc_adc.ch.5.out
+hm2_5i25.0.nano_soc_adc.ch.6.out
+hm2_5i25.0.nano_soc_adc.ch.7.out
+in the hal
 
+mksocmemio:   c++ generic Hostmot2 memory read/write utility:
+
+
+manual usage examples:
 
-      # when driver not compiled into kernel.
-      sudo insmod adcreg.ko
 
       #---------- Single channel select --------------#
 
-      # set measure number (number of samples = 2047)
-      ./adcfs w 1 2047  # limit !
+      # set measure number (number of samples = 8)
+      mksocmemio -w 0x204 8  # limit = 2047 !
 
       # set sample channel 2 start (ch_nr << 1 | 0x001)
-      ./adcfs w 0 4
-      ./adcfs w 0 5
-      ./adcfs w 0 4
+      mksocmemio -w 0x204 1  fetch 1 sample
+      mksocmemio -w 0x200 4
+      .mksocmemio -w 0x200 5
 
       # read and print all sampled values to screen
-      ./adcfs a
+      mksocmemio -r 0x204 // 1 sample
 
       # set sample channel 0 start (ch_nr << 1 | 0x001)
-      ./adcfs w 0 0
-      ./adcfs w 0 1
-      ./adcfs w 0 0
+      mksocmemio -w 0x204 4  fetch 4 samples
+      mksocmemio -w 0x200 0
+      mksocmemio -w 0x200 1
 
       # read and print all sampled values to screen
-      ./adcfs a
+      mksocmemio -r 0x204 // each suggesive read command to this location shows the next sample
 
 
-      #---------- Auto channel select ----------------#
-      # set measure number (number of samples = 16)
-      ./adcfs w 1 16
+      #---------- Auto channel select mode ----------------#
+      #---------- this is the current mode the DExx hal adc ---------------#
+      # set measure number (number of samples = 8)
+      .mksocmemio -w 0x204 8
 
       # set sample channel 2 ready/start/ready and auto update bit(ch_nr << 1 | 0x00(0/1) | 0x010)
-      ./adcfs w 0 20
-      ./adcfs w 0 21
-      ./adcfs w 0 20
+      mksocmemio -w 0x200 0x0100
+      mksocmemio -w 0x200 0x0101  // start sampling
 
       # read and print all sampled values to screen
-      ./adcfs a
+      mksocmemio -r 0x204 // repeat 8 times to read all (8) samples
+
diff --git a/SW/MK/kernel-drivers/adcfs/.kdev4/adcfs.kdev4 b/SW/MK/kernel-drivers/adcfs/.kdev4/adcfs.kdev4
deleted file mode 100644
index ce67c2f6..00000000
--- a/SW/MK/kernel-drivers/adcfs/.kdev4/adcfs.kdev4
+++ /dev/null
@@ -1,12 +0,0 @@
-[Buildset]
-BuildItems=@Variant(\x00\x00\x00\t\x00\x00\x00\x00\x01\x00\x00\x00\x0b\x00\x00\x00\x00\x01\x00\x00\x00\n\x00a\x00d\x00c\x00f\x00s)
-
-[CustomDefinesAndIncludes][ProjectPath0]
-Defines=\x00\x00\x00\x00
-Includes=\x00\x00\x00\x05\x00\x00\x00°\x00/\x00h\x00o\x00m\x00e\x00/\x00m\x00i\x00b\x00/\x00D\x00e\x00v\x00e\x00l\x00o\x00p\x00m\x00e\x00n\x00t\x00/\x00B\x00e\x00t\x00a\x003\x00_\x00P\x00r\x00o\x00j\x00e\x00c\x00t\x00/\x00a\x00r\x00m\x00-\x00l\x00i\x00n\x00u\x00x\x00-\x00l\x00i\x00n\x00u\x00x\x00-\x003\x00.\x001\x000\x00-\x00g\x00n\x00u\x00e\x00a\x00b\x00i\x00f\x00h\x00-\x00k\x00e\x00r\x00n\x00e\x00l\x00/\x00l\x00i\x00n\x00u\x00x\x00/\x00i\x00n\x00c\x00l\x00u\x00d\x00e\x00/\x00\x00\x00â\x00/\x00h\x00o\x00m\x00e\x00/\x00m\x00i\x00b\x00/\x00D\x00e\x00v\x00e\x00l\x00o\x00p\x00m\x00e\x00n\x00t\x00/\x00B\x00e\x00t\x00a\x003\x00_\x00P\x00r\x00o\x00j\x00e\x00c\x00t\x00/\x00g\x00c\x00c\x00-\x00l\x00i\x00n\x00a\x00r\x00o\x00-\x00a\x00r\x00m\x00-\x00l\x00i\x00n\x00u\x00x\x00-\x00g\x00n\x00u\x00e\x00a\x00b\x00i\x00h\x00f\x00-\x004\x00.\x009\x00-\x002\x000\x001\x004\x00.\x000\x009\x00_\x00l\x00i\x00n\x00u\x00x\x00/\x00a\x00r\x00m\x00-\x00l\x00i\x00n\x00u\x00x\x00-\x00g\x00n\x00u\x00e\x00a\x00b\x00i\x00h\x00f\x00/\x00i\x00n\x00c\x00l\x00u\x00d\x00e\x00/\x00\x00\x00ö\x00/\x00h\x00o\x00m\x00e\x00/\x00m\x00i\x00b\x00/\x00D\x00e\x00v\x00e\x00l\x00o\x00p\x00m\x00e\x00n\x00t\x00/\x00B\x00e\x00t\x00a\x003\x00_\x00P\x00r\x00o\x00j\x00e\x00c\x00t\x00/\x00g\x00c\x00c\x00-\x00l\x00i\x00n\x00a\x00r\x00o\x00-\x00a\x00r\x00m\x00-\x00l\x00i\x00n\x00u\x00x\x00-\x00g\x00n\x00u\x00e\x00a\x00b\x00i\x00h\x00f\x00-\x004\x00.\x009\x00-\x002\x000\x001\x004\x00.\x000\x009\x00_\x00l\x00i\x00n\x00u\x00x\x00/\x00a\x00r\x00m\x00-\x00l\x00i\x00n\x00u\x00x\x00-\x00g\x00n\x00u\x00e\x00a\x00b\x00i\x00h\x00f\x00/\x00i\x00n\x00c\x00l\x00u\x00d\x00e\x00/\x00c\x00+\x00+\x00/\x004\x00.\x009\x00.\x002\x00/\x00\x00\x00ô\x00/\x00h\x00o\x00m\x00e\x00/\x00m\x00i\x00b\x00/\x00D\x00e\x00v\x00e\x00l\x00o\x00p\x00m\x00e\x00n\x00t\x00/\x00B\x00e\x00t\x00a\x003\x00_\x00P\x00r\x00o\x00j\x00e\x00c\x00t\x00/\x00g\x00c\x00c\x00-\x00l\x00i\x00n\x00a\x00r\x00o\x00-\x00a\x00r\x00m\x00-\x00l\x00i\x00n\x00u\x00x\x00-\x00g\x00n\x00u\x00e\x00a\x00b\x00i\x00h\x00f\x00-\x004\x00.\x009\x00-\x002\x000\x001\x004\x00.\x000\x009\x00_\x00l\x00i\x00n\x00u\x00x\x00/\x00a\x00r\x00m\x00-\x00l\x00i\x00n\x00u\x00x\x00-\x00g\x00n\x00u\x00e\x00a\x00b\x00i\x00h\x00f\x00/\x00l\x00i\x00b\x00c\x00/\x00u\x00s\x00r\x00/\x00i\x00n\x00c\x00l\x00u\x00d\x00e\x00/\x00\x00\x00þ\x00/\x00h\x00o\x00m\x00e\x00/\x00m\x00i\x00b\x00/\x00D\x00e\x00v\x00e\x00l\x00o\x00p\x00m\x00e\x00n\x00t\x00/\x00B\x00e\x00t\x00a\x003\x00_\x00P\x00r\x00o\x00j\x00e\x00c\x00t\x00/\x00g\x00c\x00c\x00-\x00l\x00i\x00n\x00a\x00r\x00o\x00-\x00a\x00r\x00m\x00-\x00l\x00i\x00n\x00u\x00x\x00-\x00g\x00n\x00u\x00e\x00a\x00b\x00i\x00h\x00f\x00-\x004\x00.\x009\x00-\x002\x000\x001\x004\x00.\x000\x009\x00_\x00l\x00i\x00n\x00u\x00x\x00/\x00l\x00i\x00b\x00/\x00g\x00c\x00c\x00/\x00a\x00r\x00m\x00-\x00l\x00i\x00n\x00u\x00x\x00-\x00g\x00n\x00u\x00e\x00a\x00b\x00i\x00h\x00f\x00/\x004\x00.\x009\x00.\x002\x00/\x00i\x00n\x00c\x00l\x00u\x00d\x00e\x00/
-Path=.
-
-[Defines And Includes][Compiler]
-Name=None
-Path=
-Type=
diff --git a/SW/MK/kernel-drivers/adcfs/Makefile b/SW/MK/kernel-drivers/adcfs/Makefile
deleted file mode 100644
index 77068569..00000000
--- a/SW/MK/kernel-drivers/adcfs/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-# obj := adcfs.o
-
-#KERNEL_SRC_DIR=/home/mib/Development/Projects/arm-linux-gnueabifh-kernel/linux
-#PWD=$(shell pwd)
-CROSS_C=/home/mib/Development/Beta3_Project/gcc-linaro-arm-linux-gnueabihf-4.9-2014.09_linux/bin/arm-linux-gnueabihf-
-CC=$(CROSS_C)g++
-
-all:  adcfs
-
-adcfs:  main.o adcfs.o
-	$(CC) -o adcfs main.o adcfs.o
-	
-main.o: main.cpp
-	$(CC) -c main.cpp
-
-adcfs.o: adcfs.cpp
-	$(CC) -c adcfs.cpp
-
-clean:
-	rm -rf *.o
-	rm -rf adcfs
diff --git a/SW/MK/kernel-drivers/adcfs/adcfs b/SW/MK/kernel-drivers/adcfs/adcfs
deleted file mode 100755
index 30da4219..00000000
Binary files a/SW/MK/kernel-drivers/adcfs/adcfs and /dev/null differ
diff --git a/SW/MK/kernel-drivers/adcfs/adcfs.cpp b/SW/MK/kernel-drivers/adcfs/adcfs.cpp
deleted file mode 100644
index 1ca4d0a1..00000000
--- a/SW/MK/kernel-drivers/adcfs/adcfs.cpp
+++ /dev/null
@@ -1,141 +0,0 @@
-#include "fpga.h"
-
-//#include <unistd.h>
-#include <sys/types.h>
-//#include <sys/ioctl.h>
-//#include <linux/i2c-dev.h>
-//#include <fcntl.h>
-
-#include <ios>
-#include <iostream>
-#include <fstream>
-#include <string>
-
-#define FILE_DEV "/sys/bus/platform/drivers/adcreg/adcreg"
-
-using namespace std;
-
-bool m_bInitSuccess; 
-
-FPGAFS::FPGAFS()// :
-//    m_bIsVideoEnabled(false)
-{
-    m_bInitSuccess = Init();
-    if (!m_bInitSuccess )
-        cout << "FPGAFS init failed!!!" "\n";
-    else
-        cout << "FPGAFS init success" << "\n ";
-}
-
-FPGAFS::~FPGAFS()
-{
-    close(fd);
-}
-
-bool FPGAFS::Init()
-{
-    bool bSuccess = false;
-    fstream fileB;
-    fileB.open(FILE_DEV);
-    if (fileB.is_open()){
-        bSuccess = true;
-        fileB.close();
-    }
-    return bSuccess;
-}
-
-int FPGAFS::adcregSize( void ){
-    int size = 0;
-//    ifstream file( FILE_DEV, ios::binary | ios::ate);
-    ifstream file( FILE_DEV, std::ios::binary);
-
-    // Stop eating new lines in binary mode!!!
-    file.unsetf(std::ios::skipws);
-
-    // get its size:
-    std::streampos fileSize;
-
-    file.seekg(0, std::ios::end);
-//    fileSize = file.tellg();
-    size = file.tellg();
-    file.seekg(0, std::ios::beg);
-    
-//    size = file.tellg();
-    
-    cout << "FPGAFS::adcregSize: page size = " << size << "\n";
-    file.close();
-//    if(size > 22) {std::cout << "!!! Size error \n \n" << "!!! Size error \n \n"; size = 22;}
-    return size;
-}
-
-int FPGAFS::adcregReadall( char** buf){
-    int insize = 0, size = 0, count = 0;
-    insize = adcregSize();
-    char* bufpoint = new char[insize];
-//    char c;
-    
-    ifstream in( FILE_DEV, ios::binary  | ios::ate);
-//    ifstream in( FILE_DEV, std::ios::binary);
-
-    // Stop eating new lines in binary mode!!!
-//    in.unsetf(std::ios::skipws);
-
-    in.seekg(0);
-    size = insize;
-
-//    in.seekg(0);
-    in.get(bufpoint,size);
-    *buf = bufpoint;
-    cout << "FPGAFS::adcregReadall: bufsize = " << size << "\n";
-    in.close();
-    return size;
-}
-
-char FPGAFS::adcregGet(unsigned int addr ){
-    int size = adcregSize();
-    char data[size];
-    if (m_bInitSuccess){
-       ifstream gin( FILE_DEV, ios::binary | ios::ate);
-        //        fileB.open(FILE_DEV);//
-//        ifstream file;
-/*        if (!fi.is_open())
-        {
-            cout<< "Failed to open /sys/bus/platform/drivers/hmreg/hmreg for reading\r\n";
-            return false;
-        }
-*/
-//      cout << "reading value \n";
-//        size = in.tellg(); 
-        gin.seekg (0);
-        gin.get(data,size);
-//        cout << "got value ... closing file \n";
-        gin.close();
-        //        value = alt_read_byte((void *) ( (u_int8_t *)synthreg_mem + ( ( uint32_t )( regaddr + SYNTHREG_OFFSET) & ( uint32_t )( HW_REGS_MASK ) )) );
-    }
-     return data[addr];
-}
-
-
-bool FPGAFS::adcregSet( u_int16_t addr, u_int16_t value ){
-    if (!m_bInitSuccess)
-        return false;
-    ofstream fileB( FILE_DEV, ios::binary | ios::ate);
-//    fileB.open(FILE_DEV);//
-    if (!fileB.is_open())
-    {
-        cout<< "Failed to open" << FILE_DEV << " for writing\r\n";
-        return false;
-    }
-    cout << "\n" << "in adcresSet addr = " << addr << "\tvalue = " << value << "\n";
-    fileB.seekp(0);
-//    fileB << addr << value;
-    fileB.put(addr & 0x00FF);
-    fileB.put((addr & 0xFF00) >> 8);
-    fileB.put(value & 0x00FF);
-    fileB.put((value & 0xFF00) >> 8);
-    fileB.close();
-    //   alt_write_byte((void *) ( (u_int8_t *)synthreg_mem + ( ( uint32_t )( regadr + SYNTHREG_OFFSET) & ( uint32_t )( HW_REGS_MASK ) )) , value );
-    return true;
-}
-
-
diff --git a/SW/MK/kernel-drivers/adcfs/adcfs.kdev4 b/SW/MK/kernel-drivers/adcfs/adcfs.kdev4
deleted file mode 100644
index fbe1d9d0..00000000
--- a/SW/MK/kernel-drivers/adcfs/adcfs.kdev4
+++ /dev/null
@@ -1,3 +0,0 @@
-[Project]
-Manager=KDevCustomMakeManager
-Name=adcfs
diff --git a/SW/MK/kernel-drivers/adcfs/fpga.h b/SW/MK/kernel-drivers/adcfs/fpga.h
deleted file mode 100644
index 1a5beebf..00000000
--- a/SW/MK/kernel-drivers/adcfs/fpga.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef FPGA_H
-#define FPGA_H
-
-#include <unistd.h>
-#include <stdbool.h>
-#include <sys/types.h>
-
-#define addr_size 32
-
-class FPGAFS
-{
-public:
-    FPGAFS();
-    ~FPGAFS();
-    int adcregSize( void );
-    int adcregReadall( char** );
-    char adcregGet( unsigned int addr );
-    bool adcregSet(u_int16_t , u_int16_t);
-
-
-protected:
-    bool m_bInitSuccess;
-    int fd;
-//    bool m_bIsVideoEnabled;
-//    u_int8_t *s_synthreg_base;
-    bool Init();
-
-};
-
-#endif // FPGA_H
diff --git a/SW/MK/kernel-drivers/adcfs/main.cpp b/SW/MK/kernel-drivers/adcfs/main.cpp
deleted file mode 100644
index 04db67c2..00000000
--- a/SW/MK/kernel-drivers/adcfs/main.cpp
+++ /dev/null
@@ -1,194 +0,0 @@
-#include <iostream>
-#include <sys/types.h>
-#include <stdlib.h>
-#include "fpga.h"
-#include <stdbool.h>
-#include <stdio.h>
-
-#include <string.h>
-
-using namespace std;
-
-bool ADC_LTC2308_Read(int, int, u_int16_t );
-
-bool ADC_LTC2308_Read(int ch, int nReadNum, u_int16_t szData[]){
-
-    u_int16_t Value;
-    int i;
-    bool bSuccess = false, set_success = false;
-    u_int32_t Timeout;
-    
-    FPGAFS fpga;
-    // set measure number (num of samples to run);
-    set_success = fpga.adcregSet(0x4,nReadNum);
-    if(set_success){
-	set_success = fpga.adcregSet(0x0,((ch << 1) | 0x0000));
-	set_success = fpga.adcregSet(0x0,((ch << 1) | 0x0001));
-	set_success = fpga.adcregSet(0x0,((ch << 1) | 0x0000));
-    }
-
-/*   
-    cout << "will now nReadnum \n";
-    fpga.adcregSet(0x01, nReadNum);
-
-    cout << "Starting measurement \n";
-    // start measure
-    fpga.adcregSet(0x00, (ch << 1) | 0x00);
-    fpga.adcregSet(0x00, (ch << 1) | 0x01);
-    fpga.adcregSet(0x00, (ch << 1) | 0x00);
-    
-    usleep(1);
-
-    // wait measure done
-//    Timeout = alt_nticks() + alt_ticks_per_second()/2;
-//    while ( ((fpga.adcregGet(0x00) & 0x01) == 0x00) && (alt_nticks() < Timeout)){
-    while ( fpga.adcregGet(0x00 & 0x01) == 0x00) {
-
-    }
-
-    if ((fpga.adcregGet(0x00) & 0x01) == 0x01) {
-	bSuccess = true;
-    }
-	// read adc value
-    if (bSuccess) {
-      for(i=0;i<nReadNum;i++) {
-	Value = fpga.adcregGet(0x01);
-	szData[i] = Value;
-	//printf("CH%d=%.3fV\r\n", ch, (float)Value/1000.0);
-      }
-      return bSuccess;
-    }
-*/
-    return set_success;
-}
-
-int main (int argc, char *argv[] ) {
-    cout << "\n#--------------------------------  Welcone to adcfs adc tester --------------------------#\n";
-    cout << "Input "<< argc << " Arguments::--> ";//  << " arguments:" << cout;
-    for (int i = 0; i < argc; ++i) {
-        cout<< argv[i] << " ";
-    }
-    cout << "\n";
-    
-    int ret = EXIT_FAILURE;
-    unsigned char  option;
-    u_int16_t value, offset;
-    int index;
-
-    int	nNum;
-    u_int16_t szAdcValue[10];
-    int nActiveChannel;
-    
-//    nActiveChannel = 3;
-    nNum = sizeof(szAdcValue)/sizeof(szAdcValue[0]);
-
-    FPGAFS fpga;
-    
-    if (argc >= 2) {
-        option = *argv[1];
-        if (option != 'w' && option != 'r' && option != 'a' && option != 'd') {
-            cout<< "Invalid option for 1 argument \n" <<
-            " a as argument displays all address values \n" << 
-            " d as argument displays adc value \n" << 
-            " r (read) + an address location displays a single location \n" << 
-            " w (write) + and arddress location + writes a single location \n";
-            exit(EXIT_FAILURE);
-//             cout<< "Invalid option setting. " <<
-//             "Option must be either r (read) or w (write)\n";
-//             exit(EXIT_FAILURE);
-        }
-    }
-    
-    if (argc == 2) {
-        option = *argv[1];
-        if ( option != 'a' ) {
-            cout<< "Invalid option for 1 argument \n" <<
-            " a as argument displays all address values \n" << 
-            " d as argument displays adc value \n" << 
-            " r (read) + an address location displays a single location \n" << 
-            " w (write) + and arddress location + writes a single location \n";
-            exit(EXIT_FAILURE);
-        }
-
-	if (option == 'a'){
-	    char* buf = NULL;
-	    u_int16_t s_word, s_val;
-//	    u_int8_t s_ch;
-	    int val;
-	    int readbuffsize = fpga.adcregReadall(& buf);
-	    u_int16_t info_word = ((buf[1] << 8) | buf[0]);
-	    u_int16_t num_samples = ((info_word >> 1) & 0x0FFF);
-	    u_int16_t s_ch = ((info_word >> 13) & 0x0007);
-	    
-	    cout << "\nOption a: Read " << readbuffsize << " bytes" << " Got " <<  num_samples << " samples from adc ch: " << s_ch << 
-	    " status word = 0x" << std::hex << info_word << " status bit = " << std::dec << (info_word & 1) << "\n";
-
-	    for(int j=1;j<num_samples+1;j++){
-		s_word = ((buf[(j*2)+1] << 8) | buf[j*2]);
-		s_val = (s_word & 0x0FFF);
-		s_ch = ((s_word >> 12) & 0x0007); 
-		cout <<"\n" << std::dec << j << "\t" << s_ch << "\t" << s_val << "\t" << std::hex << "0x" << s_val << "\n";
-//		cout <<"\n" << std::dec << j << "\t" << s_val << "\t" << std::hex << "0x" << s_val << "\n";
-	    }
-	    cout << "\n";
-        
-	    if(buf!=NULL)
-	    {
-		delete[] buf;
-	    }
-	}
-    }
-        
-    if (argc >= 3) {
-        // check the bounds of the address //
-	int address_reg = atol(argv[2]);
-	if (address_reg > 1) {
-	    cout << "Invalid address input. \n" <<
-	    "Address must be between 0 and " << 1 << " inclusive.\n";
-	    exit(EXIT_FAILURE);
-	}
-	offset = address_reg << 2;
-	cout<< "offset = " << offset << "\n";
-
-	if (argc == 3) {
-	    option = *argv[1];
-	    if ( option != 'r' ) {
-	      cout<< "Invalid option for 1 argument \n" <<
-		" a as argument displays all address values \n" << 
-		" d as argument displays adc value \n" << 
-		" r (read) + an address location displays a single location \n" << 
-		" w (write) + and arddress location + writes a single location \n";
-		exit(EXIT_FAILURE);
-	    }
-	    if (option == 'r') {
-		cout << "r option running \n";
-		char datavalue = fpga.adcregGet(offset);
-		int pval = datavalue;
-		cout << "\n Register " << offset << " Value = " << pval << " \n";
-	    }
-	}
-	else if (argc == 4) {
-	    // check the bounds of the value being set //
-	    value = atol(argv[3]);
-	    if (value > 4095) {
-		cout << "Invalid number setting. " <<
-		"Value must be between 0 and 4095, inclusive.\n";
-		exit(EXIT_FAILURE);
-	    }
-
-	    if (option == 'w') {
-		cout << "w option running \n";
-		char datavalue = fpga.adcregSet(offset,value);
-		int pval = datavalue;
-		cout << "\n Register " << offset << " Set Value = " << value << " adcregSet return value = "<< pval << " \n";
-	    }
-	    else if (option == 'd') {
-		cout << "d option running \n";
-		if (!ADC_LTC2308_Read(nActiveChannel, nNum, szAdcValue)) {
-		    cout<< "failed to read \n"; 
-		}
-	    }
-	}
-    }
-    cout << "\n#---------------------------------   End of adcfs adc tester  ---------------------------#\n";
-}
\ No newline at end of file
diff --git a/SW/MK/kernel-drivers/adcreg/.kdev4/_custom.kdev4 b/SW/MK/kernel-drivers/adcreg/.kdev4/_custom.kdev4
deleted file mode 100644
index a6e15fbb..00000000
--- a/SW/MK/kernel-drivers/adcreg/.kdev4/_custom.kdev4
+++ /dev/null
@@ -1,19 +0,0 @@
-[Containments][1]
-ActionPluginsSource=Global
-activity=adcreg
-activityId=
-desktop=-1
-formfactor=0
-geometry=0,0,1423,847
-immutability=1
-lastDesktop=-1
-lastScreen=0
-location=0
-orientation=2
-plugin=newspaper
-screen=0
-zvalue=0
-
-[Project]
-Manager=KDevCustomMakeManager
-Name=adcreg
diff --git a/SW/MK/kernel-drivers/adcreg/.kdev4/adcreg.kdev4 b/SW/MK/kernel-drivers/adcreg/.kdev4/adcreg.kdev4
deleted file mode 100644
index 6f83cac3..00000000
--- a/SW/MK/kernel-drivers/adcreg/.kdev4/adcreg.kdev4
+++ /dev/null
@@ -1,12 +0,0 @@
-[Buildset]
-BuildItems=@Variant(\x00\x00\x00\t\x00\x00\x00\x00\x01\x00\x00\x00\x0b\x00\x00\x00\x00\x01\x00\x00\x00\x0c\x00a\x00d\x00c\x00r\x00e\x00g)
-
-[CustomDefinesAndIncludes][ProjectPath0]
-Defines=\x00\x00\x00\x00
-Includes=\x00\x00\x00\x03\x00\x00\x00f\x00/\x00h\x00o\x00m\x00e\x00/\x00m\x00i\x00b\x00/\x00D\x00e\x00v\x00e\x00l\x00o\x00p\x00m\x00e\x00n\x00t\x00/\x00B\x00e\x00t\x00a\x003\x00_\x00P\x00r\x00o\x00j\x00e\x00c\x00t\x00/\x00m\x00a\x00c\x00h\x00i\x00n\x00e\x00k\x00i\x00t\x00/\x00s\x00r\x00c\x00/\x00\x00\x00º\x00/\x00h\x00o\x00m\x00e\x00/\x00m\x00i\x00b\x00/\x00D\x00e\x00v\x00e\x00l\x00o\x00p\x00m\x00e\x00n\x00t\x00/\x00t\x00e\x00s\x00t\x00-\x00P\x00r\x00o\x00j\x00/\x00a\x00r\x00m\x00-\x00l\x00i\x00n\x00u\x00x\x00-\x00l\x00i\x00n\x00u\x00x\x00-\x003\x00.\x001\x000\x00-\x00g\x00n\x00u\x00e\x00a\x00b\x00i\x00f\x00h\x00-\x00k\x00e\x00r\x00n\x00e\x00l\x00/\x00l\x00i\x00n\x00u\x00x\x00/\x00a\x00r\x00c\x00h\x00/\x00a\x00r\x00m\x00/\x00i\x00n\x00c\x00l\x00u\x00d\x00e\x00/\x00\x00\x00°\x00/\x00h\x00o\x00m\x00e\x00/\x00m\x00i\x00b\x00/\x00D\x00e\x00v\x00e\x00l\x00o\x00p\x00m\x00e\x00n\x00t\x00/\x00B\x00e\x00t\x00a\x003\x00_\x00P\x00r\x00o\x00j\x00e\x00c\x00t\x00/\x00a\x00r\x00m\x00-\x00l\x00i\x00n\x00u\x00x\x00-\x00l\x00i\x00n\x00u\x00x\x00-\x003\x00.\x001\x000\x00-\x00g\x00n\x00u\x00e\x00a\x00b\x00i\x00f\x00h\x00-\x00k\x00e\x00r\x00n\x00e\x00l\x00/\x00l\x00i\x00n\x00u\x00x\x00/\x00i\x00n\x00c\x00l\x00u\x00d\x00e\x00/
-Path=.
-
-[Defines And Includes][Compiler]
-Name=None
-Path=
-Type=
diff --git a/SW/MK/kernel-drivers/adcreg/Makefile b/SW/MK/kernel-drivers/adcreg/Makefile
deleted file mode 100644
index f61e9d70..00000000
--- a/SW/MK/kernel-drivers/adcreg/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-obj-m := adcreg.o
-
-KERNEL_SRC_DIR=/home/mib/Development/Beta3_Project/arm-linux-linux-3.10-gnueabifh-kernel/linux
-PWD=$(shell pwd)
-CROSS_C="/home/mib/Development/Beta3_Project/gcc-linaro-arm-linux-gnueabihf-4.9-2014.09_linux/bin/arm-linux-gnueabihf-"
-//NCORES=`nproc`
-NCORES=1
-
-all:
-	make -j$(NCORES) ARCH=arm CROSS_COMPILE=$(CROSS_C) -C $(KERNEL_SRC_DIR) M=$(PWD) modules
-
-clean:
-	make -j$(NCORES) ARCH=arm CROSS_COMPILE=$(CROSS_C) -C $(KERNEL_SRC_DIR) M=$(PWD) clean
diff --git a/SW/MK/kernel-drivers/adcreg/adcreg.c b/SW/MK/kernel-drivers/adcreg/adcreg.c
deleted file mode 100644
index e48a7d1a..00000000
--- a/SW/MK/kernel-drivers/adcreg/adcreg.c
+++ /dev/null
@@ -1,149 +0,0 @@
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/uaccess.h>
-#include <linux/ioport.h>
-#include <linux/io.h>
-
-#define adcreg_BASE 0xff250000
-
-//#define PRINT_INFO
-
-void *adcreg_mem;
-
-static struct device_driver adcreg_driver = {
-	.name = "adcreg",
-	.bus = &platform_bus_type,
-};
-
-
-static ssize_t adcreg_show(struct device_driver *drv, char *buf)
-{
- 	u16 bufindex, data_size, length,file_length, count;
-	u16 indata, sample_count, s_ch;
-	u16 measure_fifo_done;
-
-	indata =  ioread16(adcreg_mem);
-	measure_fifo_done = (indata & 0x0001);
-	sample_count = ((indata >> 1) & 0x0FFF);
-	s_ch = ((indata >> 13) & 0x0007);
-#ifdef PRINT_INFO
-	printk("\n \nadcreg_show_1: status = %u\ts_ch = %u\tsample_count = %u\n",measure_fifo_done,s_ch,sample_count);
-#endif
-
-	data_size = sizeof(indata);
-
-#ifdef PRINT_INFO
-	printk("\nadcreg_show_2: initial buf width = %u bytes\t mem pointer width = %u\n", data_size, sizeof(adcreg_mem));
-#endif
-	if(measure_fifo_done){
-	    length = (sample_count * data_size);
-	    file_length = length + data_size;
-#ifdef PRINT_INFO
-	    printk("\nadcreg_show_3: length = %u\n", length);
-#endif
-	    buf[0] = (indata & 0xFF); buf[1] = (indata >> 8);
-	    count = 0;
-	    for (bufindex=data_size;bufindex < file_length;bufindex=bufindex+data_size)
-	    {
-                indata =  ioread16(adcreg_mem + 4);
-		buf[bufindex] = (indata & 0xFF); buf[bufindex+1] = (indata >> 8); count++;
-#ifdef PRINT_INFO
-		printk("\nWrote to bufindex --> %u \t Databyte  = 0x%04x \n \n", bufindex, indata);
-#endif
-	    }
-
-#ifdef PRINT_INFO
-	    printk("\nadcreg_show_4: wrote %u samples\n",count);
-#endif
-#ifdef PRINT_INFO
-	    for (bufindex=0;bufindex < file_length;bufindex=bufindex+data_size)
-	    {
-		printk("\nData_index --> %u \t Highbyte, Lowbyte  = 0x%02x%02x \n \n", (bufindex >> 1), buf[bufindex+1], buf[bufindex]);
-	    }
-#endif
-	}
-	else {
-	  buf[0] = (indata & 0xFF); buf[1] = (indata >> 8);
-	  file_length = data_size;
-	}
-	return file_length;
-}
-
-static ssize_t adcreg_store(struct device_driver *drv, const char *buf, size_t count)
-{
-	u16 setadr, setdata;
-
-	if (buf == NULL) {
-		pr_err("Error, string must not be NULL\n");
-		return -EINVAL;
-	}
-#ifdef PRINT_INFO
-	printk("adcreg_store:  Data reveived by adcreg count = %u \n", count);
-#endif
-//	setadr = buf[0] + (buf[1] << 8);
-	setadr = (buf[0] & 0x07);
-	setdata = (buf[2] + (buf[3] << 8));
-
-#ifdef PRINT_INFO
-	printk("\nAddress %u\t will be written with %u  0x%04x  \n", setadr, setdata, setdata);
-#endif
-	iowrite16(setdata, adcreg_mem + setadr);
-	return count;
-}
-
-static DRIVER_ATTR(adcreg , (S_IWUSR | S_IRUSR | S_IRGRP | S_IWGRP |  S_IROTH | S_IWOTH), adcreg_show, adcreg_store);
-
-MODULE_AUTHOR("Michael Brown");
-MODULE_DESCRIPTION("Terasic adc_ltc2308_fifo ip core driver developed for Machinekit use");
-MODULE_LICENSE("GPL v2");
-//MODULE_ALIAS("platform:" DRIVER_NAME);
-
-static int __init adcreg_init(void)
-{
-	int ret;
-	struct resource *res;
-
-	ret = driver_register(&adcreg_driver);
-	if (ret < 0)
-		return ret;
-
-	ret = driver_create_file(&adcreg_driver, &driver_attr_adcreg);
-	if (ret < 0) {
-		driver_unregister(&adcreg_driver);
-		return ret;
-	}
-
-        res = request_mem_region(adcreg_BASE, PAGE_SIZE, "adcreg");
-	if (res == NULL) {
-		driver_remove_file(&adcreg_driver, &driver_attr_adcreg);
-		driver_unregister(&adcreg_driver);
-		return -EBUSY;
-	}
-
-	adcreg_mem = ioremap(adcreg_BASE , PAGE_SIZE);
-	if (adcreg_mem == NULL) {
-		driver_remove_file(&adcreg_driver, &driver_attr_adcreg);
-		driver_unregister(&adcreg_driver);
-		release_mem_region(adcreg_BASE, PAGE_SIZE);
-		return -EFAULT;
-	}
-
-	return 0;
-}
-
-static void __exit adcreg_exit(void)
-{
-	driver_remove_file(&adcreg_driver, &driver_attr_adcreg);
-	driver_unregister(&adcreg_driver);
-	release_mem_region(adcreg_BASE, PAGE_SIZE);
-	iounmap(adcreg_mem);
-}
-
-module_init(adcreg_init);
-module_exit(adcreg_exit);
-
-MODULE_LICENSE("Dual BSD/GPL");
diff --git a/SW/MK/kernel-drivers/adcreg/adcreg.kdev4 b/SW/MK/kernel-drivers/adcreg/adcreg.kdev4
deleted file mode 100644
index 52b7b57a..00000000
--- a/SW/MK/kernel-drivers/adcreg/adcreg.kdev4
+++ /dev/null
@@ -1,3 +0,0 @@
-[Project]
-Manager=KDevCustomMakeManager
-Name=adcreg
diff --git a/SW/MK/kernel-drivers/hm2adc_uio-module/.kdev4/hm2adc_uio-module.kdev4 b/SW/MK/kernel-drivers/hm2adc_uio-module/.kdev4/hm2adc_uio-module.kdev4
deleted file mode 100644
index 4ea25102..00000000
--- a/SW/MK/kernel-drivers/hm2adc_uio-module/.kdev4/hm2adc_uio-module.kdev4
+++ /dev/null
@@ -1,7 +0,0 @@
-[Buildset]
-BuildItems=@Variant(\x00\x00\x00\t\x00\x00\x00\x00\x01\x00\x00\x00\x0b\x00\x00\x00\x00\x01\x00\x00\x00"\x00h\x00m\x002\x00a\x00d\x00c\x00_\x00u\x00i\x00o\x00-\x00m\x00o\x00d\x00u\x00l\x00e)
-
-[Defines And Includes][Compiler]
-Name=GCC
-Path=gcc
-Type=GCC
diff --git a/SW/MK/kernel-drivers/hm2adc_uio-module/.kdev4/hm2reg_uio-module.kdev4 b/SW/MK/kernel-drivers/hm2adc_uio-module/.kdev4/hm2reg_uio-module.kdev4
deleted file mode 100644
index 13d74be5..00000000
--- a/SW/MK/kernel-drivers/hm2adc_uio-module/.kdev4/hm2reg_uio-module.kdev4
+++ /dev/null
@@ -1,12 +0,0 @@
-[Buildset]
-BuildItems=@Variant(\x00\x00\x00\t\x00\x00\x00\x00\x00)
-
-[CustomDefinesAndIncludes][ProjectPath0]
-Defines=\x00\x00\x00\x00
-Includes=\x00\x00\x00\x01\x00\x00\x00�\x00/\x00h\x00o\x00m\x00e\x00/\x00m\x00i\x00b\x00/\x00D\x00e\x00v\x00e\x00l\x00o\x00p\x00m\x00e\x00n\x00t\x00/\x00P\x00r\x00o\x00j\x00e\x00c\x00t\x00s\x00/\x00a\x00r\x00m\x00-\x00l\x00i\x00n\x00u\x00x\x00-\x00g\x00n\x00u\x00e\x00a\x00b\x00i\x00f\x00h\x00-\x00k\x00e\x00r\x00n\x00e\x00l\x00/\x00l\x00i\x00n\x00u\x00x\x00/\x00i\x00n\x00c\x00l\x00u\x00d\x00e\x00/
-Path=.
-
-[Defines And Includes][Compiler]
-Name=GCC
-Path=gcc
-Type=GCC
diff --git a/SW/MK/kernel-drivers/hm2adc_uio-module/Kbuild b/SW/MK/kernel-drivers/hm2adc_uio-module/Kbuild
deleted file mode 100644
index 58332d9e..00000000
--- a/SW/MK/kernel-drivers/hm2adc_uio-module/Kbuild
+++ /dev/null
@@ -1 +0,0 @@
-obj-m  := hm2adc_uio-module.o
diff --git a/SW/MK/kernel-drivers/hm2adc_uio-module/Makefile b/SW/MK/kernel-drivers/hm2adc_uio-module/Makefile
deleted file mode 100644
index ebe891e3..00000000
--- a/SW/MK/kernel-drivers/hm2adc_uio-module/Makefile
+++ /dev/null
@@ -1,46 +0,0 @@
-KERNEL_SRC_DIR=/home/mib/Development/test-Proj/arm-linux-linux-3.10-gnueabifh-kernel/linux/
-CURDIR=$(shell pwd)
-CROSS_C="/home/mib/Development/test-Proj/gcc-linaro-arm-linux-gnueabihf-4.9-2014.09_linux/bin/arm-linux-gnueabihf-"
-ARCH=arm
-
-OUT_DIR =$(KERNEL_SRC_DIR)
-
-//NCORES=`nproc`
-NCORES=1
-
-
-
-#LINUX_VARIABLES = PATH=$(PATH)
-LINUX_VARIABLES = ARCH=$(ARCH)
-ifneq ("$(KBUILD_BUILD_VERSION)","")
-	LINUX_VARIABLES += KBUILD_BUILD_VERSION="$(KBUILD_BUILD_VERSION)" 
-endif
-LINUX_VARIABLES += CROSS_COMPILE=$(CROSS_C)
-
-#ifneq ("$(DEVICETREE_SRC)","")
-#	LINUX_VARIABLES += CONFIG_DTB_SOURCE=$(DEVICETREE_SRC)
-#endif
-#LINUX_VARIABLES += INSTALL_MOD_PATH=$(INSTALL_MOD_PATH)
-
-
-ifndef OUT_DIR
-    $(error OUT_DIR is undefined, bad environment, you point OUT_DIR to the linux kernel build output directory)
-endif
-
-KDIR ?= $(OUT_DIR)
-
-default:
-	$(MAKE) -j$(NCORES) $(LINUX_VARIABLES) -C $(KDIR) M=$(CURDIR)
-
-clean:
-	$(MAKE) -C $(KDIR) $(LINUX_VARIABLES) M=$(CURDIR) clean
-
-help:
-	$(MAKE) -C $(KDIR) $(LINUX_VARIABLES) M=$(CURDIR) help
-
-modules:
-	$(MAKE) -j$(NCORES) $(LINUX_VARIABLES) -C $(KDIR) M=$(CURDIR) modules
-
-modules_install:
-	$(MAKE) -C $(KDIR) $(LINUX_VARIABLES) M=$(CURDIR) modules_install
-
diff --git a/SW/MK/kernel-drivers/hm2adc_uio-module/Makefile.tar.gz b/SW/MK/kernel-drivers/hm2adc_uio-module/Makefile.tar.gz
deleted file mode 100644
index 4653e735..00000000
Binary files a/SW/MK/kernel-drivers/hm2adc_uio-module/Makefile.tar.gz and /dev/null differ
diff --git a/SW/MK/kernel-drivers/hm2adc_uio-module/hm2adc_uio-module.c b/SW/MK/kernel-drivers/hm2adc_uio-module/hm2adc_uio-module.c
deleted file mode 100644
index 206c6659..00000000
--- a/SW/MK/kernel-drivers/hm2adc_uio-module/hm2adc_uio-module.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * drivers/uio/uio_pdrv_genirq.c
- *
- * Userspace I/O platform driver with generic IRQ handling code.
- *
- * Copyright (C) 2008 Magnus Damm
- *
- * Based on uio_pdrv.c by Uwe Kleine-Koenig,
- * Copyright (C) 2008 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/uio_driver.h>
-#include <linux/spinlock.h>
-#include <linux/bitops.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/stringify.h>
-#include <linux/pm_runtime.h>
-#include <linux/slab.h>
-
-#include <linux/of.h>
-#include <linux/of_platform.h>
-#include <linux/of_address.h>
-
-#define DRIVER_NAME "hm2adc"
-
-struct uio_pdrv_genirq_platdata {
-    struct uio_info *uioinfo;
-    spinlock_t lock;
-    unsigned long flags;
-    struct platform_device *pdev;
-};
-
-/* Bits in uio_pdrv_genirq_platdata.flags */
-enum {
-            UIO_IRQ_DISABLED = 1,
-};
-    
-
-static int uio_pdrv_genirq_open(struct uio_info *info, struct inode *inode)
-{
-    struct uio_pdrv_genirq_platdata *priv = info->priv;
-    
-    /* Wait until the Runtime PM code has woken up the device */
-    pm_runtime_get_sync(&priv->pdev->dev);
-    return 0;
-}
-
-static int uio_pdrv_genirq_release(struct uio_info *info, struct inode *inode)
-{
-    struct uio_pdrv_genirq_platdata *priv = info->priv;
-    
-    /* Tell the Runtime PM code that the device has become idle */
-    pm_runtime_put_sync(&priv->pdev->dev);
-    return 0;
-}
-
-static irqreturn_t uio_pdrv_genirq_handler(int irq, struct uio_info *dev_info)
-{
-    struct uio_pdrv_genirq_platdata *priv = dev_info->priv;
-    
-    /* Just disable the interrupt in the interrupt controller, and
-     * remember the state so we can allow user space to enable it later.
-     */
-    
-    if (!test_and_set_bit(0, &priv->flags))
-        disable_irq_nosync(irq);
-    
-    return IRQ_HANDLED;
-}
-
-static int uio_pdrv_genirq_irqcontrol(struct uio_info *dev_info, s32 irq_on)
-{
-    struct uio_pdrv_genirq_platdata *priv = dev_info->priv;
-    unsigned long flags;
-    
-    /* Allow user space to enable and disable the interrupt
-     * in the interrupt controller, but keep track of the
-     * state to prevent per-irq depth damage.
-     *
-     * Serialize this operation to support multiple tasks.
-     */
-    
-    spin_lock_irqsave(&priv->lock, flags);
-    if (irq_on) {
-        if (test_and_clear_bit(0, &priv->flags))
-            enable_irq(dev_info->irq);
-    } else {
-        if (!test_and_set_bit(0, &priv->flags))
-            disable_irq(dev_info->irq);
-    }
-    spin_unlock_irqrestore(&priv->lock, flags);
-    
-    return 0;
-}
-
-static int uio_pdrv_hm2adc_io_probe(struct platform_device *pdev)
-{
-    struct uio_info *uioinfo = pdev->dev.platform_data;
-    struct uio_pdrv_genirq_platdata *priv;
-    struct uio_mem *uiomem;
-    int ret = -EINVAL;
-    int i;
-    
-    if (pdev->dev.of_node) {
-        int irq;
-        
-        /* alloc uioinfo for one device */
-        uioinfo = kzalloc(sizeof(*uioinfo), GFP_KERNEL);
-        if (!uioinfo) {
-            ret = -ENOMEM;
-            dev_err(&pdev->dev, "unable to kmalloc\n");
-            goto bad2;
-        }
-        uioinfo->name = pdev->dev.of_node->name;
-        uioinfo->version = "devicetree";
-        
-        /* Multiple IRQs are not supported */
-        irq = platform_get_irq(pdev, 0);
-        if (irq == -ENXIO)
-            uioinfo->irq = UIO_IRQ_NONE;
-        else
-            uioinfo->irq = irq;
-    }
-    
-    if (!uioinfo || !uioinfo->name || !uioinfo->version) {
-        dev_err(&pdev->dev, "missing platform_data\n");
-        goto bad0;
-    }
-    
-    if (uioinfo->handler || uioinfo->irqcontrol ||
-        uioinfo->irq_flags & IRQF_SHARED) {
-        dev_err(&pdev->dev, "interrupt configuration error\n");
-    goto bad0;
-        }
-        
-        priv = kzalloc(sizeof(*priv), GFP_KERNEL);
-        if (!priv) {
-            ret = -ENOMEM;
-            dev_err(&pdev->dev, "unable to kmalloc\n");
-            goto bad0;
-        }
-        
-        priv->uioinfo = uioinfo;
-        spin_lock_init(&priv->lock);
-        priv->flags = 0; /* interrupt is enabled to begin with */
-        priv->pdev = pdev;
-        
-        if (!uioinfo->irq) {
-            ret = platform_get_irq(pdev, 0);
-            if (ret < 0) {
-                dev_err(&pdev->dev, "setting: uioinfo->irq = UIO_IRQ_NONE \n");
-//                goto bad0;
-                uioinfo->irq = UIO_IRQ_NONE;
-                
-            }
-//            uioinfo->irq = ret;
-        }
-        uiomem = &uioinfo->mem[0];
-        
-        for (i = 0; i < pdev->num_resources; ++i) {
-            struct resource *r = &pdev->resource[i];
-            
-            if (r->flags != IORESOURCE_MEM)
-                continue;
-            
-            if (uiomem >= &uioinfo->mem[MAX_UIO_MAPS]) {
-                dev_warn(&pdev->dev, "device has more than "
-                __stringify(MAX_UIO_MAPS)
-                " I/O memory resources.\n");
-                break;
-            }
-            
-            uiomem->memtype = UIO_MEM_PHYS;
-            uiomem->addr = r->start;
-            uiomem->size = resource_size(r);
-            uiomem->name = r->name;
-            ++uiomem;
-        }
-        
-        while (uiomem < &uioinfo->mem[MAX_UIO_MAPS]) {
-            uiomem->size = 0;
-            ++uiomem;
-        }
-        
-        /* This driver requires no hardware specific kernel code to handle
-         * interrupts. Instead, the interrupt handler simply disables the
-         * interrupt in the interrupt controller. User space is responsible
-         * for performing hardware specific acknowledge and re-enabling of
-         * the interrupt in the interrupt controller.
-         *
-         * Interrupt sharing is not supported.
-         */
-        
-        uioinfo->handler = uio_pdrv_genirq_handler;
-        uioinfo->irqcontrol = uio_pdrv_genirq_irqcontrol;
-        uioinfo->open = uio_pdrv_genirq_open;
-        uioinfo->release = uio_pdrv_genirq_release;
-        uioinfo->priv = priv;
-        
-        /* Enable Runtime PM for this device:
-         * The device starts in suspended state to allow the hardware to be
-         * turned off by default. The Runtime PM bus code should power on the
-         * hardware and enable clocks at open().
-         */
-        pm_runtime_enable(&pdev->dev);
-        
-        ret = uio_register_device(&pdev->dev, priv->uioinfo);
-        if (ret) {
-            dev_err(&pdev->dev, "unable to register uio device\n");
-            goto bad1;
-        }
-        
-        platform_set_drvdata(pdev, priv);
-        return 0;
-        bad1:
-        kfree(priv);
-        pm_runtime_disable(&pdev->dev);
-        bad0:
-        /* kfree uioinfo for OF */
-        if (pdev->dev.of_node)
-            kfree(uioinfo);
-        bad2:
-        return ret;
-}
-
-static int uio_pdrv_hm2adc_io_remove(struct platform_device *pdev)
-{
-    struct uio_pdrv_genirq_platdata *priv = platform_get_drvdata(pdev);
-    
-    uio_unregister_device(priv->uioinfo);
-    pm_runtime_disable(&pdev->dev);
-    
-    priv->uioinfo->handler = NULL;
-    priv->uioinfo->irqcontrol = NULL;
-    
-    /* kfree uioinfo for OF */
-    if (pdev->dev.of_node)
-        kfree(priv->uioinfo);
-    
-    kfree(priv);
-    return 0;
-}
-
-static int uio_pdrv_genirq_runtime_nop(struct device *dev)
-{
-    /* Runtime PM callback shared between ->runtime_suspend()
-     * and ->runtime_resume(). Simply returns success.
-     *
-     * In this driver pm_runtime_get_sync() and pm_runtime_put_sync()
-     * are used at open() and release() time. This allows the
-     * Runtime PM code to turn off power to the device while the
-     * device is unused, ie before open() and after release().
-     *
-     * This Runtime PM callback does not need to save or restore
-     * any registers since user space is responsbile for hardware
-     * register reinitialization after open().
-     */
-    return 0;
-}
-
-static const struct dev_pm_ops uio_pdrv_genirq_dev_pm_ops = {
-    .runtime_suspend = uio_pdrv_genirq_runtime_nop,
-    .runtime_resume = uio_pdrv_genirq_runtime_nop,
-};
-
-#ifdef CONFIG_OF
-static const struct of_device_id uio_of_genirq_match[] = {
-    { .compatible = "machkt,adc-io-1.1", },
-    { }
-};
-MODULE_DEVICE_TABLE(of, uio_of_genirq_match);
-#else
-# define uio_of_genirq_match NULL
-#endif
-
-static struct platform_driver hm2adc_uio = {
-    .probe = uio_pdrv_hm2adc_io_probe,
-    .remove = uio_pdrv_hm2adc_io_remove,
-    .driver = {
-        .name = DRIVER_NAME,
-        .owner = THIS_MODULE,
-        .pm = &uio_pdrv_genirq_dev_pm_ops,
-        .of_match_table = uio_of_genirq_match,
-    },
-};
-
-module_platform_driver(hm2adc_uio);
-
-MODULE_AUTHOR("Michael Brown");
-MODULE_DESCRIPTION("ADC Userspace I/O platform driver with generic IRQ handling developed for Machinekit use");
-MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/SW/MK/kernel-drivers/hm2adc_uio-module/hm2adc_uio-module.kdev4 b/SW/MK/kernel-drivers/hm2adc_uio-module/hm2adc_uio-module.kdev4
deleted file mode 100644
index 3117c0a0..00000000
--- a/SW/MK/kernel-drivers/hm2adc_uio-module/hm2adc_uio-module.kdev4
+++ /dev/null
@@ -1,3 +0,0 @@
-[Project]
-Manager=KDevCustomMakeManager
-Name=hm2adc_uio-module
diff --git a/SW/MK/kernel-drivers/socfpga_defconfig b/SW/MK/kernel-drivers/socfpga_defconfig
deleted file mode 100644
index 647c06e1..00000000
--- a/SW/MK/kernel-drivers/socfpga_defconfig
+++ /dev/null
@@ -1,197 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CGROUPS=y
-CONFIG_CPUSETS=y
-CONFIG_NAMESPACES=y
-CONFIG_EMBEDDED=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_HOTPLUG=y
-CONFIG_UIO=y
-CONFIG_UIO_PDRV=y
-CONFIG_UIO_PDRV_GENIRQ=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SOCFPGA=y
-CONFIG_MACH_SOCFPGA_CYCLONE5=y
-# CONFIG_FPGA_SDRAM is not set
-CONFIG_ARM_THUMBEE=y
-# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
-CONFIG_SMP=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_VMSPLIT_2G=y
-CONFIG_NR_CPUS=2
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE=""
-CONFIG_VFP=y
-CONFIG_NEON=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_CAN=y
-CONFIG_CAN_RAW=y
-CONFIG_CAN_BCM=y
-CONFIG_CAN_GW=y
-CONFIG_CAN_DEV=y
-CONFIG_CAN_CALC_BITTIMING=y
-CONFIG_CAN_C_CAN=y
-CONFIG_CAN_C_CAN_PLATFORM=y
-CONFIG_CAN_DEBUG_DEVICES=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_DENALI=y
-CONFIG_MTD_NAND_DENALI_DT=y
-CONFIG_PROC_DEVICETREE=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=2
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_STMMAC_ETH=y
-# CONFIG_STMMAC_PHY_ID_ZERO_WORKAROUND is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_AMBAKMI=y
-CONFIG_LEGACY_PTY_COUNT=16
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=2
-CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_SERIAL_8250_DW=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_LIBCOMPOSITE=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_PHY=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_GENERIC_PHY=y
-CONFIG_USB_DWC2=y
-CONFIG_MMC=y
-CONFIG_MMC_DW=y
-CONFIG_MMC_DW_IDMAC=y
-CONFIG_MMC_DW_SOCFPGA=y
-CONFIG_SPI=y
-CONFIG_SPI_CADENCE_QSPI=y
-CONFIG_SPI_DESIGNWARE=y
-CONFIG_SPI_DW_PL330_DMA=y
-CONFIG_SPI_DW_MMIO=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_DWAPB=y
-CONFIG_GPIO_ALTERA=m
-CONFIG_GPIO_A10SYCON=y
-CONFIG_SENSORS_A10SYCON=y
-CONFIG_SENSORS_MAX1619=y
-CONFIG_PMBUS=y
-CONFIG_SENSORS_LTC2978=y
-# CONFIG_RTC_HCTOSYS is not set
-CONFIG_WATCHDOG=y
-CONFIG_DW_WATCHDOG=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT4_FS=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY_USER=y
-CONFIG_VFAT_FS=y
-CONFIG_NTFS_FS=y
-CONFIG_NTFS_RW=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_INFO=y
-CONFIG_ENABLE_DEFAULT_TRACERS=y
-CONFIG_DEBUG_USER=y
-CONFIG_XZ_DEC=y
-CONFIG_I2C=y
-CONFIG_I2C_DESIGNWARE_CORE=y
-CONFIG_I2C_DESIGNWARE_PLATFORM=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_NEWHAVEN_LCD=y
-CONFIG_EEPROM_AT24=y
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V2=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFS_USE_KERNEL_DNS=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_FPGA=y
-CONFIG_FPGA_MGR_ALTERA=y
-CONFIG_FPGA_MGR_SOCFPGA_A10=y
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_COMMON_CLK_DEBUG=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_TRACER=y
-CONFIG_FUNCTION_TRACER=y
-CONFIG_FUNCTION_GRAPH_TRACER=y
-CONFIG_DYNAMIC_FTRACE=y
-CONFIG_FTRACE_MCOUNT_RECORD=y
-CONFIG_OLD_MCOUNT=y
-CONFIG_FPGA_BRIDGE=y
-CONFIG_ALTERA_SOCFPGA_BRIDGE=y
-CONFIG_SIGNALFD=y
-CONFIG_VLAN_8021Q=y
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_GARP=y
-CONFIG_IPV6=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_SRAM=y
-CONFIG_PPS=y
-CONFIG_NETWORK_PHY_TIMESTAMPING=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPT_RT=y
-CONFIG_PREEMPT_RT_FULL=y
-CONFIG_MARVELL_PHY=y
-CONFIG_FHANDLE=y
diff --git a/SW/MK/mksocmemio/Makefile b/SW/MK/mksocmemio/Makefile
deleted file mode 100644
index 29aeb0ae..00000000
--- a/SW/MK/mksocmemio/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-TARGET = mksocmemio
-
-SOCEDS_DEST_ROOT = /home/mib/altera/15.1/embedded
-HWLIBS_ROOT = /home/mib/altera/15.1/embedded/ip/altera/hps/altera_hps/hwlib/
-CROSS_COMPILE := /home/mib/Development/Projects/gcc-linaro-arm-linux-gnueabihf-4.9-2014.09_linux/bin/arm-linux-gnueabihf-
-ALT_DEVICE_FAMILY ?= soc_cv_av
-
-CFLAGS := -g $(OFLAG) -Wall -Werror -std=c99 $(MULTILIBFLAGS) -I$(HWLIBS_ROOT)/include -I$(HWLIBS_ROOT)/include/$(ALT_DEVICE_FAMILY) -D$(ALT_DEVICE_FAMILY)
-ALL_HWLIBS_SRC = $(wildcard $(HWLIBS_ROOT)/src/hwmgr/*.c) $(wildcard $(HWLIBS_ROOT)/src/hwmgr/$(ALT_DEVICE_FAMILY)/*.c $(wildcard $(HWLIBS_ROOT)/src/utils/*.c))
-
-LDFLAGS =  -g -Wall
-CC = $(CROSS_COMPILE)gcc
-ARCH= arm
-
-all:  $(TARGET)
-
-build: $(TARGET)
-$(TARGET): $(TARGET).o
-	$(CC) $(LDFLAGS)   $^ -o $@
-%.o : %.c
-	$(CC) $(CFLAGS) -c $< -o $@
-
-.PHONY: clean
-clean:
-	rm -f $(TARGET) *.a *.o *~
diff --git a/SW/MK/mksocmemio/mksocmemio b/SW/MK/mksocmemio/mksocmemio
deleted file mode 100755
index 97fb39d1..00000000
Binary files a/SW/MK/mksocmemio/mksocmemio and /dev/null differ
diff --git a/SW/MK/mksocmemio/mksocmemio.c b/SW/MK/mksocmemio/mksocmemio.c
deleted file mode 100644
index 3804885d..00000000
--- a/SW/MK/mksocmemio/mksocmemio.c
+++ /dev/null
@@ -1,90 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/mman.h>
-#include "hwlib.h"
-#include "socal/socal.h"
-#include "socal/hps.h"
-
-#define HW_REGS_BASE ( ALT_STM_OFST )
-#define HW_REGS_SPAN ( 65536 )
-#define HW_REGS_MASK ( HW_REGS_SPAN - 1 )
-
-//#define MAX_ADDR 65533 (higher creates no output error)
-#define MAX_ADDR 1020
-void usage(void);
-
-void usage(void)
-{
-	printf("Usage:\n");
-	printf(" -r address \n");
-	printf(" -w address \n");
-	exit (8);
-}
-
-
-int main ( int argc, char *argv[] )
-{
-    void *virtual_base;
-    void *h2p_lw_axi_mem_addr=NULL;
-    int fd;
-
-    printf("    mksocfpgamemio: read write hm2 memory locatons by cmmandline arguments  \n");
-
-    // Open /dev/uio0
-    if ( ( fd = open ( "/dev/uio0", ( O_RDWR | O_SYNC ) ) ) == -1 ) {
-        printf ( "    ERROR: could not open \"/dev/uio0\"...\n" );
-        return ( 1 );
-    }
-    printf("    /dev/uio0 opened fine OK \n");
-
-    // get virtual addr that maps to physical
-    virtual_base = mmap( NULL, HW_REGS_SPAN, ( PROT_READ | PROT_WRITE ), MAP_SHARED, fd, 0);
-
-    if ( virtual_base == MAP_FAILED ) {
-        printf ( "    ERROR: mmap() failed...\n" );
-
-        close ( fd );
-        return ( 1 );
-    }
-    printf("    region mmap'ed  OK \n");
-
-    // Get the base address that maps to the device
-    //    assign pointer
-    h2p_lw_axi_mem_addr=virtual_base;// + ( ( unsigned long  )( ALT_LWFPGASLVS_OFST + HM2REG_IO_0_BASE ) & ( unsigned long)( HW_REGS_MASK ) );
-
-    printf("    mem pointer created OK\n");
-
-    uint32_t index = (uint32_t) strtol(argv[2], NULL, 16);
-
-    uint32_t value = *((uint32_t *)(h2p_lw_axi_mem_addr + index));
-
-
-    printf("Program name: %s    input option = %c \n", argv[0], argv[1][1]);
-
-	switch (argv[1][1])
-	{
-		case 'r':
-			printf("Read only \n");
-			printf("Address %u \tvalue = 0x%08X \tdecimal = %u \n", index, value, value);
-			break;
-
-		case 'w':
-			printf("read Write read  \n");
-			printf("Address %u will be set to \tvalue = 0x%08X \tdecimal = %u \n", index, value, value);
-			uint32_t inval = (uint32_t) atoi(argv[3]);
-			uint32_t oldval = *((uint32_t *)(h2p_lw_axi_mem_addr + index));
-			*((uint32_t *)(h2p_lw_axi_mem_addr + index)) = inval;
-			value = *((uint32_t *)(h2p_lw_axi_mem_addr + index));
-			printf("Address %u \tformer val = 0x%08X \t wrote: --> 0x%08X \tdecimal = %u \t read: = 0x%08X \tdecimal = %u \n", index, oldval, inval, inval, value, value);
-			break;
-
-		default:
-			printf("Wrong Argument: %s\n", argv[1]);
-			usage();
-	}
-    return (0);
-}
\ No newline at end of file
diff --git a/SW/MK/mksocmemio/mksocmemio.o b/SW/MK/mksocmemio/mksocmemio.o
deleted file mode 100644
index c1c45687..00000000
Binary files a/SW/MK/mksocmemio/mksocmemio.o and /dev/null differ