From 34520908388c03f04c6abd920ed357721720e30a Mon Sep 17 00:00:00 2001 From: Michael Brown Date: Thu, 23 May 2019 14:57:16 +0200 Subject: [PATCH 1/9] DExx..Cramps: Change spi type to bspi --- ...3x24_cap_spi.vhd => PIN_3x24_cap_bspi.vhd} | 30 +++++++++---------- ...3x24_cap_spi.sv => atlas_3x24_cap_bspi.sv} | 0 2 files changed, 15 insertions(+), 15 deletions(-) rename HW/hm2/config/DExx_Nano_xxx_Cramps/{PIN_3x24_cap_spi.vhd => PIN_3x24_cap_bspi.vhd} (92%) rename HW/hm2/config/DExx_Nano_xxx_Cramps/{atlas_3x24_cap_spi.sv => atlas_3x24_cap_bspi.sv} (100%) diff --git a/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_spi.vhd b/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_bspi.vhd similarity index 92% rename from HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_spi.vhd rename to HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_bspi.vhd index 2ee9230a..2d04bc3f 100644 --- a/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_spi.vhd +++ b/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_bspi.vhd @@ -81,7 +81,7 @@ package Pintypes is (LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask), (NANOADCTag, x"00", ClockLowTag, x"08", NANOADCAddr&PadT, NANOADCNumRegs, x"00", NANOADCBitMask), (CAPSENSETag, x"00", ClockLowTag, x"04", CAPSENSEAddr&PadT, CAPSENSENumRegs, x"00", CAPSENSEBitMask), - (SPITag, x"00", ClockLowTag, x"01", SPIDataAddr&PadT, SPINumRegs, x"00", SPIMPBitMask), + (BSPITag, x"00", ClockLowTag, x"01", BSPIDataAddr&PadT, BSPINumRegs, x"11", BSPIMPBitMask), (FWIDTag, x"00", ClockLowTag, x"01", FWIDAddr&PadT, FWIDNumRegs, x"00", FWIDMPBitMask), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), @@ -154,21 +154,21 @@ package Pintypes is IOPortTag & x"00" & CAPSENSETag & CapSensePin1, -- I/O 38 GPIO_1 03 03 CapSense sense 1 IOPortTag & x"00" & CAPSENSETag & CapSensePin2, -- I/O 39 GPIO_1 04 04 CapSense sense 2 IOPortTag & x"00" & CAPSENSETag & CapSensePin3, -- I/O 40 GPIO_1 05 05 CapSense sense 3 - IOPortTag & x"00" & NullTag & NullPin, -- I/O 41 GPIO_1 06 06 just GPIO - IOPortTag & x"00" & SPITag & SPIFramePin, -- I/O 42 GPIO_1 07 07 SPI Frame - IOPortTag & x"00" & SPITag & SPIOutPin, -- I/O 43 GPIO_1 08 08 SPI Out - IOPortTag & x"00" & SPITag & SPIClkPin, -- I/O 44 GPIO_1 09 09 SPI Clk - IOPortTag & x"00" & SPITag & SPIInPin, -- I/O 45 GPIO_1 10 10 SPI In - IOPortTag & x"00" & NullTag & NullPin, -- I/O 46 GPIO_1 11 13 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 41 GPIO_1 06 06 Encoder 1 Z + IOPortTag & x"00" & NullTag & NullPin, -- I/O 42 GPIO_1 07 07 Encoder 1 B + IOPortTag & x"00" & NullTag & NullPin, -- I/O 43 GPIO_1 08 08 Encoder 1 A + IOPortTag & x"00" & NullTag & NullPin, -- I/O 44 GPIO_1 09 09 Encoder 2 Z + IOPortTag & x"00" & NullTag & NullPin, -- I/O 45 GPIO_1 10 10 Encoder 2 B + IOPortTag & x"00" & NullTag & NullPin, -- I/O 46 GPIO_1 11 13 Encoder 2 A IOPortTag & x"00" & NullTag & NullPin, -- I/O 47 GPIO_1 12 14 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 48 GPIO_1 13 15 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 49 GPIO_1 14 16 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 50 GPIO_1 15 17 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 51 GPIO_1 16 18 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 52 GPIO_1 17 19 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 53 GPIO_1 18 20 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 54 GPIO_1 19 21 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 55 GPIO_1 20 22 just GPIO + IOPortTag & x"00" & BSPITag & BSPIFramePin, -- I/O 48 GPIO_1 13 15 SPI Frame + IOPortTag & x"00" & BSPITag & BSPIOutPin, -- I/O 49 GPIO_1 14 16 SPI Out + IOPortTag & x"00" & BSPITag & BSPIClkPin, -- I/O 50 GPIO_1 15 17 SPI Clk + IOPortTag & x"00" & BSPITag & BSPIInPin, -- I/O 51 GPIO_1 16 18 SPI In + IOPortTag & x"00" & BSPITag & BSPICS3Pin, -- I/O 52 GPIO_1 17 19 SPI Cs + IOPortTag & x"00" & BSPITag & BSPICS2Pin, -- I/O 53 GPIO_1 18 20 SPI Cs + IOPortTag & x"00" & BSPITag & BSPICS1Pin, -- I/O 54 GPIO_1 19 21 SPI Cs + IOPortTag & x"00" & BSPITag & BSPICS0Pin, -- I/O 55 GPIO_1 20 22 SPI Cs IOPortTag & x"00" & NullTag & NullPin, -- I/O 56 GPIO_1 21 23 just GPIO IOPortTag & x"00" & NullTag & NullPin, -- I/O 57 GPIO_1 22 24 just GPIO IOPortTag & x"00" & NullTag & NullPin, -- I/O 58 GPIO_1 23 25 just GPIO diff --git a/HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_spi.sv b/HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_bspi.sv similarity index 100% rename from HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_spi.sv rename to HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_bspi.sv From 0292077862bae3482faac09e0f52483a39c704c5 Mon Sep 17 00:00:00 2001 From: Michael Brown Date: Mon, 27 May 2019 17:12:07 +0200 Subject: [PATCH 2/9] DExx_Cramps: Add bspi cores --- HW/hm2/hm3_socfpga.qip | 1 + HW/hm2/hostmot3.vhd | 977 ++++++++++++++++++---------------- HW/hm2/wrappers/MakeBSPIs.vhd | 159 ++++++ 3 files changed, 673 insertions(+), 464 deletions(-) create mode 100644 HW/hm2/wrappers/MakeBSPIs.vhd diff --git a/HW/hm2/hm3_socfpga.qip b/HW/hm2/hm3_socfpga.qip index 031b05fc..1015f192 100644 --- a/HW/hm2/hm3_socfpga.qip +++ b/HW/hm2/hm3_socfpga.qip @@ -30,6 +30,7 @@ set_global_assignment -name VHDL_FILE ../../hm2/wrappers/MakeMuxedQCounters.vhd set_global_assignment -name VHDL_FILE ../../hm2/wrappers/MakePwmgens.vhd set_global_assignment -name VHDL_FILE ../../hm2/wrappers/MakeTPPWMGens.vhd set_global_assignment -name VHDL_FILE ../../hm2/wrappers/MakeSPIs.vhd +set_global_assignment -name VHDL_FILE ../../hm2/wrappers/MakeBSPIs.vhd # HM2 cores: set_global_assignment -name VHDL_FILE ../../hm2/kubstepgenzi.vhd diff --git a/HW/hm2/hostmot3.vhd b/HW/hm2/hostmot3.vhd index f05d266e..648ddaef 100644 --- a/HW/hm2/hostmot3.vhd +++ b/HW/hm2/hostmot3.vhd @@ -82,59 +82,59 @@ use work.PinExists.all; use work.ModuleExists.all; entity HostMot3 is - generic - ( - ThePinDesc: PinDescType; - TheModuleID: ModuleIDType; - IDROMType: integer; - SepClocks: boolean; - OneWS: boolean; - UseStepGenPrescaler: boolean; - UseIRQLogic: boolean; - PWMRefWidth: integer; - UseWatchDog: boolean; - OffsetToModules: integer; - OffsetToPinDesc: integer; - ClockHigh: integer; - ClockMed: integer; - ClockLow: integer; - BoardNameLow : std_Logic_Vector(31 downto 0); - BoardNameHigh : std_Logic_Vector(31 downto 0); - FPGASize: integer; - FPGAPins: integer; - IOPorts: integer; - IOWidth: integer; - LIOWidth: integer; - PortWidth: integer; - BusWidth: integer; - AddrWidth: integer; - InstStride0: integer; - InstStride1: integer; - RegStride0: integer; - RegStride1: integer; - LEDCount: integer - ); - port - ( - -- Generic 32 bit bus interface signals -- + generic + ( + ThePinDesc: PinDescType; + TheModuleID: ModuleIDType; + IDROMType: integer; + SepClocks: boolean; + OneWS: boolean; + UseStepGenPrescaler: boolean; + UseIRQLogic: boolean; + PWMRefWidth: integer; + UseWatchDog: boolean; + OffsetToModules: integer; + OffsetToPinDesc: integer; + ClockHigh: integer; + ClockMed: integer; + ClockLow: integer; + BoardNameLow : std_Logic_Vector(31 downto 0); + BoardNameHigh : std_Logic_Vector(31 downto 0); + FPGASize: integer; + FPGAPins: integer; + IOPorts: integer; + IOWidth: integer; + LIOWidth: integer; + PortWidth: integer; + BusWidth: integer; + AddrWidth: integer; + InstStride0: integer; + InstStride1: integer; + RegStride0: integer; + RegStride1: integer; + LEDCount: integer + ); + port +( + -- Generic 32 bit bus interface signals -- - ibustop: in std_logic_vector(BusWidth -1 downto 0); - obustop: out std_logic_vector(BusWidth -1 downto 0); - addr: in std_logic_vector(AddrWidth -1 downto 2); - readstb: in std_logic; - writestb: in std_logic; - clklow: in std_logic; - clkmed: in std_logic; - clkhigh: in std_logic; - intirq: out std_logic; - dreq: out std_logic; - demandmode: out std_logic; - iobitsouttop: out std_logic_vector (IOWidth -1 downto 0) := (others => 'Z'); - iobitsintop: in std_logic_vector (IOWidth -1 downto 0) := (others => 'Z'); - liobits: inout std_logic_vector (lIOWidth -1 downto 0); - rates: out std_logic_vector (4 downto 0); - leds: out std_logic_vector(ledcount-1 downto 0) - ); + ibustop: in std_logic_vector(BusWidth -1 downto 0); + obustop: out std_logic_vector(BusWidth -1 downto 0); + addr: in std_logic_vector(AddrWidth -1 downto 2); + readstb: in std_logic; + writestb: in std_logic; + clklow: in std_logic; + clkmed: in std_logic; + clkhigh: in std_logic; + intirq: out std_logic; + dreq: out std_logic; + demandmode: out std_logic; + iobitsouttop: out std_logic_vector (IOWidth -1 downto 0) := (others => 'Z'); + iobitsintop: in std_logic_vector (IOWidth -1 downto 0) := (others => 'Z'); + liobits: inout std_logic_vector (lIOWidth -1 downto 0); + rates: out std_logic_vector (4 downto 0); + leds: out std_logic_vector(ledcount-1 downto 0) + ); end HostMot3; @@ -151,7 +151,7 @@ signal obusint: std_logic_vector(BusWidth -1 downto 0); signal IOBitsin: std_logic_vector(IOWidth-1 downto 0); signal CoreDataOut: std_logic_vector(IOWidth-1 downto 0); - -- Extract the number of modules of each type from the ModuleID + -- Extract the number of modules of each type from the ModuleID constant StepGens: integer := NumberOfModules(TheModuleID,StepGenTag); constant QCounters: integer := NumberOfModules(TheModuleID,QCountTag); constant MuxedQCounters: integer := NumberOfModules(TheModuleID,MuxedQCountTag); -- non-muxed index mask @@ -160,8 +160,8 @@ constant PWMGens : integer := NumberOfModules(TheModuleID,PWMTag); constant UsePWMEnas: boolean := PinExists(ThePinDesc,PWMTag,PWMCEnaPin); constant TPPWMGens : integer := NumberOfModules(TheModuleID,TPPWMTag); constant SPIs: integer := NumberOfModules(TheModuleID,SPITag); ---constant BSPIs: integer := NumberOfModules(TheModuleID,BSPITag); ---constant DBSPIs: integer := NumberOfModules(TheModuleID,DBSPITag); +constant BSPIs: integer := NumberOfModules(TheModuleID,BSPITag); +-- constant DBSPIs: integer := NumberOfModules(TheModuleID,DBSPITag); --constant SSSIs: integer := NumberOfModules(TheModuleID,SSSITag); --constant FAbss: integer := NumberOfModules(TheModuleID,FAbsTag); --constant BISSs: integer := NumberOfModules(TheModuleID,BISSTag); @@ -193,9 +193,9 @@ constant HM2DPLLs: integer := NumberOfModules(TheModuleID,HM2DPLLTag); -- extract the needed Stepgen table width from the max pin# used with a stepgen tag constant StepGenTableWidth: integer := MaxPinsPerModule(ThePinDesc,StepGenTag); - -- extract how many BSPI CS pins are needed ---constant BSPICSWidth: integer := CountPinsInRange(ThePinDesc,BSPITag,BSPICS0Pin,BSPICS7Pin); - -- extract how many DBSPI CS pins are needed + -- extract how many BSPI CS pins are needed +constant BSPICSWidth: integer := CountPinsInRange(ThePinDesc,BSPITag,BSPICS0Pin,BSPICS7Pin); + -- extract how many DBSPI CS pins are needed --constant DBSPICSWidth: integer := CountPinsInRange(ThePinDesc,DBSPITag,DBSPICS0Pin,DBSPICS7Pin); constant UseProbe: boolean := PinExists(ThePinDesc,QCountTag,QCountProbePin); @@ -208,422 +208,471 @@ constant UseStepgenProbe: boolean := PinExists(ThePinDesc,StepGenTag,StepGenProb -- I/O port related signals - signal IOBitsCorein : std_logic_vector(IOWidth-1 downto 0) := (others => '0'); + signal IOBitsCorein : std_logic_vector(IOWidth-1 downto 0) := (others => '0'); -- qcounter related signals - signal Probe : std_logic; -- hs probe input for counters,stepgens etc + signal Probe : std_logic; -- hs probe input for counters,stepgens etc -- PWM related signals (this is global because its shared by two modules) - signal RefCountBus : std_logic_vector(PWMRefWidth-1 downto 0); + signal RefCountBus : std_logic_vector(PWMRefWidth-1 downto 0); -- Timer related signals -- signal DPLLTimers: std_logic_vector(3 downto 0); -- signal DPLLRefOut: std_logic; - signal RateSources: std_logic_vector(4 downto 0); + signal RateSources: std_logic_vector(4 downto 0); - function bitreverse(v: in std_logic_vector) -- Thanks: J. Bromley - return std_logic_vector is - variable result: std_logic_vector(v'RANGE); - alias tv: std_logic_vector(v'REVERSE_RANGE) is v; - begin - for i in tv'RANGE loop - result(i) := tv(i); - end loop; - return result; - end; + function bitreverse(v: in std_logic_vector) -- Thanks: J. Bromley + return std_logic_vector is + variable result: std_logic_vector(v'RANGE); + alias tv: std_logic_vector(v'REVERSE_RANGE) is v; + begin + for i in tv'RANGE loop + result(i) := tv(i); + end loop; + return result; + end; - begin + begin - MakeIOPorts : entity work.MakeIOPorts - generic map ( - ThePinDesc => ThePinDesc, - TheModuleID => TheModuleID, - IDROMType => IDROMType, - OffsetToModules => OffsetToModules, - OffsetToPinDesc => OffsetToPinDesc, - ClockHigh => ClockHigh, - ClockLow => ClockLow, - BoardNameLow => BoardNameLow, - BoardNameHigh => BoardNameHigh, - FPGASize => FPGASize, - FPGAPins => FPGAPins, - IOPorts => IOPorts, - IOWidth => IOWidth, - PortWidth => PortWidth, - InstStride0 => InstStride0, - InstStride1 => InstStride1, - RegStride0 => RegStride0, - RegStride1 => RegStride1, --- - ClockMed => ClockMed, - BusWidth => BusWidth, - AddrWidth => AddrWidth, - STEPGENs => STEPGENs, - StepGenTableWidth => StepGenTableWidth, - UseStepGenPreScaler => UseStepGenPreScaler, - UseStepgenIndex => UseStepgenIndex, - UseStepgenProbe => UseStepgenProbe, - timersize => 14, - asize => 48, - rsize => 32, - PWMGens => PWMGens, - PWMRefWidth => PWMRefWidth, - UsePWMEnas => UsePWMEnas, - QCounters => QCounters, - UseMuxedProbe => UseMuxedProbe, - UseProbe => UseProbe, - UseWatchDog => UseWatchDog, - UseDemandModeDMA => UseDemandModeDMA, - UseIRQlogic => UseIRQlogic, - LEDCount => LEDCount - ) - port map ( - ibustop => ibustop, - ibusint => ibusint, - obustop => obustop, - obusint => obusint, - addr => addr, - Aint => Aint, - readstb => readstb, - writestb => writestb, - iobitsouttop => iobitsouttop, - iobitsintop => iobitsintop, - IOBitsCorein => IOBitsCorein, - CoreDataOut => CoreDataOut, --- portdata => portdata, - clklow => clklow, - clkmed => clkmed, - clkhigh => clkhigh, - PRobe => PRobe, - demandmode => demandmode, -- passed directly to top - intirq => intirq, - dreq => dreq, - RateSources => RateSources, - LEDS => leds - ); + MakeIOPorts : entity work.MakeIOPorts + generic map ( + ThePinDesc => ThePinDesc, + TheModuleID => TheModuleID, + IDROMType => IDROMType, + OffsetToModules => OffsetToModules, + OffsetToPinDesc => OffsetToPinDesc, + ClockHigh => ClockHigh, + ClockLow => ClockLow, + BoardNameLow => BoardNameLow, + BoardNameHigh => BoardNameHigh, + FPGASize => FPGASize, + FPGAPins => FPGAPins, + IOPorts => IOPorts, + IOWidth => IOWidth, + PortWidth => PortWidth, + InstStride0 => InstStride0, + InstStride1 => InstStride1, + RegStride0 => RegStride0, + RegStride1 => RegStride1, +-- +-- ClockMed => ClockMed, + BusWidth => BusWidth, + AddrWidth => AddrWidth, +-- STEPGENs => STEPGENs, +-- StepGenTableWidth => StepGenTableWidth, +-- UseStepGenPreScaler => UseStepGenPreScaler, +-- UseStepgenIndex => UseStepgenIndex, +-- UseStepgenProbe => UseStepgenProbe, +-- timersize => 14, +-- asize => 48, +-- rsize => 32, +-- PWMGens => PWMGens, +-- PWMRefWidth => PWMRefWidth, +-- UsePWMEnas => UsePWMEnas, +-- QCounters => QCounters, +-- UseMuxedProbe => UseMuxedProbe, +-- UseProbe => UseProbe, + UseWatchDog => UseWatchDog, + UseDemandModeDMA => UseDemandModeDMA, + UseIRQlogic => UseIRQlogic, + LEDCount => LEDCount + ) + port map ( + ibustop => ibustop, + ibusint => ibusint, + obustop => obustop, + obusint => obusint, + addr => addr, + Aint => Aint, + readstb => readstb, + writestb => writestb, + iobitsouttop => iobitsouttop, + iobitsintop => iobitsintop, + IOBitsCorein => IOBitsCorein, + CoreDataOut => CoreDataOut, +-- portdata => portdata, + clklow => clklow, + clkmed => clkmed, + clkhigh => clkhigh, + PRobe => PRobe, + demandmode => demandmode, -- passed directly to top + intirq => intirq, + dreq => dreq, + RateSources => RateSources, + LEDS => leds + ); GenMakeHm2Dpllmods: if HM2DPLLs >0 generate - MakeHm2Dpllmods : entity work.MakeHm2Dpllmods - generic map ( - ThePinDesc => ThePinDesc, - ClockHigh => ClockHigh, - ClockMed => ClockMed, - ClockLow => ClockLow, - BusWidth => BusWidth, - AddrWidth => AddrWidth, - IOWidth => IOWidth, - STEPGENs => STEPGENs, - StepGenTableWidth => StepGenTableWidth, - UseStepGenPreScaler => UseStepGenPreScaler, - UseStepgenIndex => UseStepgenIndex, - UseStepgenProbe => UseStepgenProbe, - timersize => 14, - asize => 48, - rsize => 32, - HM2DPLLs => HM2DPLLs, - MuxedQCounters => MuxedQCounters, - MuxedQCountersMIM => MuxedQCountersMIM, - PWMGens => PWMGens, - PWMRefWidth => PWMRefWidth, - UsePWMEnas => UsePWMEnas, - TPPWMGens => TPPWMGens, - QCounters => QCounters, - UseMuxedProbe => UseMuxedProbe, - UseProbe => UseProbe - ) - port map ( - ibus => ibusint, - obusint => obusint, - Aint => Aint, - readstb => readstb, - writestb => writestb, - CoreDataOut => CoreDataOut, - IOBitsCorein => IOBitsCorein, - clklow => clklow, - clkmed => clkmed, - clkhigh => clkhigh, - PRobe => PRobe, - RateSources => RateSources, - rates => rates - ); + MakeHm2Dpllmods : entity work.MakeHm2Dpllmods + generic map ( + ThePinDesc => ThePinDesc, + ClockHigh => ClockHigh, + ClockMed => ClockMed, + ClockLow => ClockLow, + BusWidth => BusWidth, + AddrWidth => AddrWidth, + IOWidth => IOWidth, + STEPGENs => STEPGENs, + StepGenTableWidth => StepGenTableWidth, + UseStepGenPreScaler => UseStepGenPreScaler, + UseStepgenIndex => UseStepgenIndex, + UseStepgenProbe => UseStepgenProbe, + timersize => 14, + asize => 48, + rsize => 32, + HM2DPLLs => HM2DPLLs, + MuxedQCounters => MuxedQCounters, + MuxedQCountersMIM => MuxedQCountersMIM, + PWMGens => PWMGens, + PWMRefWidth => PWMRefWidth, + UsePWMEnas => UsePWMEnas, + TPPWMGens => TPPWMGens, + QCounters => QCounters, + UseMuxedProbe => UseMuxedProbe, + UseProbe => UseProbe + ) + port map ( + ibus => ibusint, + obusint => obusint, + Aint => Aint, + readstb => readstb, + writestb => writestb, + CoreDataOut => CoreDataOut, + IOBitsCorein => IOBitsCorein, + clklow => clklow, + clkmed => clkmed, + clkhigh => clkhigh, + PRobe => PRobe, + RateSources => RateSources, + rates => rates + ); end generate; GenMakeStepgens: if STEPGENs >0 generate - MakeStepgens : entity work.MakeStepgens - generic map ( - ThePinDesc => ThePinDesc, - ClockHigh => ClockHigh, - ClockMed => ClockMed, - ClockLow => ClockLow, - BusWidth => BusWidth, - AddrWidth => AddrWidth, - IOWidth => IOWidth, - STEPGENs => STEPGENs, - StepGenTableWidth => StepGenTableWidth, - UseStepGenPreScaler => UseStepGenPreScaler, - UseStepgenIndex => UseStepgenIndex, - UseStepgenProbe => UseStepgenProbe, - timersize => 14, - asize => 48, - rsize => 32, - HM2DPLLs => HM2DPLLs, - MuxedQCounters => MuxedQCounters, - MuxedQCountersMIM => MuxedQCountersMIM, - PWMGens => PWMGens, - PWMRefWidth => PWMRefWidth, - UsePWMEnas => UsePWMEnas, - TPPWMGens => TPPWMGens, - QCounters => QCounters, - UseMuxedProbe => UseMuxedProbe, - UseProbe => UseProbe - ) - port map ( - ibus => ibusint, - obusint => obusint, - Aint => Aint, - readstb => readstb, - writestb => writestb, - CoreDataOut => CoreDataOut, - IOBitsCorein => IOBitsCorein, - clklow => clklow, - clkmed => clkmed, - clkhigh => clkhigh, - PRobe => PRobe, - RateSources => RateSources, - rates => rates - ); + MakeStepgens : entity work.MakeStepgens + generic map ( + ThePinDesc => ThePinDesc, + ClockHigh => ClockHigh, + ClockMed => ClockMed, + ClockLow => ClockLow, + BusWidth => BusWidth, + AddrWidth => AddrWidth, + IOWidth => IOWidth, + STEPGENs => STEPGENs, + StepGenTableWidth => StepGenTableWidth, + UseStepGenPreScaler => UseStepGenPreScaler, + UseStepgenIndex => UseStepgenIndex, + UseStepgenProbe => UseStepgenProbe, + timersize => 14, + asize => 48, + rsize => 32, + HM2DPLLs => HM2DPLLs, + MuxedQCounters => MuxedQCounters, + MuxedQCountersMIM => MuxedQCountersMIM, + PWMGens => PWMGens, + PWMRefWidth => PWMRefWidth, + UsePWMEnas => UsePWMEnas, + TPPWMGens => TPPWMGens, + QCounters => QCounters, + UseMuxedProbe => UseMuxedProbe, + UseProbe => UseProbe + ) + port map ( + ibus => ibusint, + obusint => obusint, + Aint => Aint, + readstb => readstb, + writestb => writestb, + CoreDataOut => CoreDataOut, + IOBitsCorein => IOBitsCorein, + clklow => clklow, + clkmed => clkmed, + clkhigh => clkhigh, + PRobe => PRobe, + RateSources => RateSources, + rates => rates + ); end generate; GenMakeQCounters: if QCounters >0 generate - MakeQCounters : entity work.MakeQCounters - generic map ( - ThePinDesc => ThePinDesc, - ClockHigh => ClockHigh, - ClockMed => ClockMed, - ClockLow => ClockLow, - BusWidth => BusWidth, - AddrWidth => AddrWidth, - IOWidth => IOWidth, - STEPGENs => STEPGENs, - StepGenTableWidth => StepGenTableWidth, - UseStepGenPreScaler => UseStepGenPreScaler, - UseStepgenIndex => UseStepgenIndex, - UseStepgenProbe => UseStepgenProbe, - timersize => 14, - asize => 48, - rsize => 32, - HM2DPLLs => HM2DPLLs, - MuxedQCounters => MuxedQCounters, - MuxedQCountersMIM => MuxedQCountersMIM, - PWMGens => PWMGens, - PWMRefWidth => PWMRefWidth, - UsePWMEnas => UsePWMEnas, - TPPWMGens => TPPWMGens, - QCounters => QCounters, - UseMuxedProbe => UseMuxedProbe, - UseProbe => UseProbe - ) - port map ( - ibus => ibusint, - obusint => obusint, - Aint => Aint, - readstb => readstb, - writestb => writestb, - CoreDataOut => CoreDataOut, - IOBitsCorein => IOBitsCorein, - clklow => clklow, - clkmed => clkmed, - clkhigh => clkhigh, - PRobe => PRobe, - RateSources => RateSources, - rates => rates - ); + MakeQCounters : entity work.MakeQCounters + generic map ( + ThePinDesc => ThePinDesc, + ClockHigh => ClockHigh, + ClockMed => ClockMed, + ClockLow => ClockLow, + BusWidth => BusWidth, + AddrWidth => AddrWidth, + IOWidth => IOWidth, + STEPGENs => STEPGENs, + StepGenTableWidth => StepGenTableWidth, + UseStepGenPreScaler => UseStepGenPreScaler, + UseStepgenIndex => UseStepgenIndex, + UseStepgenProbe => UseStepgenProbe, + timersize => 14, + asize => 48, + rsize => 32, + HM2DPLLs => HM2DPLLs, + MuxedQCounters => MuxedQCounters, + MuxedQCountersMIM => MuxedQCountersMIM, + PWMGens => PWMGens, + PWMRefWidth => PWMRefWidth, + UsePWMEnas => UsePWMEnas, + TPPWMGens => TPPWMGens, + QCounters => QCounters, + UseMuxedProbe => UseMuxedProbe, + UseProbe => UseProbe + ) + port map ( + ibus => ibusint, + obusint => obusint, + Aint => Aint, + readstb => readstb, + writestb => writestb, + CoreDataOut => CoreDataOut, + IOBitsCorein => IOBitsCorein, + clklow => clklow, + clkmed => clkmed, + clkhigh => clkhigh, + PRobe => PRobe, + RateSources => RateSources, + rates => rates + ); end generate; GenMakeMuxedQCounters: if MuxedQCounters >0 generate - MakeMuxedQCounters : entity work.MakeMuxedQCounters - generic map ( - ThePinDesc => ThePinDesc, - ClockHigh => ClockHigh, - ClockMed => ClockMed, - ClockLow => ClockLow, - BusWidth => BusWidth, - AddrWidth => AddrWidth, - IOWidth => IOWidth, - STEPGENs => STEPGENs, - StepGenTableWidth => StepGenTableWidth, - UseStepGenPreScaler => UseStepGenPreScaler, - UseStepgenIndex => UseStepgenIndex, - UseStepgenProbe => UseStepgenProbe, - timersize => 14, - asize => 48, - rsize => 32, - HM2DPLLs => HM2DPLLs, - MuxedQCounters => MuxedQCounters, - MuxedQCountersMIM => MuxedQCountersMIM, - PWMGens => PWMGens, - PWMRefWidth => PWMRefWidth, - UsePWMEnas => UsePWMEnas, - TPPWMGens => TPPWMGens, - QCounters => QCounters, - UseMuxedProbe => UseMuxedProbe, - UseProbe => UseProbe - ) - port map ( - ibus => ibusint, - obusint => obusint, - Aint => Aint, - readstb => readstb, - writestb => writestb, - CoreDataOut => CoreDataOut, - IOBitsCorein => IOBitsCorein, - clklow => clklow, - clkmed => clkmed, - clkhigh => clkhigh, - PRobe => PRobe, - RateSources => RateSources, - rates => rates - ); + MakeMuxedQCounters : entity work.MakeMuxedQCounters + generic map ( + ThePinDesc => ThePinDesc, + ClockHigh => ClockHigh, + ClockMed => ClockMed, + ClockLow => ClockLow, + BusWidth => BusWidth, + AddrWidth => AddrWidth, + IOWidth => IOWidth, + STEPGENs => STEPGENs, + StepGenTableWidth => StepGenTableWidth, + UseStepGenPreScaler => UseStepGenPreScaler, + UseStepgenIndex => UseStepgenIndex, + UseStepgenProbe => UseStepgenProbe, + timersize => 14, + asize => 48, + rsize => 32, + HM2DPLLs => HM2DPLLs, + MuxedQCounters => MuxedQCounters, + MuxedQCountersMIM => MuxedQCountersMIM, + PWMGens => PWMGens, + PWMRefWidth => PWMRefWidth, + UsePWMEnas => UsePWMEnas, + TPPWMGens => TPPWMGens, + QCounters => QCounters, + UseMuxedProbe => UseMuxedProbe, + UseProbe => UseProbe + ) + port map ( + ibus => ibusint, + obusint => obusint, + Aint => Aint, + readstb => readstb, + writestb => writestb, + CoreDataOut => CoreDataOut, + IOBitsCorein => IOBitsCorein, + clklow => clklow, + clkmed => clkmed, + clkhigh => clkhigh, + PRobe => PRobe, + RateSources => RateSources, + rates => rates + ); end generate; GenMakePWMgens: if PWMGens >0 generate - MakePWMgens : entity work.MakePWMgens - generic map ( - ThePinDesc => ThePinDesc, - ClockHigh => ClockHigh, - ClockMed => ClockMed, - ClockLow => ClockLow, - BusWidth => BusWidth, - AddrWidth => AddrWidth, - IOWidth => IOWidth, - STEPGENs => STEPGENs, - StepGenTableWidth => StepGenTableWidth, - UseStepGenPreScaler => UseStepGenPreScaler, - UseStepgenIndex => UseStepgenIndex, - UseStepgenProbe => UseStepgenProbe, - timersize => 14, - asize => 48, - rsize => 32, - HM2DPLLs => HM2DPLLs, - MuxedQCounters => MuxedQCounters, - MuxedQCountersMIM => MuxedQCountersMIM, - PWMGens => PWMGens, - PWMRefWidth => PWMRefWidth, - UsePWMEnas => UsePWMEnas, - TPPWMGens => TPPWMGens, - QCounters => QCounters, - UseMuxedProbe => UseMuxedProbe, - UseProbe => UseProbe - ) - port map ( - ibus => ibusint, - obusint => obusint, - Aint => Aint, - readstb => readstb, - writestb => writestb, - CoreDataOut => CoreDataOut, - IOBitsCorein => IOBitsCorein, - clklow => clklow, - clkmed => clkmed, - clkhigh => clkhigh, - PRobe => PRobe, - RateSources => RateSources, - rates => rates - ); + MakePWMgens : entity work.MakePWMgens + generic map ( + ThePinDesc => ThePinDesc, + ClockHigh => ClockHigh, + ClockMed => ClockMed, + ClockLow => ClockLow, + BusWidth => BusWidth, + AddrWidth => AddrWidth, + IOWidth => IOWidth, + STEPGENs => STEPGENs, + StepGenTableWidth => StepGenTableWidth, + UseStepGenPreScaler => UseStepGenPreScaler, + UseStepgenIndex => UseStepgenIndex, + UseStepgenProbe => UseStepgenProbe, + timersize => 14, + asize => 48, + rsize => 32, + HM2DPLLs => HM2DPLLs, + MuxedQCounters => MuxedQCounters, + MuxedQCountersMIM => MuxedQCountersMIM, + PWMGens => PWMGens, + PWMRefWidth => PWMRefWidth, + UsePWMEnas => UsePWMEnas, + TPPWMGens => TPPWMGens, + QCounters => QCounters, + UseMuxedProbe => UseMuxedProbe, + UseProbe => UseProbe + ) + port map ( + ibus => ibusint, + obusint => obusint, + Aint => Aint, + readstb => readstb, + writestb => writestb, + CoreDataOut => CoreDataOut, + IOBitsCorein => IOBitsCorein, + clklow => clklow, + clkmed => clkmed, + clkhigh => clkhigh, + PRobe => PRobe, + RateSources => RateSources, + rates => rates + ); end generate; GenMakeTPPWMGens: if TPPWMGens >0 generate - MakeTPPWMGens : entity work.MakeTPPWMGens - generic map ( - ThePinDesc => ThePinDesc, - ClockHigh => ClockHigh, - ClockMed => ClockMed, - ClockLow => ClockLow, - BusWidth => BusWidth, - AddrWidth => AddrWidth, - IOWidth => IOWidth, - STEPGENs => STEPGENs, - StepGenTableWidth => StepGenTableWidth, - UseStepGenPreScaler => UseStepGenPreScaler, - UseStepgenIndex => UseStepgenIndex, - UseStepgenProbe => UseStepgenProbe, - timersize => 14, - asize => 48, - rsize => 32, - HM2DPLLs => HM2DPLLs, - MuxedQCounters => MuxedQCounters, - MuxedQCountersMIM => MuxedQCountersMIM, - PWMGens => PWMGens, - PWMRefWidth => PWMRefWidth, - UsePWMEnas => UsePWMEnas, - TPPWMGens => TPPWMGens, - QCounters => QCounters, - UseMuxedProbe => UseMuxedProbe, - UseProbe => UseProbe - ) - port map ( - ibus => ibusint, - obusint => obusint, - Aint => Aint, - readstb => readstb, - writestb => writestb, - CoreDataOut => CoreDataOut, - IOBitsCorein => IOBitsCorein, - clklow => clklow, - clkmed => clkmed, - clkhigh => clkhigh, - PRobe => PRobe, - RateSources => RateSources, - rates => rates - ); + MakeTPPWMGens : entity work.MakeTPPWMGens + generic map ( + ThePinDesc => ThePinDesc, + ClockHigh => ClockHigh, + ClockMed => ClockMed, + ClockLow => ClockLow, + BusWidth => BusWidth, + AddrWidth => AddrWidth, + IOWidth => IOWidth, + STEPGENs => STEPGENs, + StepGenTableWidth => StepGenTableWidth, + UseStepGenPreScaler => UseStepGenPreScaler, + UseStepgenIndex => UseStepgenIndex, + UseStepgenProbe => UseStepgenProbe, + timersize => 14, + asize => 48, + rsize => 32, + HM2DPLLs => HM2DPLLs, + MuxedQCounters => MuxedQCounters, + MuxedQCountersMIM => MuxedQCountersMIM, + PWMGens => PWMGens, + PWMRefWidth => PWMRefWidth, + UsePWMEnas => UsePWMEnas, + TPPWMGens => TPPWMGens, + QCounters => QCounters, + UseMuxedProbe => UseMuxedProbe, + UseProbe => UseProbe + ) + port map ( + ibus => ibusint, + obusint => obusint, + Aint => Aint, + readstb => readstb, + writestb => writestb, + CoreDataOut => CoreDataOut, + IOBitsCorein => IOBitsCorein, + clklow => clklow, + clkmed => clkmed, + clkhigh => clkhigh, + PRobe => PRobe, + RateSources => RateSources, + rates => rates + ); end generate; GenMakeSPIs: if SPIs >0 generate - MakeSPIs : entity work.MakeSPIs - generic map ( - ThePinDesc => ThePinDesc, - ClockHigh => ClockHigh, - ClockMed => ClockMed, - ClockLow => ClockLow, - BusWidth => BusWidth, - AddrWidth => AddrWidth, - IOWidth => IOWidth, - STEPGENs => STEPGENs, - StepGenTableWidth => StepGenTableWidth, - UseStepGenPreScaler => UseStepGenPreScaler, - UseStepgenIndex => UseStepgenIndex, - UseStepgenProbe => UseStepgenProbe, - timersize => 14, - asize => 48, - rsize => 32, - HM2DPLLs => HM2DPLLs, - MuxedQCounters => MuxedQCounters, - MuxedQCountersMIM => MuxedQCountersMIM, - PWMGens => PWMGens, - PWMRefWidth => PWMRefWidth, - UsePWMEnas => UsePWMEnas, - TPPWMGens => TPPWMGens, - QCounters => QCounters, - UseMuxedProbe => UseMuxedProbe, - UseProbe => UseProbe, - SPIs => SPIs - ) - port map ( - ibus => ibusint, - obusint => obusint, - Aint => Aint, - readstb => readstb, - writestb => writestb, - CoreDataOut => CoreDataOut, - IOBitsCorein => IOBitsCorein, - clklow => clklow, - clkmed => clkmed, - clkhigh => clkhigh, - PRobe => PRobe, - RateSources => RateSources, - rates => rates - ); + MakeSPIs : entity work.MakeSPIs + generic map ( + ThePinDesc => ThePinDesc, + ClockHigh => ClockHigh, + ClockMed => ClockMed, + ClockLow => ClockLow, + BusWidth => BusWidth, + AddrWidth => AddrWidth, + IOWidth => IOWidth, + STEPGENs => STEPGENs, + StepGenTableWidth => StepGenTableWidth, + UseStepGenPreScaler => UseStepGenPreScaler, + UseStepgenIndex => UseStepgenIndex, + UseStepgenProbe => UseStepgenProbe, + timersize => 14, + asize => 48, + rsize => 32, + HM2DPLLs => HM2DPLLs, + MuxedQCounters => MuxedQCounters, + MuxedQCountersMIM => MuxedQCountersMIM, + PWMGens => PWMGens, + PWMRefWidth => PWMRefWidth, + UsePWMEnas => UsePWMEnas, + TPPWMGens => TPPWMGens, + QCounters => QCounters, + UseMuxedProbe => UseMuxedProbe, + UseProbe => UseProbe, + SPIs => SPIs + ) + port map ( + ibus => ibusint, + obusint => obusint, + Aint => Aint, + readstb => readstb, + writestb => writestb, + CoreDataOut => CoreDataOut, + IOBitsCorein => IOBitsCorein, + clklow => clklow, + clkmed => clkmed, + clkhigh => clkhigh, + PRobe => PRobe, + RateSources => RateSources, + rates => rates + ); +end generate; + +GenMakeBSPIs: if BSPIs >0 generate + MakeBSPIs : entity work.MakeBSPIs + generic map ( + ThePinDesc => ThePinDesc, + ClockHigh => ClockHigh, + ClockMed => ClockMed, + ClockLow => ClockLow, + BusWidth => BusWidth, + AddrWidth => AddrWidth, + IOWidth => IOWidth, + STEPGENs => STEPGENs, + StepGenTableWidth => StepGenTableWidth, + UseStepGenPreScaler => UseStepGenPreScaler, + UseStepgenIndex => UseStepgenIndex, + UseStepgenProbe => UseStepgenProbe, + timersize => 14, + asize => 48, + rsize => 32, + HM2DPLLs => HM2DPLLs, + MuxedQCounters => MuxedQCounters, + MuxedQCountersMIM => MuxedQCountersMIM, + PWMGens => PWMGens, + PWMRefWidth => PWMRefWidth, + UsePWMEnas => UsePWMEnas, + TPPWMGens => TPPWMGens, + QCounters => QCounters, + UseMuxedProbe => UseMuxedProbe, + UseProbe => UseProbe, + SPIs => SPIs, + BSPIs => BSPIs, + BSPICSWidth => BSPICSWidth + ) + port map ( + ibus => ibusint, + obusint => obusint, + Aint => Aint, + readstb => readstb, + writestb => writestb, + CoreDataOut => CoreDataOut, + IOBitsCorein => IOBitsCorein, + clklow => clklow, + clkmed => clkmed, + clkhigh => clkhigh, + PRobe => PRobe, + RateSources => RateSources, + rates => rates + ); end generate; -- @@ -706,8 +755,8 @@ end generate; -- BSPIIn(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBitsCorein(i); -- when others => -- IOBitsCorein(i) <= BSPICS(conv_integer(ThePinDesc(i)(23 downto 16)))(conv_integer(ThePinDesc(i)(6 downto 0))-5); --- -- magic foo, magic foo, what on earth does it do? --- -- (this needs to written more clearly!) +-- magic foo, magic foo, what on earth does it do? +-- (this needs to written more clearly!) -- end case; -- end if; -- end loop; @@ -789,8 +838,8 @@ end generate; -- DBSPIIn(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBitsCorein(i); -- when others => -- IOBitsCorein(i) <= DBSPICS(conv_integer(ThePinDesc(i)(23 downto 16)))(conv_integer(ThePinDesc(i)(6 downto 0))-5); --- -- magic foo, magic foo, what on earth does it do? --- -- (this needs to written more clearly!) +-- magic foo, magic foo, what on earth does it do? +-- (this needs to written more clearly!) -- end case; -- end if; -- end loop; @@ -814,8 +863,8 @@ end generate; -- when others => -- LIOBits(i) <= DBSPICS(conv_integer(ThePinDesc(i+IOWidth)(23 downto 16)))(conv_integer(ThePinDesc(i+IOWidth)(6 downto 0))-5); -- report("Local DBSPICSPin found at LIOBit " & integer'image(i)); --- -- magic foo, magic foo, what on earth does it do? --- -- (this needs to written more clearly!) +-- magic foo, magic foo, what on earth does it do? +-- (this needs to written more clearly!) -- end case; -- end if; -- end loop; @@ -1880,7 +1929,7 @@ end generate; -- testbit => SSerialTestBits(i) -- ); -- end generate; --- +-- -- SSerialDecodeProcess : process (Aint,Readstb,writestb,SSerialCommandSel,SSerialDataSel, -- SSerialRAMSel0,SSerialRAMSel1,SSerialRAMSel2,SSerialRAMSel3) -- begin @@ -1931,10 +1980,10 @@ end generate; -- report "UARTS per sserial 1 " & integer 'image(UARTSPerSSerial(1)); -- report "UARTS per sserial 2 " & integer 'image(UARTSPerSSerial(2)); -- report "UARTS per sserial 3 " & integer 'image(UARTSPerSSerial(3)); --- --- +-- +-- -- end process SSerialDecodeProcess; --- +-- -- DoSSerialPins: process(SSerialTX, SSerialTXEn, SSerialTestBits, IOBitsCorein) -- begin -- for i in 0 to IOWidth -1 loop -- loop through all the external I/O pins @@ -1955,7 +2004,7 @@ end generate; -- end loop; -- end process; -- end generate; --- +-- -- maketwiddlermod: if Twiddlers >0 generate -- signal LoadTwiddlerCommand: std_logic_vector(Twiddlers -1 downto 0); -- signal ReadTwiddlerCommand: std_logic_vector(Twiddlers -1 downto 0); @@ -1996,7 +2045,7 @@ end generate; -- -- testbit => TwiddlerTestBits(i) -- ); -- end generate; --- +-- -- TwiddleDecodeProcess : process (Aint,Readstb,writestb,TwiddlerCommandSel,TwiddlerDataSel,TwiddlerRAMSel) -- begin -- if Aint(AddrWidth-1 downto 8) = TwiddlerCommandAddr then @@ -2021,7 +2070,7 @@ end generate; -- LoadTwiddlerRam <= OneOfNDecode(Twiddlers,TwiddlerRAMSel,writestb,Aint(7 downto 6)); -- 16 addresses per Twiddle RAM max, this implies 4 max Twiddlers -- ReadTwiddlerRam <= OneOfNDecode(Twiddlers,TwiddlerRAMSel,Readstb,Aint(7 downto 6)); -- 16 addresses per Twiddle RAM max -- end process TwiddleDecodeProcess; --- +-- -- DoTwiddlerPins: process(TwiddlerOutput) -- begin -- for i in 0 to IOWidth -1 loop -- loop through all the external I/O pins @@ -2039,7 +2088,7 @@ end generate; -- end if; -- end loop; -- end process; --- +-- -- end generate; -- makescalercounters: if ScalerCounters >0 generate -- note scaler counter are in pairs @@ -2050,7 +2099,7 @@ end generate; -- signal ScalerCountSel: std_logic; -- signal ScalerLatchSel: std_logic; -- signal ReadScalerTimer: std_logic; --- +-- -- begin -- scalertimerx : entity work.scalertimer -- port map ( @@ -2058,7 +2107,7 @@ end generate; -- readtimer => ReadScalerTimer, -- clk => clklow -- ); --- +-- -- makescalercounters: for i in 0 to ScalerCounters-1 generate -- scalercounterx: entity work.scalercounter -- port map ( @@ -2071,7 +2120,7 @@ end generate; -- clk => clklow -- ); -- end generate; --- +-- -- DoScalerCounterPins: process(IOBitsCorein) -- begin -- for i in 0 to IOWidth -1 loop -- loop through all the external I/O pins @@ -2085,7 +2134,7 @@ end generate; -- end if; -- end loop; -- end process; --- +-- -- ScalerDecodeProcess : process (Aint,Readstb,ScalerCountSel,ScalerLatchSel) -- begin -- if Aint(AddrWidth-1 downto 8) = ScalerCountAddr then -- @@ -2093,23 +2142,23 @@ end generate; -- else -- ScalerCountSel <= '0'; -- end if; --- +-- -- if Aint(AddrWidth-1 downto 8) = ScalerLatchAddr then -- -- ScalerLatchSel <= '1'; -- else -- ScalerLatchSel <= '0'; -- end if; --- +-- -- if Aint(AddrWidth-1 downto 8) = ScalerTimerAddr and readstb = '1' then -- -- ReadScalerTimer <= '1'; -- else -- ReadScalerTimer <= '0'; -- end if; --- +-- -- ReadScalerCount <= OneOfNDecode(ScalerCounters,ScalerCountSel,readstb,Aint(7 downto 2)); -- ReadScalerLatch <= OneOfNDecode(ScalerCounters,ScalerLatchSel,readstb,Aint(7 downto 2)); -- end process ScalerDecodeProcess; --- +-- -- end generate; -- MuxedEncMIM: if MuxedQCountersMIM > 0 generate diff --git a/HW/hm2/wrappers/MakeBSPIs.vhd b/HW/hm2/wrappers/MakeBSPIs.vhd new file mode 100644 index 00000000..05a97418 --- /dev/null +++ b/HW/hm2/wrappers/MakeBSPIs.vhd @@ -0,0 +1,159 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.std_logic_ARITH.ALL; +use IEEE.std_logic_UNSIGNED.ALL; + +-- Copyright 2016 - 2017 (C) Michael Brown Holotronic +-- holotronic.dk + +-- This file is created for Machinekit intended use +library pin; +use pin.Pintypes.all; +use work.IDROMConst.all; + +use work.oneofndecode.all; + +entity MakeBSPIs is + generic ( + ThePinDesc: PinDescType := PinDesc; + ClockHigh: integer; + ClockMed: integer; + ClockLow: integer; + BusWidth: integer; + AddrWidth: integer; + IOWidth: integer; + STEPGENs: integer; + StepGenTableWidth: integer; + UseStepGenPreScaler: boolean; + UseStepgenIndex: boolean; + UseStepgenProbe: boolean; + timersize: integer; -- = ~480 usec at 33 MHz, ~320 at 50 Mhz + asize: integer; + rsize: integer; + HM2DPLLs: integer; + MuxedQCounters: integer; + MuxedQCountersMIM: integer; + PWMGens: integer; + PWMRefWidth : integer; + UsePWMEnas : boolean; + TPPWMGens : integer; + QCounters: integer; + UseMuxedProbe: boolean; + UseProbe: boolean; + SPIs: integer; + BSPIs: integer; + BSPICSWidth: integer); + Port ( + ibus : in std_logic_vector(BusWidth -1 downto 0) := (others => 'Z'); + obusint : out std_logic_vector(BusWidth -1 downto 0) := (others => 'Z'); + Aint: in std_logic_vector(AddrWidth -1 downto 2); + readstb : in std_logic; + writestb : in std_logic; + CoreDataOut : inout std_logic_vector(IOWidth-1 downto 0) := (others => 'Z'); + IOBitsCorein : inout std_logic_vector(IOWidth-1 downto 0) := (others => '0'); + clklow : in std_logic; + clkmed : in std_logic; + clkhigh : in std_logic; + Probe : inout std_logic; + RateSources: out std_logic_vector(4 downto 0) := (others => 'Z'); + rates: out std_logic_vector (4 downto 0) + ); + +end MakeBSPIs; + + +architecture dataflow of MakeBSPIs is + +-- Signals + +-- I/O port related signals + + begin + makebspimod: if BSPIs >0 generate + signal LoadBSPIData: std_logic_vector(BSPIs -1 downto 0); + signal ReadBSPIData: std_logic_vector(BSPIs -1 downto 0); + signal LoadBSPIDescriptor: std_logic_vector(BSPIs -1 downto 0); + signal ReadBSPIFIFOCOunt: std_logic_vector(BSPIs -1 downto 0); + signal ClearBSPIFIFO: std_logic_vector(BSPIs -1 downto 0); + signal BSPIClk: std_logic_vector(BSPIs -1 downto 0); + signal BSPIIn: std_logic_vector(BSPIs -1 downto 0); + signal BSPIOut: std_logic_vector(BSPIs -1 downto 0); + signal BSPIFrame: std_logic_vector(BSPIs -1 downto 0); + signal BSPIDataSel : std_logic; + signal BSPIFIFOCountSel : std_logic; + signal BSPIDescriptorSel : std_logic; + type BSPICSType is array(BSPIs-1 downto 0) of std_logic_vector(BSPICSWidth-1 downto 0); + signal BSPICS : BSPICSType; + begin + makebspis: for i in 0 to BSPIs -1 generate + bspi: entity work.BufferedSPI + generic map ( + cswidth => BSPICSWidth, + gatedcs => false) + port map ( + clk => clklow, + ibus => ibus, + obus => obusint, + addr => Aint(5 downto 2), + hostpush => LoadBSPIData(i), + hostpop => ReadBSPIData(i), + loaddesc => LoadBSPIDescriptor(i), + loadasend => '0', + clear => ClearBSPIFIFO(i), + readcount => ReadBSPIFIFOCount(i), + spiclk => BSPIClk(i), + spiin => BSPIIn(i), + spiout => BSPIOut(i), + spiframe => BSPIFrame(i), + spicsout => BSPICS(i) + ); + end generate; + + BSPIDecodeProcess : process (Aint,readstb,writestb,BSPIDataSel,BSPIFIFOCountSel,BSPIDescriptorSel) + begin + if Aint(15 downto 8) = BSPIDataAddr then -- BSPI data register select + BSPIDataSel <= '1'; + else + BSPIDataSel <= '0'; + end if; + if Aint(15 downto 8) = BSPIFIFOCountAddr then -- BSPI FIFO count register select + BSPIFIFOCountSel <= '1'; + else + BSPIFIFOCountSel <= '0'; + end if; + if Aint(15 downto 8) = BSPIDescriptorAddr then -- BSPI channel descriptor register select + BSPIDescriptorSel <= '1'; + else + BSPIDescriptorSel <= '0'; + end if; + LoadBSPIData <= OneOfNDecode(BSPIs,BSPIDataSel,writestb,Aint(7 downto 6)); -- 4 max + ReadBSPIData <= OneOfNDecode(BSPIs,BSPIDataSel,readstb,Aint(7 downto 6)); + LoadBSPIDescriptor<= OneOfNDecode(BSPIs,BSPIDescriptorSel,writestb,Aint(5 downto 2)); + ReadBSPIFIFOCOunt <= OneOfNDecode(BSPIs,BSPIFIFOCountSel,readstb,Aint(5 downto 2)); + ClearBSPIFIFO <= OneOfNDecode(BSPIs,BSPIFIFOCountSel,writestb,Aint(5 downto 2)); + end process BSPIDecodeProcess; + + DoBSPIPins: process(BSPIFrame, BSPIOut, BSPIClk, BSPICS, IOBitsCorein) + begin + for i in 0 to IOWidth -1 loop -- loop through all the external I/O pins + if ThePinDesc(i)(15 downto 8) = BSPITag then + case (ThePinDesc(i)(7 downto 0)) is --secondary pin function, drop MSB + when BSPIFramePin => + CoreDataOut(i) <= BSPIFrame(conv_integer(ThePinDesc(i)(23 downto 16))); + when BSPIOutPin => + CoreDataOut(i) <= BSPIOut(conv_integer(ThePinDesc(i)(23 downto 16))); + when BSPIClkPin => + CoreDataOut(i) <= BSPIClk(conv_integer(ThePinDesc(i)(23 downto 16))); + when BSPIInPin => + BSPIIn(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBitsCorein(i); + when others => + CoreDataOut(i) <= BSPICS(conv_integer(ThePinDesc(i)(23 downto 16)))(conv_integer(ThePinDesc(i)(6 downto 0))-5); + -- magic foo, magic foo, what on earth does it do? + -- (this needs to written more clearly!) + end case; + end if; + end loop; + end process; + end generate makebspimod; + +end dataflow; From 3b8e88079cf10e33bf1e6a56f58ab773784eb512 Mon Sep 17 00:00:00 2001 From: Michael Brown Date: Mon, 27 May 2019 17:14:03 +0200 Subject: [PATCH 3/9] DExx_Cramps: Add bspi bitfile config --- .../PIN_3x24_cap_enc_bspi.vhd | 200 ++++++++++++++++++ .../atlas_3x24_cap_enc_bspi.sv | 35 +++ 2 files changed, 235 insertions(+) create mode 100644 HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_enc_bspi.vhd create mode 100644 HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_enc_bspi.sv diff --git a/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_enc_bspi.vhd b/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_enc_bspi.vhd new file mode 100644 index 00000000..ebd49507 --- /dev/null +++ b/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_enc_bspi.vhd @@ -0,0 +1,200 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics +-- http://www.mesanet.com +-- +-- This program is is licensed under a disjunctive dual license giving you +-- the choice of one of the two following sets of free software/open source +-- licensing terms: +-- +-- * GNU General Public License (GPL), version 2.0 or later +-- * 3-clause BSD License +-- +-- +-- The GNU GPL License: +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- +-- +-- The 3-clause BSD License: +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- * Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- * Neither the name of Mesa Electronics nor the names of its +-- contributors may be used to endorse or promote products +-- derived from this software without specific prior written +-- permission. +-- +-- +-- Disclaimer: +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- + +use work.IDROMConst.all; + +package Pintypes is + constant ModuleID : ModuleIDType :=( + -- GTag Version Clock NumInst BaseAddr NumRegisters Strides MultiRegs + (HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask), + (WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask), + (IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask), + (QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask), + (StepGenTag, x"02", ClockLowTag, x"0A", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask), + (PWMTag, x"00", ClockHighTag, x"06", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask), + (LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask), + (NANOADCTag, x"00", ClockLowTag, x"08", NANOADCAddr&PadT, NANOADCNumRegs, x"00", NANOADCBitMask), + (CAPSENSETag, x"00", ClockLowTag, x"04", CAPSENSEAddr&PadT, CAPSENSENumRegs, x"00", CAPSENSEBitMask), + (BSPITag, x"00", ClockLowTag, x"02", BSPIDataAddr&PadT, BSPINumRegs, x"11", BSPIMPBitMask), + (FWIDTag, x"00", ClockLowTag, x"01", FWIDAddr&PadT, FWIDNumRegs, x"00", FWIDMPBitMask), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000") + ); + + + constant PinDesc : PinDescType :=( +-- Base Sec Sec Sec +-- func unit func pin -- hostmot2 DE0-Nano pin Function + IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 00 GPIO_0 01 01 X Step + IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 01 GPIO_0 02 02 X Dir + IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 02 GPIO_0 03 03 Y Step + IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 03 GPIO_0 04 04 Y Dir + IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 04 GPIO_0 05 05 Z Step + IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 05 GPIO_0 06 06 Z Dir + IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 06 GPIO_0 07 07 E0 Step + IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 07 GPIO_0 08 08 E0 Dir + IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 08 GPIO_0 09 09 E1 Step + IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 09 GPIO_0 10 10 E1 Dir + IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 10 GPIO_0 11 13 E2 Step + IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 11 GPIO_0 12 14 E2 Dir + IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 12 GPIO_0 13 15 U Step + IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 13 GPIO_0 14 16 U Dir + IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 14 GPIO_0 15 17 V Step + IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 15 GPIO_0 16 18 V Dir + IOPortTag & x"08" & StepGenTag & StepGenStepPin, -- I/O 16 GPIO_0 17 19 W Step + IOPortTag & x"08" & StepGenTag & StepGenDirPin, -- I/O 17 GPIO_0 18 20 W Dir + IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 18 GPIO_0 19 21 Spindle DAC PWM + IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 19 GPIO_0 20 22 Spindle DAC PWM + IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 20 GPIO_0 21 23 Spindle DAC PWM + IOPortTag & x"03" & PWMTag & PWMAOutPin, -- I/O 21 GPIO_0 22 24 Spindle DAC PWM + IOPortTag & x"04" & PWMTag & PWMAOutPin, -- I/O 22 GPIO_0 23 25 Spindle DAC PWM + IOPortTag & x"05" & PWMTag & PWMAOutPin, -- I/O 23 GPIO_0 24 26 Spindle DAC PWM + IOPortTag & x"00" & NullTag & NullPin, -- I/O 24 GPIO_0 25 27 Limit X-Min + IOPortTag & x"00" & NullTag & NullPin, -- I/O 25 GPIO_0 26 28 Limit X-Max + IOPortTag & x"00" & NullTag & NullPin, -- I/O 26 GPIO_0 27 31 Limit Y-Min + IOPortTag & x"00" & NullTag & NullPin, -- I/O 27 GPIO_0 27 32 Limit Y-Max + IOPortTag & x"00" & NullTag & NullPin, -- I/O 28 GPIO_0 29 33 Limit Z-Min + IOPortTag & x"00" & NullTag & NullPin, -- I/O 29 GPIO_0 30 34 Limit Z-Max + IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 GPIO_0 31 35 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 31 GPIO_0 32 36 Led + IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 GPIO_0 33 37 Axis_ENA_n + IOPortTag & x"00" & NullTag & NullPin, -- I/O 33 GPIO_0 34 38 Machine_Pwr + IOPortTag & x"00" & NullTag & NullPin, -- I/O 34 GPIO_0 35 39 Estop (In) + IOPortTag & x"00" & NullTag & NullPin, -- I/O 35 GPIO_0 36 40 Estop_Sw + +-- Base Sec Sec Sec +-- func unit func pin -- hostmot2 DE0-Nano pin Function + IOPortTag & x"00" & CAPSENSETag & CapChargePin, -- I/O 36 GPIO_1 01 01 CapSense charge + IOPortTag & x"00" & CAPSENSETag & CapSensePin0, -- I/O 37 GPIO_1 02 02 CapSense sense 0 + IOPortTag & x"00" & CAPSENSETag & CapSensePin1, -- I/O 38 GPIO_1 03 03 CapSense sense 1 + IOPortTag & x"00" & CAPSENSETag & CapSensePin2, -- I/O 39 GPIO_1 04 04 CapSense sense 2 + IOPortTag & x"00" & CAPSENSETag & CapSensePin3, -- I/O 40 GPIO_1 05 05 CapSense sense 3 + IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 41 GPIO_1 06 06 Encoder Z + IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 42 GPIO_1 07 07 Encoder B + IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 43 GPIO_1 08 08 Encoder A + IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 44 GPIO_1 09 09 Encoder Z + IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 45 GPIO_1 10 10 Encoder B + IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 46 GPIO_1 11 13 Encoder A + IOPortTag & x"00" & NullTag & NullPin, -- I/O 47 GPIO_1 12 14 just GPIO + IOPortTag & x"00" & BSPITag & BSPIFramePin, -- I/O 48 GPIO_1 13 15 SPI Frame + IOPortTag & x"00" & BSPITag & BSPIOutPin, -- I/O 49 GPIO_1 14 16 SPI Out + IOPortTag & x"00" & BSPITag & BSPIClkPin, -- I/O 50 GPIO_1 15 17 SPI Clk + IOPortTag & x"00" & BSPITag & BSPIInPin, -- I/O 51 GPIO_1 16 18 SPI In + IOPortTag & x"00" & BSPITag & BSPICS2Pin, -- I/O 52 GPIO_1 17 19 SPI Cs + IOPortTag & x"00" & BSPITag & BSPICS1Pin, -- I/O 53 GPIO_1 18 20 SPI Cs + IOPortTag & x"00" & BSPITag & BSPICS0Pin, -- I/O 54 GPIO_1 19 21 SPI Cs + IOPortTag & x"01" & BSPITag & BSPIFramePin, -- I/O 55 GPIO_1 20 22 SPI Frame + IOPortTag & x"01" & BSPITag & BSPIOutPin, -- I/O 56 GPIO_1 21 23 SPI Out + IOPortTag & x"01" & BSPITag & BSPIClkPin, -- I/O 57 GPIO_1 22 24 SPI Clk + IOPortTag & x"01" & BSPITag & BSPIInPin, -- I/O 58 GPIO_1 23 25 SPI In + IOPortTag & x"01" & BSPITag & BSPICS2Pin, -- I/O 59 GPIO_1 24 26 SPI Cs + IOPortTag & x"01" & BSPITag & BSPICS1Pin, -- I/O 60 GPIO_1 25 27 SPI Cs + IOPortTag & x"01" & BSPITag & BSPICS0Pin, -- I/O 61 GPIO_1 26 28 SPI Cs + IOPortTag & x"00" & NullTag & NullPin, -- I/O 62 GPIO_1 27 31 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 63 GPIO_1 28 32 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 64 GPIO_1 29 33 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 65 GPIO_1 30 34 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 66 GPIO_1 31 35 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 67 GPIO_1 32 36 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 68 GPIO_1 33 37 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 69 GPIO_1 34 38 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 70 GPIO_1 35 39 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 71 GPIO_1 36 40 just GPIO + + -- Remainder of 144 pin descriptors are unused + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin); + +end package Pintypes; --PIN_Cramps_3x24_dpll_irq diff --git a/HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_enc_bspi.sv b/HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_enc_bspi.sv new file mode 100644 index 00000000..77762507 --- /dev/null +++ b/HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_enc_bspi.sv @@ -0,0 +1,35 @@ +package boardtype; +// DE0-Nano Dev kit and I/O adaptors specific info +// {STRAIGHT=0,DB25=1} BoardAdaptor; + +parameter BoardAdaptor = 0; + parameter ClockHigh = 200000000; // 200 MHz + parameter ClockMed = 100000000; // 100 MHz + parameter ClockLow = 50000000; // 50 MHz +// parameter BoardNameLow = 32'h41524554; // "TERA" +// parameter BoardNameHigh = 32'h4E304544; // "DE0N" + parameter BoardNameLow = 32'h4153454D; // "MESA" + parameter BoardNameHigh = 32'h35324935; // "5I25" + parameter FPGASize = 9; // Reported as 32-bit value in IDROM.vhd (9 matches Mesanet value for 5i25) + // FIXME: Figure out Mesanet encoding and put something sensible here + parameter FPGAPins = 144; // Total Number of available I/O pins for Hostmot2 use Reported as 32-bit value in IDROM.vhd + // Proposal: On DE0 NANO board Limit to total count of gpios + arduinoconnectors + ltc + adc I/Os + // Maximum of 144 pindesc entries currently hard-coded in IDROM.vhd + parameter IOPorts = 3; // Number of external ports (DE0-Nano_DB25 can have 2 on each 40-pin expansion header) + parameter IOWidth = 72; // Number of total I/O pins = IOPorts * PortWidth + parameter PortWidth = 24; // Number of I/O pins per port: 17 per DB25 + parameter LIOWidth = 0; // Number of local I/Os (used for on-board serial-port on Mesanet cards) + parameter LEDCount = 0; // Number of LEDs + parameter SepClocks = "true"; // Deprecated + parameter OneWS = "true"; // Deprecated + parameter BusWidth = 32; + parameter AddrWidth = 16; + + parameter GPIOWidth = 36; + parameter NumGPIO = 2; + parameter MuxGPIOIOWidth = IOWidth/NumGPIO; + parameter MuxLedWidth = LEDCount/NumGPIO; + parameter ADC = "DE0-Nano-SoC"; + parameter Capsense = 1; + parameter NumSense = 4; +endpackage //_HeaderIncluded From 419976f411185d575bbf14f296860631e7f4d5e1 Mon Sep 17 00:00:00 2001 From: Michael Brown Date: Mon, 27 May 2019 17:15:48 +0200 Subject: [PATCH 4/9] All: Change SRL16E ip cores to Quartus version 15.1 --- HW/cv-megawizard/lpm-ip/lpm_mux16.cmp | 12 ++++++------ HW/cv-megawizard/lpm-ip/lpm_mux16.qip | 2 +- HW/cv-megawizard/lpm-ip/lpm_mux16.vhd | 14 +++++++------- HW/cv-megawizard/lpm-ip/lpm_shiftreg16.cmp | 12 ++++++------ HW/cv-megawizard/lpm-ip/lpm_shiftreg16.qip | 2 +- HW/cv-megawizard/lpm-ip/lpm_shiftreg16.vhd | 14 +++++++------- 6 files changed, 28 insertions(+), 28 deletions(-) diff --git a/HW/cv-megawizard/lpm-ip/lpm_mux16.cmp b/HW/cv-megawizard/lpm-ip/lpm_mux16.cmp index 8c1523ba..16ef71ec 100644 --- a/HW/cv-megawizard/lpm-ip/lpm_mux16.cmp +++ b/HW/cv-megawizard/lpm-ip/lpm_mux16.cmp @@ -1,15 +1,15 @@ ---Copyright (C) 2017 Intel Corporation. All rights reserved. ---Your use of Intel Corporation's design tools, logic functions +--Copyright (C) 1991-2016 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject ---to the terms and conditions of the Intel Program License ---Subscription Agreement, the Intel Quartus Prime License Agreement, ---the Intel MegaCore Function License Agreement, or other +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other --applicable license agreement, including, without limitation, --that your use is for the sole purpose of programming logic ---devices manufactured by Intel and sold by Intel or its +--devices manufactured by Altera and sold by Altera or its --authorized distributors. Please refer to the applicable --agreement for further details. diff --git a/HW/cv-megawizard/lpm-ip/lpm_mux16.qip b/HW/cv-megawizard/lpm-ip/lpm_mux16.qip index da226fc8..bf93dc36 100644 --- a/HW/cv-megawizard/lpm-ip/lpm_mux16.qip +++ b/HW/cv-megawizard/lpm-ip/lpm_mux16.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "LPM_MUX" -set_global_assignment -name IP_TOOL_VERSION "16.1" +set_global_assignment -name IP_TOOL_VERSION "15.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux16.vhd"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux16.cmp"] diff --git a/HW/cv-megawizard/lpm-ip/lpm_mux16.vhd b/HW/cv-megawizard/lpm-ip/lpm_mux16.vhd index b3eea36a..f68c1aec 100644 --- a/HW/cv-megawizard/lpm-ip/lpm_mux16.vhd +++ b/HW/cv-megawizard/lpm-ip/lpm_mux16.vhd @@ -14,22 +14,22 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 16.1.2 Build 203 01/18/2017 SJ Standard Edition +-- 15.1.2 Build 193 02/01/2016 SJ Standard Edition -- ************************************************************ ---Copyright (C) 2017 Intel Corporation. All rights reserved. ---Your use of Intel Corporation's design tools, logic functions +--Copyright (C) 1991-2016 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject ---to the terms and conditions of the Intel Program License ---Subscription Agreement, the Intel Quartus Prime License Agreement, ---the Intel MegaCore Function License Agreement, or other +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other --applicable license agreement, including, without limitation, --that your use is for the sole purpose of programming logic ---devices manufactured by Intel and sold by Intel or its +--devices manufactured by Altera and sold by Altera or its --authorized distributors. Please refer to the applicable --agreement for further details. diff --git a/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.cmp b/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.cmp index ff006534..b43e2e9e 100644 --- a/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.cmp +++ b/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.cmp @@ -1,15 +1,15 @@ ---Copyright (C) 2017 Intel Corporation. All rights reserved. ---Your use of Intel Corporation's design tools, logic functions +--Copyright (C) 1991-2016 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject ---to the terms and conditions of the Intel Program License ---Subscription Agreement, the Intel Quartus Prime License Agreement, ---the Intel MegaCore Function License Agreement, or other +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other --applicable license agreement, including, without limitation, --that your use is for the sole purpose of programming logic ---devices manufactured by Intel and sold by Intel or its +--devices manufactured by Altera and sold by Altera or its --authorized distributors. Please refer to the applicable --agreement for further details. diff --git a/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.qip b/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.qip index 7a52a5ac..78f7fc16 100644 --- a/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.qip +++ b/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" -set_global_assignment -name IP_TOOL_VERSION "16.1" +set_global_assignment -name IP_TOOL_VERSION "15.1" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg16.vhd"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg16_inst.vhd"] diff --git a/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.vhd b/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.vhd index 4fafdc53..bb046bce 100644 --- a/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.vhd +++ b/HW/cv-megawizard/lpm-ip/lpm_shiftreg16.vhd @@ -14,22 +14,22 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 16.1.2 Build 203 01/18/2017 SJ Standard Edition +-- 15.1.2 Build 193 02/01/2016 SJ Standard Edition -- ************************************************************ ---Copyright (C) 2017 Intel Corporation. All rights reserved. ---Your use of Intel Corporation's design tools, logic functions +--Copyright (C) 1991-2016 Altera Corporation. All rights reserved. +--Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject ---to the terms and conditions of the Intel Program License ---Subscription Agreement, the Intel Quartus Prime License Agreement, ---the Intel MegaCore Function License Agreement, or other +--to the terms and conditions of the Altera Program License +--Subscription Agreement, the Altera Quartus Prime License Agreement, +--the Altera MegaCore Function License Agreement, or other --applicable license agreement, including, without limitation, --that your use is for the sole purpose of programming logic ---devices manufactured by Intel and sold by Intel or its +--devices manufactured by Altera and sold by Altera or its --authorized distributors. Please refer to the applicable --agreement for further details. From 22f38a26725766f4f92a3de0f1e92509ab9b4cb8 Mon Sep 17 00:00:00 2001 From: Michael Brown Date: Mon, 27 May 2019 17:17:46 +0200 Subject: [PATCH 5/9] DExx_Cramps: remove former bspi config --- .../PIN_3x24_cap_bspi.vhd | 200 ------------------ .../atlas_3x24_cap_bspi.sv | 35 --- 2 files changed, 235 deletions(-) delete mode 100644 HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_bspi.vhd delete mode 100644 HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_bspi.sv diff --git a/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_bspi.vhd b/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_bspi.vhd deleted file mode 100644 index 2d04bc3f..00000000 --- a/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_bspi.vhd +++ /dev/null @@ -1,200 +0,0 @@ -library IEEE; -use IEEE.std_logic_1164.all; -- defines std_logic types -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - --- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics --- http://www.mesanet.com --- --- This program is is licensed under a disjunctive dual license giving you --- the choice of one of the two following sets of free software/open source --- licensing terms: --- --- * GNU General Public License (GPL), version 2.0 or later --- * 3-clause BSD License --- --- --- The GNU GPL License: --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA --- --- --- The 3-clause BSD License: --- --- Redistribution and use in source and binary forms, with or without --- modification, are permitted provided that the following conditions --- are met: --- --- * Redistributions of source code must retain the above copyright --- notice, this list of conditions and the following disclaimer. --- --- * Redistributions in binary form must reproduce the above --- copyright notice, this list of conditions and the following --- disclaimer in the documentation and/or other materials --- provided with the distribution. --- --- * Neither the name of Mesa Electronics nor the names of its --- contributors may be used to endorse or promote products --- derived from this software without specific prior written --- permission. --- --- --- Disclaimer: --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS --- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT --- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE --- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, --- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; --- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER --- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT --- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN --- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- - -use work.IDROMConst.all; - -package Pintypes is - constant ModuleID : ModuleIDType :=( - -- GTag Version Clock NumInst BaseAddr NumRegisters Strides MultiRegs - (HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask), - (WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask), - (IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask), - (QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask), - (StepGenTag, x"02", ClockLowTag, x"0A", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask), - (PWMTag, x"00", ClockHighTag, x"06", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask), - (LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask), - (NANOADCTag, x"00", ClockLowTag, x"08", NANOADCAddr&PadT, NANOADCNumRegs, x"00", NANOADCBitMask), - (CAPSENSETag, x"00", ClockLowTag, x"04", CAPSENSEAddr&PadT, CAPSENSENumRegs, x"00", CAPSENSEBitMask), - (BSPITag, x"00", ClockLowTag, x"01", BSPIDataAddr&PadT, BSPINumRegs, x"11", BSPIMPBitMask), - (FWIDTag, x"00", ClockLowTag, x"01", FWIDAddr&PadT, FWIDNumRegs, x"00", FWIDMPBitMask), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), - (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000") - ); - - - constant PinDesc : PinDescType :=( --- Base Sec Sec Sec --- func unit func pin -- hostmot2 DE0-Nano pin Function - IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 00 GPIO_0 01 01 X Step - IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 01 GPIO_0 02 02 X Dir - IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 02 GPIO_0 03 03 Y Step - IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 03 GPIO_0 04 04 Y Dir - IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 04 GPIO_0 05 05 Z Step - IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 05 GPIO_0 06 06 Z Dir - IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 06 GPIO_0 07 07 E0 Step - IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 07 GPIO_0 08 08 E0 Dir - IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 08 GPIO_0 09 09 E1 Step - IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 09 GPIO_0 10 10 E1 Dir - IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 10 GPIO_0 11 13 E2 Step - IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 11 GPIO_0 12 14 E2 Dir - IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 12 GPIO_0 13 15 U Step - IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 13 GPIO_0 14 16 U Dir - IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 14 GPIO_0 15 17 V Step - IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 15 GPIO_0 16 18 V Dir - IOPortTag & x"08" & StepGenTag & StepGenStepPin, -- I/O 16 GPIO_0 17 19 W Step - IOPortTag & x"08" & StepGenTag & StepGenDirPin, -- I/O 17 GPIO_0 18 20 W Dir - IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 18 GPIO_0 19 21 Spindle DAC PWM - IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 19 GPIO_0 20 22 Spindle DAC PWM - IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 20 GPIO_0 21 23 Spindle DAC PWM - IOPortTag & x"03" & PWMTag & PWMAOutPin, -- I/O 21 GPIO_0 22 24 Spindle DAC PWM - IOPortTag & x"04" & PWMTag & PWMAOutPin, -- I/O 22 GPIO_0 23 25 Spindle DAC PWM - IOPortTag & x"05" & PWMTag & PWMAOutPin, -- I/O 23 GPIO_0 24 26 Spindle DAC PWM - IOPortTag & x"00" & NullTag & NullPin, -- I/O 24 GPIO_0 25 27 Limit X-Min - IOPortTag & x"00" & NullTag & NullPin, -- I/O 25 GPIO_0 26 28 Limit X-Max - IOPortTag & x"00" & NullTag & NullPin, -- I/O 26 GPIO_0 27 31 Limit Y-Min - IOPortTag & x"00" & NullTag & NullPin, -- I/O 27 GPIO_0 27 32 Limit Y-Max - IOPortTag & x"00" & NullTag & NullPin, -- I/O 28 GPIO_0 29 33 Limit Z-Min - IOPortTag & x"00" & NullTag & NullPin, -- I/O 29 GPIO_0 30 34 Limit Z-Max - IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 GPIO_0 31 35 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 31 GPIO_0 32 36 Led - IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 GPIO_0 33 37 Axis_ENA_n - IOPortTag & x"00" & NullTag & NullPin, -- I/O 33 GPIO_0 34 38 Machine_Pwr - IOPortTag & x"00" & NullTag & NullPin, -- I/O 34 GPIO_0 35 39 Estop (In) - IOPortTag & x"00" & NullTag & NullPin, -- I/O 35 GPIO_0 36 40 Estop_Sw - --- Base Sec Sec Sec --- func unit func pin -- hostmot2 DE0-Nano pin Function - IOPortTag & x"00" & CAPSENSETag & CapChargePin, -- I/O 36 GPIO_1 01 01 CapSense charge - IOPortTag & x"00" & CAPSENSETag & CapSensePin0, -- I/O 37 GPIO_1 02 02 CapSense sense 0 - IOPortTag & x"00" & CAPSENSETag & CapSensePin1, -- I/O 38 GPIO_1 03 03 CapSense sense 1 - IOPortTag & x"00" & CAPSENSETag & CapSensePin2, -- I/O 39 GPIO_1 04 04 CapSense sense 2 - IOPortTag & x"00" & CAPSENSETag & CapSensePin3, -- I/O 40 GPIO_1 05 05 CapSense sense 3 - IOPortTag & x"00" & NullTag & NullPin, -- I/O 41 GPIO_1 06 06 Encoder 1 Z - IOPortTag & x"00" & NullTag & NullPin, -- I/O 42 GPIO_1 07 07 Encoder 1 B - IOPortTag & x"00" & NullTag & NullPin, -- I/O 43 GPIO_1 08 08 Encoder 1 A - IOPortTag & x"00" & NullTag & NullPin, -- I/O 44 GPIO_1 09 09 Encoder 2 Z - IOPortTag & x"00" & NullTag & NullPin, -- I/O 45 GPIO_1 10 10 Encoder 2 B - IOPortTag & x"00" & NullTag & NullPin, -- I/O 46 GPIO_1 11 13 Encoder 2 A - IOPortTag & x"00" & NullTag & NullPin, -- I/O 47 GPIO_1 12 14 just GPIO - IOPortTag & x"00" & BSPITag & BSPIFramePin, -- I/O 48 GPIO_1 13 15 SPI Frame - IOPortTag & x"00" & BSPITag & BSPIOutPin, -- I/O 49 GPIO_1 14 16 SPI Out - IOPortTag & x"00" & BSPITag & BSPIClkPin, -- I/O 50 GPIO_1 15 17 SPI Clk - IOPortTag & x"00" & BSPITag & BSPIInPin, -- I/O 51 GPIO_1 16 18 SPI In - IOPortTag & x"00" & BSPITag & BSPICS3Pin, -- I/O 52 GPIO_1 17 19 SPI Cs - IOPortTag & x"00" & BSPITag & BSPICS2Pin, -- I/O 53 GPIO_1 18 20 SPI Cs - IOPortTag & x"00" & BSPITag & BSPICS1Pin, -- I/O 54 GPIO_1 19 21 SPI Cs - IOPortTag & x"00" & BSPITag & BSPICS0Pin, -- I/O 55 GPIO_1 20 22 SPI Cs - IOPortTag & x"00" & NullTag & NullPin, -- I/O 56 GPIO_1 21 23 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 57 GPIO_1 22 24 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 58 GPIO_1 23 25 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 59 GPIO_1 24 26 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 60 GPIO_1 25 27 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 61 GPIO_1 26 28 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 62 GPIO_1 27 31 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 63 GPIO_1 28 32 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 64 GPIO_1 29 33 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 65 GPIO_1 30 34 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 66 GPIO_1 31 35 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 67 GPIO_1 32 36 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 68 GPIO_1 33 37 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 69 GPIO_1 34 38 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 70 GPIO_1 35 39 just GPIO - IOPortTag & x"00" & NullTag & NullPin, -- I/O 71 GPIO_1 36 40 just GPIO - - -- Remainder of 144 pin descriptors are unused - emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, - emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, - emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, - emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, - emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, - emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, - emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, - emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, - emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin); - -end package Pintypes; --PIN_Cramps_3x24_dpll_irq diff --git a/HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_bspi.sv b/HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_bspi.sv deleted file mode 100644 index 77762507..00000000 --- a/HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_bspi.sv +++ /dev/null @@ -1,35 +0,0 @@ -package boardtype; -// DE0-Nano Dev kit and I/O adaptors specific info -// {STRAIGHT=0,DB25=1} BoardAdaptor; - -parameter BoardAdaptor = 0; - parameter ClockHigh = 200000000; // 200 MHz - parameter ClockMed = 100000000; // 100 MHz - parameter ClockLow = 50000000; // 50 MHz -// parameter BoardNameLow = 32'h41524554; // "TERA" -// parameter BoardNameHigh = 32'h4E304544; // "DE0N" - parameter BoardNameLow = 32'h4153454D; // "MESA" - parameter BoardNameHigh = 32'h35324935; // "5I25" - parameter FPGASize = 9; // Reported as 32-bit value in IDROM.vhd (9 matches Mesanet value for 5i25) - // FIXME: Figure out Mesanet encoding and put something sensible here - parameter FPGAPins = 144; // Total Number of available I/O pins for Hostmot2 use Reported as 32-bit value in IDROM.vhd - // Proposal: On DE0 NANO board Limit to total count of gpios + arduinoconnectors + ltc + adc I/Os - // Maximum of 144 pindesc entries currently hard-coded in IDROM.vhd - parameter IOPorts = 3; // Number of external ports (DE0-Nano_DB25 can have 2 on each 40-pin expansion header) - parameter IOWidth = 72; // Number of total I/O pins = IOPorts * PortWidth - parameter PortWidth = 24; // Number of I/O pins per port: 17 per DB25 - parameter LIOWidth = 0; // Number of local I/Os (used for on-board serial-port on Mesanet cards) - parameter LEDCount = 0; // Number of LEDs - parameter SepClocks = "true"; // Deprecated - parameter OneWS = "true"; // Deprecated - parameter BusWidth = 32; - parameter AddrWidth = 16; - - parameter GPIOWidth = 36; - parameter NumGPIO = 2; - parameter MuxGPIOIOWidth = IOWidth/NumGPIO; - parameter MuxLedWidth = LEDCount/NumGPIO; - parameter ADC = "DE0-Nano-SoC"; - parameter Capsense = 1; - parameter NumSense = 4; -endpackage //_HeaderIncluded From e30d6d751674a310ee91776a7b80b60d7159df35 Mon Sep 17 00:00:00 2001 From: Michael Brown Date: Mon, 27 May 2019 17:21:34 +0200 Subject: [PATCH 6/9] DExx_Cramps: cleanup file --- HW/hm2/wrappers/MakeIOPorts.vhd | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/HW/hm2/wrappers/MakeIOPorts.vhd b/HW/hm2/wrappers/MakeIOPorts.vhd index 7e6865d9..6a6e4c49 100644 --- a/HW/hm2/wrappers/MakeIOPorts.vhd +++ b/HW/hm2/wrappers/MakeIOPorts.vhd @@ -39,23 +39,23 @@ entity MakeIOPorts is RegStride0: integer; RegStride1: integer; -- - ClockMed: integer; +-- ClockMed: integer; BusWidth: integer; AddrWidth: integer; - STEPGENs: integer; - StepGenTableWidth: integer; - UseStepGenPreScaler: boolean; - UseStepgenIndex: boolean; - UseStepgenProbe: boolean; - timersize: integer; -- = ~480 usec at 33 MHz, ~320 at 50 Mhz - asize: integer; - rsize: integer; - PWMGens: integer; - PWMRefWidth : integer; - UsePWMEnas : boolean; - QCounters: integer; - UseMuxedProbe: boolean; - UseProbe: boolean; +-- STEPGENs: integer; +-- StepGenTableWidth: integer; +-- UseStepGenPreScaler: boolean; +-- UseStepgenIndex: boolean; +-- UseStepgenProbe: boolean; +-- timersize: integer; -- = ~480 usec at 33 MHz, ~320 at 50 Mhz +-- asize: integer; +-- rsize: integer; +-- PWMGens: integer; +-- PWMRefWidth : integer; +-- UsePWMEnas : boolean; +-- QCounters: integer; +-- UseMuxedProbe: boolean; +-- UseProbe: boolean; UseWatchDog: boolean; UseDemandModeDMA: boolean; UseIRQlogic: boolean; @@ -115,7 +115,7 @@ architecture dataflow of MakeIOPorts is signal PortSel: std_logic; -- I/O port related signals - signal RefCountBus : std_logic_vector(PWMRefWidth-1 downto 0); +-- signal RefCountBus : std_logic_vector(PWMRefWidth-1 downto 0); signal LoadPortCmd: std_logic_vector(IOPorts -1 downto 0); signal ReadPortCmd: std_logic_vector(IOPorts -1 downto 0); From b988a7b7218fd1b8b5664d84436ddc6efca4c025 Mon Sep 17 00:00:00 2001 From: Michael Brown Date: Mon, 27 May 2019 17:22:59 +0200 Subject: [PATCH 7/9] ALL: change hm2 write timing so a register is only written once Signed-off-by: Michael Brown --- HW/cv-ip/hm2reg_io/hm2reg_io_hw.tcl | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/HW/cv-ip/hm2reg_io/hm2reg_io_hw.tcl b/HW/cv-ip/hm2reg_io/hm2reg_io_hw.tcl index dd613817..f0140541 100644 --- a/HW/cv-ip/hm2reg_io/hm2reg_io_hw.tcl +++ b/HW/cv-ip/hm2reg_io/hm2reg_io_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 15.1 -# Mon May 16 17:56:54 CEST 2016 +# Mon May 27 16:40:18 CEST 2019 # DO NOT MODIFY # -# hm2reg_io "hm2reg-io" v1.0 -# Michael Brown 2016.05.16.17:56:54 +# hm2reg_io "generic-uio,ui_pdrv" v1.0 +# Michael Brown 2019.05.27.16:40:18 # hostmot2 interface for mesa hdl source # @@ -26,7 +26,7 @@ set_module_property OPAQUE_ADDRESS_MAP true set_module_property GROUP Interfaces set_module_property AUTHOR "Michael Brown" set_module_property ICON_PATH machinekiticon.png -set_module_property DISPLAY_NAME "generic-uio,ui_pdrv" +set_module_property DISPLAY_NAME generic-uio,ui_pdrv set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE true set_module_property REPORT_TO_TALKBACK false @@ -144,8 +144,7 @@ set_interface_property slave readWaitStates 2 set_interface_property slave readWaitTime 2 set_interface_property slave setupTime 2 set_interface_property slave timingUnits Cycles -set_interface_property slave writeWaitStates 2 -set_interface_property slave writeWaitTime 2 +set_interface_property slave writeWaitTime 0 set_interface_property slave ENABLED true set_interface_property slave EXPORT_OF "" set_interface_property slave PORT_NAME_MAP "" From cf035069c539dda57131a2190499f204f9f5412f Mon Sep 17 00:00:00 2001 From: Michael Brown Date: Tue, 28 May 2019 12:38:16 +0200 Subject: [PATCH 8/9] DExx_Cramps: Add dbspi config --- .../PIN_3x24_cap_enc_dbspi.vhd | 200 ++++++++++++++++++ .../atlas_3x24_cap_enc_dbspi.sv | 35 +++ 2 files changed, 235 insertions(+) create mode 100644 HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_enc_dbspi.vhd create mode 100644 HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_enc_dbspi.sv diff --git a/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_enc_dbspi.vhd b/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_enc_dbspi.vhd new file mode 100644 index 00000000..8ea8ca71 --- /dev/null +++ b/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_enc_dbspi.vhd @@ -0,0 +1,200 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics +-- http://www.mesanet.com +-- +-- This program is is licensed under a disjunctive dual license giving you +-- the choice of one of the two following sets of free software/open source +-- licensing terms: +-- +-- * GNU General Public License (GPL), version 2.0 or later +-- * 3-clause BSD License +-- +-- +-- The GNU GPL License: +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +-- +-- +-- The 3-clause BSD License: +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- * Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- +-- * Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- * Neither the name of Mesa Electronics nor the names of its +-- contributors may be used to endorse or promote products +-- derived from this software without specific prior written +-- permission. +-- +-- +-- Disclaimer: +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- + +use work.IDROMConst.all; + +package Pintypes is + constant ModuleID : ModuleIDType :=( + -- GTag Version Clock NumInst BaseAddr NumRegisters Strides MultiRegs + (HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask), + (WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask), + (IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask), + (QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask), + (StepGenTag, x"02", ClockLowTag, x"0A", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask), + (PWMTag, x"00", ClockHighTag, x"06", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask), + (LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask), + (NANOADCTag, x"00", ClockLowTag, x"08", NANOADCAddr&PadT, NANOADCNumRegs, x"00", NANOADCBitMask), + (CAPSENSETag, x"00", ClockLowTag, x"04", CAPSENSEAddr&PadT, CAPSENSENumRegs, x"00", CAPSENSEBitMask), + (DBSPITag, x"00", ClockLowTag, x"02", DBSPIDataAddr&PadT, DBSPINumRegs, x"11", DBSPIMPBitMask), + (FWIDTag, x"00", ClockLowTag, x"01", FWIDAddr&PadT, FWIDNumRegs, x"00", FWIDMPBitMask), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), + (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000") + ); + + + constant PinDesc : PinDescType :=( +-- Base Sec Sec Sec +-- func unit func pin -- hostmot2 DE0-Nano pin Function + IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 00 GPIO_0 01 01 X Step + IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 01 GPIO_0 02 02 X Dir + IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 02 GPIO_0 03 03 Y Step + IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 03 GPIO_0 04 04 Y Dir + IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 04 GPIO_0 05 05 Z Step + IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 05 GPIO_0 06 06 Z Dir + IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 06 GPIO_0 07 07 E0 Step + IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 07 GPIO_0 08 08 E0 Dir + IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 08 GPIO_0 09 09 E1 Step + IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 09 GPIO_0 10 10 E1 Dir + IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 10 GPIO_0 11 13 E2 Step + IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 11 GPIO_0 12 14 E2 Dir + IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 12 GPIO_0 13 15 U Step + IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 13 GPIO_0 14 16 U Dir + IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 14 GPIO_0 15 17 V Step + IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 15 GPIO_0 16 18 V Dir + IOPortTag & x"08" & StepGenTag & StepGenStepPin, -- I/O 16 GPIO_0 17 19 W Step + IOPortTag & x"08" & StepGenTag & StepGenDirPin, -- I/O 17 GPIO_0 18 20 W Dir + IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 18 GPIO_0 19 21 Spindle DAC PWM + IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 19 GPIO_0 20 22 Spindle DAC PWM + IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 20 GPIO_0 21 23 Spindle DAC PWM + IOPortTag & x"03" & PWMTag & PWMAOutPin, -- I/O 21 GPIO_0 22 24 Spindle DAC PWM + IOPortTag & x"04" & PWMTag & PWMAOutPin, -- I/O 22 GPIO_0 23 25 Spindle DAC PWM + IOPortTag & x"05" & PWMTag & PWMAOutPin, -- I/O 23 GPIO_0 24 26 Spindle DAC PWM + IOPortTag & x"00" & NullTag & NullPin, -- I/O 24 GPIO_0 25 27 Limit X-Min + IOPortTag & x"00" & NullTag & NullPin, -- I/O 25 GPIO_0 26 28 Limit X-Max + IOPortTag & x"00" & NullTag & NullPin, -- I/O 26 GPIO_0 27 31 Limit Y-Min + IOPortTag & x"00" & NullTag & NullPin, -- I/O 27 GPIO_0 27 32 Limit Y-Max + IOPortTag & x"00" & NullTag & NullPin, -- I/O 28 GPIO_0 29 33 Limit Z-Min + IOPortTag & x"00" & NullTag & NullPin, -- I/O 29 GPIO_0 30 34 Limit Z-Max + IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 GPIO_0 31 35 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 31 GPIO_0 32 36 Led + IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 GPIO_0 33 37 Axis_ENA_n + IOPortTag & x"00" & NullTag & NullPin, -- I/O 33 GPIO_0 34 38 Machine_Pwr + IOPortTag & x"00" & NullTag & NullPin, -- I/O 34 GPIO_0 35 39 Estop (In) + IOPortTag & x"00" & NullTag & NullPin, -- I/O 35 GPIO_0 36 40 Estop_Sw + +-- Base Sec Sec Sec +-- func unit func pin -- hostmot2 DE0-Nano pin Function + IOPortTag & x"00" & CAPSENSETag & CapChargePin, -- I/O 36 GPIO_1 01 01 CapSense charge + IOPortTag & x"00" & CAPSENSETag & CapSensePin0, -- I/O 37 GPIO_1 02 02 CapSense sense 0 + IOPortTag & x"00" & CAPSENSETag & CapSensePin1, -- I/O 38 GPIO_1 03 03 CapSense sense 1 + IOPortTag & x"00" & CAPSENSETag & CapSensePin2, -- I/O 39 GPIO_1 04 04 CapSense sense 2 + IOPortTag & x"00" & CAPSENSETag & CapSensePin3, -- I/O 40 GPIO_1 05 05 CapSense sense 3 + IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 41 GPIO_1 06 06 Encoder Z + IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 42 GPIO_1 07 07 Encoder B + IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 43 GPIO_1 08 08 Encoder A + IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 44 GPIO_1 09 09 Encoder Z + IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 45 GPIO_1 10 10 Encoder B + IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 46 GPIO_1 11 13 Encoder A + IOPortTag & x"00" & DBSPITag & DBSPIOutPin, -- I/O 47 GPIO_1 12 14 SPI Out + IOPortTag & x"00" & DBSPITag & DBSPIClkPin, -- I/O 48 GPIO_1 13 15 SPI Clk + IOPortTag & x"00" & DBSPITag & DBSPIInPin, -- I/O 49 GPIO_1 14 16 SPI In + IOPortTag & x"00" & DBSPITag & DBSPICS0Pin, -- I/O 50 GPIO_1 15 17 SPI Cs + IOPortTag & x"00" & DBSPITag & DBSPICS1Pin, -- I/O 51 GPIO_1 16 18 SPI Cs + IOPortTag & x"00" & DBSPITag & DBSPICS2Pin, -- I/O 52 GPIO_1 17 19 SPI Cs + IOPortTag & x"00" & DBSPITag & DBSPICS3Pin, -- I/O 53 GPIO_1 18 20 SPI Cs + IOPortTag & x"00" & DBSPITag & DBSPICS4Pin, -- I/O 54 GPIO_1 19 21 SPI Cs + IOPortTag & x"01" & DBSPITag & DBSPICS5Pin, -- I/O 55 GPIO_1 20 22 SPI Cs + IOPortTag & x"01" & DBSPITag & DBSPICS6Pin, -- I/O 56 GPIO_1 21 23 SPI Cs + IOPortTag & x"01" & DBSPITag & DBSPICS7Pin, -- I/O 57 GPIO_1 22 24 SPI Cs + IOPortTag & x"01" & NullTag & NullPin, -- I/O 58 GPIO_1 23 25 just GPIO + IOPortTag & x"01" & NullTag & NullPin, -- I/O 59 GPIO_1 24 26 just GPIO + IOPortTag & x"01" & NullTag & NullPin, -- I/O 60 GPIO_1 25 27 just GPIO + IOPortTag & x"01" & NullTag & NullPin, -- I/O 61 GPIO_1 26 28 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 62 GPIO_1 27 31 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 63 GPIO_1 28 32 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 64 GPIO_1 29 33 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 65 GPIO_1 30 34 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 66 GPIO_1 31 35 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 67 GPIO_1 32 36 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 68 GPIO_1 33 37 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 69 GPIO_1 34 38 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 70 GPIO_1 35 39 just GPIO + IOPortTag & x"00" & NullTag & NullPin, -- I/O 71 GPIO_1 36 40 just GPIO + + -- Remainder of 144 pin descriptors are unused + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, + emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin); + +end package Pintypes; --PIN_Cramps_3x24_dpll_irq diff --git a/HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_enc_dbspi.sv b/HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_enc_dbspi.sv new file mode 100644 index 00000000..77762507 --- /dev/null +++ b/HW/hm2/config/DExx_Nano_xxx_Cramps/atlas_3x24_cap_enc_dbspi.sv @@ -0,0 +1,35 @@ +package boardtype; +// DE0-Nano Dev kit and I/O adaptors specific info +// {STRAIGHT=0,DB25=1} BoardAdaptor; + +parameter BoardAdaptor = 0; + parameter ClockHigh = 200000000; // 200 MHz + parameter ClockMed = 100000000; // 100 MHz + parameter ClockLow = 50000000; // 50 MHz +// parameter BoardNameLow = 32'h41524554; // "TERA" +// parameter BoardNameHigh = 32'h4E304544; // "DE0N" + parameter BoardNameLow = 32'h4153454D; // "MESA" + parameter BoardNameHigh = 32'h35324935; // "5I25" + parameter FPGASize = 9; // Reported as 32-bit value in IDROM.vhd (9 matches Mesanet value for 5i25) + // FIXME: Figure out Mesanet encoding and put something sensible here + parameter FPGAPins = 144; // Total Number of available I/O pins for Hostmot2 use Reported as 32-bit value in IDROM.vhd + // Proposal: On DE0 NANO board Limit to total count of gpios + arduinoconnectors + ltc + adc I/Os + // Maximum of 144 pindesc entries currently hard-coded in IDROM.vhd + parameter IOPorts = 3; // Number of external ports (DE0-Nano_DB25 can have 2 on each 40-pin expansion header) + parameter IOWidth = 72; // Number of total I/O pins = IOPorts * PortWidth + parameter PortWidth = 24; // Number of I/O pins per port: 17 per DB25 + parameter LIOWidth = 0; // Number of local I/Os (used for on-board serial-port on Mesanet cards) + parameter LEDCount = 0; // Number of LEDs + parameter SepClocks = "true"; // Deprecated + parameter OneWS = "true"; // Deprecated + parameter BusWidth = 32; + parameter AddrWidth = 16; + + parameter GPIOWidth = 36; + parameter NumGPIO = 2; + parameter MuxGPIOIOWidth = IOWidth/NumGPIO; + parameter MuxLedWidth = LEDCount/NumGPIO; + parameter ADC = "DE0-Nano-SoC"; + parameter Capsense = 1; + parameter NumSense = 4; +endpackage //_HeaderIncluded From b3c491f6e81680e0b74eaef0485e105786cdc802 Mon Sep 17 00:00:00 2001 From: Michael Brown Date: Tue, 28 May 2019 12:57:34 +0200 Subject: [PATCH 9/9] DExx_Cramps: add dbspi (Buffered SPI with cs decoder) support Signed-off-by: Michael Brown --- .../PIN_3x24_cap_enc_dbspi.vhd | 8 +- HW/hm2/hm3_socfpga.qip | 1 + HW/hm2/hostmot3.vhd | 250 ++++-------------- HW/hm2/wrappers/MakeDBSPIs.vhd | 159 +++++++++++ 4 files changed, 217 insertions(+), 201 deletions(-) create mode 100644 HW/hm2/wrappers/MakeDBSPIs.vhd diff --git a/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_enc_dbspi.vhd b/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_enc_dbspi.vhd index 8ea8ca71..6c33dc5a 100644 --- a/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_enc_dbspi.vhd +++ b/HW/hm2/config/DExx_Nano_xxx_Cramps/PIN_3x24_cap_enc_dbspi.vhd @@ -81,7 +81,7 @@ package Pintypes is (LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask), (NANOADCTag, x"00", ClockLowTag, x"08", NANOADCAddr&PadT, NANOADCNumRegs, x"00", NANOADCBitMask), (CAPSENSETag, x"00", ClockLowTag, x"04", CAPSENSEAddr&PadT, CAPSENSENumRegs, x"00", CAPSENSEBitMask), - (DBSPITag, x"00", ClockLowTag, x"02", DBSPIDataAddr&PadT, DBSPINumRegs, x"11", DBSPIMPBitMask), + (DBSPITag, x"00", ClockLowTag, x"01", DBSPIDataAddr&PadT, DBSPINumRegs, x"11", DBSPIMPBitMask), (FWIDTag, x"00", ClockLowTag, x"01", FWIDAddr&PadT, FWIDNumRegs, x"00", FWIDMPBitMask), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), @@ -168,9 +168,9 @@ package Pintypes is IOPortTag & x"00" & DBSPITag & DBSPICS2Pin, -- I/O 52 GPIO_1 17 19 SPI Cs IOPortTag & x"00" & DBSPITag & DBSPICS3Pin, -- I/O 53 GPIO_1 18 20 SPI Cs IOPortTag & x"00" & DBSPITag & DBSPICS4Pin, -- I/O 54 GPIO_1 19 21 SPI Cs - IOPortTag & x"01" & DBSPITag & DBSPICS5Pin, -- I/O 55 GPIO_1 20 22 SPI Cs - IOPortTag & x"01" & DBSPITag & DBSPICS6Pin, -- I/O 56 GPIO_1 21 23 SPI Cs - IOPortTag & x"01" & DBSPITag & DBSPICS7Pin, -- I/O 57 GPIO_1 22 24 SPI Cs + IOPortTag & x"00" & DBSPITag & DBSPICS5Pin, -- I/O 55 GPIO_1 20 22 SPI Cs + IOPortTag & x"00" & DBSPITag & DBSPICS6Pin, -- I/O 56 GPIO_1 21 23 SPI Cs + IOPortTag & x"00" & DBSPITag & DBSPICS7Pin, -- I/O 57 GPIO_1 22 24 SPI Cs IOPortTag & x"01" & NullTag & NullPin, -- I/O 58 GPIO_1 23 25 just GPIO IOPortTag & x"01" & NullTag & NullPin, -- I/O 59 GPIO_1 24 26 just GPIO IOPortTag & x"01" & NullTag & NullPin, -- I/O 60 GPIO_1 25 27 just GPIO diff --git a/HW/hm2/hm3_socfpga.qip b/HW/hm2/hm3_socfpga.qip index 1015f192..baa7a308 100644 --- a/HW/hm2/hm3_socfpga.qip +++ b/HW/hm2/hm3_socfpga.qip @@ -31,6 +31,7 @@ set_global_assignment -name VHDL_FILE ../../hm2/wrappers/MakePwmgens.vhd set_global_assignment -name VHDL_FILE ../../hm2/wrappers/MakeTPPWMGens.vhd set_global_assignment -name VHDL_FILE ../../hm2/wrappers/MakeSPIs.vhd set_global_assignment -name VHDL_FILE ../../hm2/wrappers/MakeBSPIs.vhd +set_global_assignment -name VHDL_FILE ../../hm2/wrappers/MakeDBSPIs.vhd # HM2 cores: set_global_assignment -name VHDL_FILE ../../hm2/kubstepgenzi.vhd diff --git a/HW/hm2/hostmot3.vhd b/HW/hm2/hostmot3.vhd index 648ddaef..3719c308 100644 --- a/HW/hm2/hostmot3.vhd +++ b/HW/hm2/hostmot3.vhd @@ -161,7 +161,7 @@ constant UsePWMEnas: boolean := PinExists(ThePinDesc,PWMTag,PWMCEnaPin); constant TPPWMGens : integer := NumberOfModules(TheModuleID,TPPWMTag); constant SPIs: integer := NumberOfModules(TheModuleID,SPITag); constant BSPIs: integer := NumberOfModules(TheModuleID,BSPITag); --- constant DBSPIs: integer := NumberOfModules(TheModuleID,DBSPITag); +constant DBSPIs: integer := NumberOfModules(TheModuleID,DBSPITag); --constant SSSIs: integer := NumberOfModules(TheModuleID,SSSITag); --constant FAbss: integer := NumberOfModules(TheModuleID,FAbsTag); --constant BISSs: integer := NumberOfModules(TheModuleID,BISSTag); @@ -196,7 +196,7 @@ constant StepGenTableWidth: integer := MaxPinsPerModule(ThePinDesc,StepGenTag); -- extract how many BSPI CS pins are needed constant BSPICSWidth: integer := CountPinsInRange(ThePinDesc,BSPITag,BSPICS0Pin,BSPICS7Pin); -- extract how many DBSPI CS pins are needed ---constant DBSPICSWidth: integer := CountPinsInRange(ThePinDesc,DBSPITag,DBSPICS0Pin,DBSPICS7Pin); +constant DBSPICSWidth: integer := CountPinsInRange(ThePinDesc,DBSPITag,DBSPICS0Pin,DBSPICS7Pin); constant UseProbe: boolean := PinExists(ThePinDesc,QCountTag,QCountProbePin); constant UseMuxedProbe: boolean := PinExists(ThePinDesc,MuxedQCountTag,MuxedQCountProbePin); @@ -675,201 +675,57 @@ GenMakeBSPIs: if BSPIs >0 generate ); end generate; --- --- makebspimod: if BSPIs >0 generate --- signal LoadBSPIData: std_logic_vector(BSPIs -1 downto 0); --- signal ReadBSPIData: std_logic_vector(BSPIs -1 downto 0); --- signal LoadBSPIDescriptor: std_logic_vector(BSPIs -1 downto 0); --- signal ReadBSPIFIFOCOunt: std_logic_vector(BSPIs -1 downto 0); --- signal ClearBSPIFIFO: std_logic_vector(BSPIs -1 downto 0); --- signal BSPIClk: std_logic_vector(BSPIs -1 downto 0); --- signal BSPIIn: std_logic_vector(BSPIs -1 downto 0); --- signal BSPIOut: std_logic_vector(BSPIs -1 downto 0); --- signal BSPIFrame: std_logic_vector(BSPIs -1 downto 0); --- signal BSPIDataSel : std_logic; --- signal BSPIFIFOCountSel : std_logic; --- signal BSPIDescriptorSel : std_logic; --- type BSPICSType is array(BSPIs-1 downto 0) of std_logic_vector(BSPICSWidth-1 downto 0); --- signal BSPICS : BSPICSType; --- begin --- makebspis: for i in 0 to BSPIs -1 generate --- bspi: entity work.BufferedSPI --- generic map ( --- cswidth => BSPICSWidth, --- gatedcs => false) --- port map ( --- clk => clklow, --- ibus => ibusint, --- obus => obusint, --- addr => Aint(5 downto 2), --- hostpush => LoadBSPIData(i), --- hostpop => ReadBSPIData(i), --- loaddesc => LoadBSPIDescriptor(i), --- loadasend => '0', --- clear => ClearBSPIFIFO(i), --- readcount => ReadBSPIFIFOCount(i), --- spiclk => BSPIClk(i), --- spiin => BSPIIn(i), --- spiout => BSPIOut(i), --- spiframe => BSPIFrame(i), --- spicsout => BSPICS(i) --- ); --- end generate; --- --- BSPIDecodeProcess : process (Aint,Readstb,writestb,BSPIDataSel,BSPIFIFOCountSel,BSPIDescriptorSel) --- begin --- if Aint(AddrWidth-1 downto 8) = BSPIDataAddr then -- BSPI data register select --- BSPIDataSel <= '1'; --- else --- BSPIDataSel <= '0'; --- end if; --- if Aint(AddrWidth-1 downto 8) = BSPIFIFOCountAddr then -- BSPI FIFO count register select --- BSPIFIFOCountSel <= '1'; --- else --- BSPIFIFOCountSel <= '0'; --- end if; --- if Aint(AddrWidth-1 downto 8) = BSPIDescriptorAddr then -- BSPI channel descriptor register select --- BSPIDescriptorSel <= '1'; --- else --- BSPIDescriptorSel <= '0'; --- end if; --- LoadBSPIData <= OneOfNDecode(BSPIs,BSPIDataSel,writestb,Aint(7 downto 6)); -- 4 max --- ReadBSPIData <= OneOfNDecode(BSPIs,BSPIDataSel,Readstb,Aint(7 downto 6)); --- LoadBSPIDescriptor<= OneOfNDecode(BSPIs,BSPIDescriptorSel,writestb,Aint(5 downto 2)); --- ReadBSPIFIFOCOunt <= OneOfNDecode(BSPIs,BSPIFIFOCountSel,Readstb,Aint(5 downto 2)); --- ClearBSPIFIFO <= OneOfNDecode(BSPIs,BSPIFIFOCountSel,writestb,Aint(5 downto 2)); --- end process BSPIDecodeProcess; --- --- DoBSPIPins: process(BSPIFrame, BSPIOut, BSPIClk, BSPICS, IOBitsCorein) --- begin --- for i in 0 to IOWidth -1 loop -- loop through all the external I/O pins --- if ThePinDesc(i)(15 downto 8) = BSPITag then --- case (ThePinDesc(i)(7 downto 0)) is --secondary pin function, drop MSB --- when BSPIFramePin => --- IOBitsCorein(i) <= BSPIFrame(conv_integer(ThePinDesc(i)(23 downto 16))); --- when BSPIOutPin => --- IOBitsCorein(i) <= BSPIOut(conv_integer(ThePinDesc(i)(23 downto 16))); --- when BSPIClkPin => --- IOBitsCorein(i) <= BSPIClk(conv_integer(ThePinDesc(i)(23 downto 16))); --- when BSPIInPin => --- BSPIIn(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBitsCorein(i); --- when others => --- IOBitsCorein(i) <= BSPICS(conv_integer(ThePinDesc(i)(23 downto 16)))(conv_integer(ThePinDesc(i)(6 downto 0))-5); --- magic foo, magic foo, what on earth does it do? --- (this needs to written more clearly!) --- end case; --- end if; --- end loop; --- end process; --- end generate; --- --- makedbspimod: if DBSPIs >0 generate --- signal LoadDBSPIData: std_logic_vector(DBSPIs -1 downto 0); --- signal ReadDBSPIData: std_logic_vector(DBSPIs -1 downto 0); --- signal LoadDBSPIDescriptor: std_logic_vector(DBSPIs -1 downto 0); --- signal ReadDBSPIFIFOCOunt: std_logic_vector(DBSPIs -1 downto 0); --- signal ClearDBSPIFIFO: std_logic_vector(DBSPIs -1 downto 0); --- signal DBSPIClk: std_logic_vector(DBSPIs -1 downto 0); --- signal DBSPIIn: std_logic_vector(DBSPIs -1 downto 0); --- signal DBSPIOut: std_logic_vector(DBSPIs -1 downto 0); --- type DBSPICSType is array(DBSPIs-1 downto 0) of std_logic_vector(DBSPICSWidth-1 downto 0); --- signal DBSPICS : DBSPICSType; --- signal DBSPIDataSel : std_logic; --- signal DBSPIFIFOCountSel : std_logic; --- signal DBSPIDescriptorSel : std_logic; --- begin --- makedbspis: for i in 0 to DBSPIs -1 generate --- bspi: entity work.BufferedSPI --- generic map ( --- cswidth => DBSPICSWidth, --- gatedcs => true --- ) --- port map ( --- clk => clklow, --- ibus => ibusint, --- obus => obusint, --- addr => Aint(5 downto 2), --- hostpush => LoadDBSPIData(i), --- hostpop => ReadDBSPIData(i), --- loaddesc => LoadDBSPIDescriptor(i), --- loadasend => '0', --- clear => ClearDBSPIFIFO(i), --- readcount => ReadDBSPIFIFOCount(i), --- spiclk => DBSPIClk(i), --- spiin => DBSPIIn(i), --- spiout => DBSPIOut(i), --- spicsout => DBSPICS(i) --- ); --- end generate; --- --- DBSPIDecodeProcess : process (Aint,Readstb,writestb,DBSPIDataSel,DBSPIFIFOCountSel,DBSPIDescriptorSel) --- begin --- if Aint(AddrWidth-1 downto 8) = DBSPIDataAddr then -- DBSPI data register select --- DBSPIDataSel <= '1'; --- else --- DBSPIDataSel <= '0'; --- end if; --- if Aint(AddrWidth-1 downto 8) = DBSPIFIFOCountAddr then -- DBSPI FIFO count register select --- DBSPIFIFOCountSel <= '1'; --- else --- DBSPIFIFOCountSel <= '0'; --- end if; --- if Aint(AddrWidth-1 downto 8) = DBSPIDescriptorAddr then -- DBSPI channel descriptor register select --- DBSPIDescriptorSel <= '1'; --- else --- DBSPIDescriptorSel <= '0'; --- end if; --- LoadDBSPIData <= OneOfNDecode(DBSPIs,DBSPIDataSel,writestb,Aint(7 downto 6)); -- 4 max --- ReadDBSPIData <= OneOfNDecode(DBSPIs,DBSPIDataSel,Readstb,Aint(7 downto 6)); --- LoadDBSPIDescriptor<= OneOfNDecode(DBSPIs,DBSPIDescriptorSel,writestb,Aint(5 downto 2)); --- ReadDBSPIFIFOCOunt <= OneOfNDecode(DBSPIs,DBSPIFIFOCountSel,Readstb,Aint(5 downto 2)); --- ClearDBSPIFIFO <= OneOfNDecode(DBSPIs,DBSPIFIFOCountSel,writestb,Aint(5 downto 2)); --- end process DBSPIDecodeProcess; --- --- DoDBSPIPins: process(DBSPIOut, DBSPIClk, DBSPICS, IOBitsCorein) --- begin --- for i in 0 to IOWidth -1 loop -- loop through all the external I/O pins --- if ThePinDesc(i)(15 downto 8) = DBSPITag then --- case (ThePinDesc(i)(7 downto 0)) is --secondary pin function, drop MSB --- when DBSPIOutPin => --- IOBitsCorein(i) <= DBSPIOut(conv_integer(ThePinDesc(i)(23 downto 16))); --- when DBSPIClkPin => --- IOBitsCorein(i) <= DBSPIClk(conv_integer(ThePinDesc(i)(23 downto 16))); when DBSPIInPin => --- DBSPIIn(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBitsCorein(i); --- when others => --- IOBitsCorein(i) <= DBSPICS(conv_integer(ThePinDesc(i)(23 downto 16)))(conv_integer(ThePinDesc(i)(6 downto 0))-5); --- magic foo, magic foo, what on earth does it do? --- (this needs to written more clearly!) --- end case; --- end if; --- end loop; --- end process; --- --- DoLocalDDBSPIPins: process(LIOBits,DBSPICS,DBSPIClk,DBSPIOut) -- only for 4I69 LIO currently --- begin --- for i in 0 to LIOWidth -1 loop -- loop through all the local I/O pins --- report("Doing DBSPI LIOLoop: "& integer'image(i)); --- if ThePinDesc(i+IOWidth)(15 downto 8) = DBSPITag then -- GTag (Local I/O starts at end of external I/O) --- case (ThePinDesc(i+IOWidth)(7 downto 0)) is --secondary pin function, drop MSB --- when DBSPIOutPin => --- LIOBits(i) <= DBSPIOut(conv_integer(ThePinDesc(i+IOWidth)(23 downto 16))); --- report("Local DBSPIOutPin found at LIOBit " & integer'image(i)); --- when DBSPIClkPin => --- LIOBits(i) <= DBSPIClk(conv_integer(ThePinDesc(i+IOWidth)(23 downto 16))); --- report("Local DBSPClkPin found at LIOBit " & integer'image(i)); --- when DBSPIInPin => --- DBSPIIn(conv_integer(ThePinDesc(i+IOWidth)(23 downto 16))) <= LIOBits(i); --- report("Local DBSPIInPin found at LIOBit " & integer'image(i)); --- when others => --- LIOBits(i) <= DBSPICS(conv_integer(ThePinDesc(i+IOWidth)(23 downto 16)))(conv_integer(ThePinDesc(i+IOWidth)(6 downto 0))-5); --- report("Local DBSPICSPin found at LIOBit " & integer'image(i)); --- magic foo, magic foo, what on earth does it do? --- (this needs to written more clearly!) --- end case; --- end if; --- end loop; --- end process; --- end generate; +GenMakeDBSPIs: if DBSPIs >0 generate + MakeDBSPIs : entity work.MakeDBSPIs + generic map ( + ThePinDesc => ThePinDesc, + ClockHigh => ClockHigh, + ClockMed => ClockMed, + ClockLow => ClockLow, + BusWidth => BusWidth, + AddrWidth => AddrWidth, + IOWidth => IOWidth, + STEPGENs => STEPGENs, + StepGenTableWidth => StepGenTableWidth, + UseStepGenPreScaler => UseStepGenPreScaler, + UseStepgenIndex => UseStepgenIndex, + UseStepgenProbe => UseStepgenProbe, + timersize => 14, + asize => 48, + rsize => 32, + HM2DPLLs => HM2DPLLs, + MuxedQCounters => MuxedQCounters, + MuxedQCountersMIM => MuxedQCountersMIM, + PWMGens => PWMGens, + PWMRefWidth => PWMRefWidth, + UsePWMEnas => UsePWMEnas, + TPPWMGens => TPPWMGens, + QCounters => QCounters, + UseMuxedProbe => UseMuxedProbe, + UseProbe => UseProbe, + SPIs => SPIs, + BSPIs => BSPIs, + BSPICSWidth => BSPICSWidth, + DBSPIs => DBSPIs, + DBSPICSWidth => DBSPICSWidth + ) + port map ( + ibus => ibusint, + obusint => obusint, + Aint => Aint, + readstb => readstb, + writestb => writestb, + CoreDataOut => CoreDataOut, + IOBitsCorein => IOBitsCorein, + clklow => clklow, + clkmed => clkmed, + clkhigh => clkhigh, + PRobe => PRobe, + RateSources => RateSources, + rates => rates + ); +end generate; + -- -- makesssimod: if SSSIs >0 generate -- signal LoadSSSIData0: std_logic_vector(SSSIs -1 downto 0); diff --git a/HW/hm2/wrappers/MakeDBSPIs.vhd b/HW/hm2/wrappers/MakeDBSPIs.vhd new file mode 100644 index 00000000..97a1e6d4 --- /dev/null +++ b/HW/hm2/wrappers/MakeDBSPIs.vhd @@ -0,0 +1,159 @@ +library IEEE; +use IEEE.std_logic_1164.all; -- defines std_logic types +use IEEE.std_logic_ARITH.ALL; +use IEEE.std_logic_UNSIGNED.ALL; + +-- Copyright 2016 - 2017 (C) Michael Brown Holotronic +-- holotronic.dk + +-- This file is created for Machinekit intended use +library pin; +use pin.Pintypes.all; +use work.IDROMConst.all; + +use work.oneofndecode.all; + +entity MakeDBSPIs is + generic ( + ThePinDesc: PinDescType := PinDesc; + ClockHigh: integer; + ClockMed: integer; + ClockLow: integer; + BusWidth: integer; + AddrWidth: integer; + IOWidth: integer; + STEPGENs: integer; + StepGenTableWidth: integer; + UseStepGenPreScaler: boolean; + UseStepgenIndex: boolean; + UseStepgenProbe: boolean; + timersize: integer; -- = ~480 usec at 33 MHz, ~320 at 50 Mhz + asize: integer; + rsize: integer; + HM2DPLLs: integer; + MuxedQCounters: integer; + MuxedQCountersMIM: integer; + PWMGens: integer; + PWMRefWidth : integer; + UsePWMEnas : boolean; + TPPWMGens : integer; + QCounters: integer; + UseMuxedProbe: boolean; + UseProbe: boolean; + SPIs: integer; + BSPIs: integer; + BSPICSWidth: integer; + DBSPIs: integer; + DBSPICSWidth: integer); + Port ( + ibus : in std_logic_vector(BusWidth -1 downto 0) := (others => 'Z'); + obusint : out std_logic_vector(BusWidth -1 downto 0) := (others => 'Z'); + Aint: in std_logic_vector(AddrWidth -1 downto 2); + readstb : in std_logic; + writestb : in std_logic; + CoreDataOut : inout std_logic_vector(IOWidth-1 downto 0) := (others => 'Z'); + IOBitsCorein : inout std_logic_vector(IOWidth-1 downto 0) := (others => '0'); + clklow : in std_logic; + clkmed : in std_logic; + clkhigh : in std_logic; + Probe : inout std_logic; + RateSources: out std_logic_vector(4 downto 0) := (others => 'Z'); + rates: out std_logic_vector (4 downto 0) + ); + +end MakeDBSPIs; + + +architecture dataflow of MakeDBSPIs is + +-- Signals + +-- I/O port related signals + + begin + makedbspimod: if DBSPIs >0 generate + signal LoadDBSPIData: std_logic_vector(DBSPIs -1 downto 0); + signal ReadDBSPIData: std_logic_vector(DBSPIs -1 downto 0); + signal LoadDBSPIDescriptor: std_logic_vector(DBSPIs -1 downto 0); + signal ReadDBSPIFIFOCount: std_logic_vector(DBSPIs -1 downto 0); + signal ClearDBSPIFIFO: std_logic_vector(DBSPIs -1 downto 0); + signal DBSPIClk: std_logic_vector(DBSPIs -1 downto 0); + signal DBSPIIn: std_logic_vector(DBSPIs -1 downto 0); + signal DBSPIOut: std_logic_vector(DBSPIs -1 downto 0); + type DBSPICSType is array(DBSPIs-1 downto 0) of std_logic_vector(DBSPICSWidth-1 downto 0); + signal DBSPICS : DBSPICSType; + signal DBSPIDataSel : std_logic; + signal DBSPIFIFOCountSel : std_logic; + signal DBSPIDescriptorSel : std_logic; + begin + makedbspis: for i in 0 to DBSPIs -1 generate + bspi: entity work.BufferedSPI + generic map ( + cswidth => DBSPICSWidth, + gatedcs => true + ) + port map ( + clk => clklow, + ibus => ibus, + obus => obusint, + addr => Aint(5 downto 2), + hostpush => LoadDBSPIData(i), + hostpop => ReadDBSPIData(i), + loaddesc => LoadDBSPIDescriptor(i), + loadasend => '0', + clear => ClearDBSPIFIFO(i), + readcount => ReadDBSPIFIFOCount(i), + spiclk => DBSPIClk(i), + spiin => DBSPIIn(i), + spiout => DBSPIOut(i), + spicsout => DBSPICS(i) + ); + end generate; + + DBSPIDecodeProcess : process (Aint,Readstb,writestb,DBSPIDataSel,DBSPIFIFOCountSel,DBSPIDescriptorSel) + begin + if Aint(15 downto 8) = DBSPIDataAddr then -- DBSPI data register select + DBSPIDataSel <= '1'; + else + DBSPIDataSel <= '0'; + end if; + if Aint(15 downto 8) = DBSPIFIFOCountAddr then -- DBSPI FIFO count register select + DBSPIFIFOCountSel <= '1'; + else + DBSPIFIFOCountSel <= '0'; + end if; + if Aint(15 downto 8) = DBSPIDescriptorAddr then -- DBSPI channel descriptor register select + DBSPIDescriptorSel <= '1'; + else + DBSPIDescriptorSel <= '0'; + end if; + LoadDBSPIData <= OneOfNDecode(DBSPIs,DBSPIDataSel,writestb,Aint(7 downto 6)); -- 4 max + ReadDBSPIData <= OneOfNDecode(DBSPIs,DBSPIDataSel,Readstb,Aint(7 downto 6)); + LoadDBSPIDescriptor<= OneOfNDecode(DBSPIs,DBSPIDescriptorSel,writestb,Aint(5 downto 2)); + ReadDBSPIFIFOCount <= OneOfNDecode(DBSPIs,DBSPIFIFOCountSel,Readstb,Aint(5 downto 2)); + ClearDBSPIFIFO <= OneOfNDecode(DBSPIs,DBSPIFIFOCountSel,writestb,Aint(5 downto 2)); + end process DBSPIDecodeProcess; + + DoDBSPIPins: process(DBSPIOut, DBSPIClk, DBSPICS, IOBitsCorein) + begin + for i in 0 to IOWidth -1 loop -- loop through all the external I/O pins + if ThePinDesc(i)(15 downto 8) = DBSPITag then + case (ThePinDesc(i)(7 downto 0)) is --secondary pin function, drop MSB + when DBSPIOutPin => + CoreDataOut(i) <= DBSPIOut(conv_integer(ThePinDesc(i)(23 downto 16))); + when DBSPIClkPin => + CoreDataOut(i) <= DBSPIClk(conv_integer(ThePinDesc(i)(23 downto 16))); + when DBSPIInPin => + DBSPIIn(conv_integer(ThePinDesc(i)(23 downto 16))) <= IOBitsCorein(i); + when others => + CoreDataOut(i) <= DBSPICS(conv_integer(ThePinDesc(i)(23 downto 16)))(conv_integer(ThePinDesc(i)(6 downto 0))-5); + -- magic foo, magic foo, what on earth does it do? + -- (this needs to written more clearly!) + end case; + end if; + end loop; + end process; + + end generate makedbspimod; + +end dataflow;