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Merged
merged 3 commits into from
Mar 16, 2018
Merged

Late Fix for package building errors, introduced in january #92

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27cf5ea
Update makefiles in DE0 DE10 Nano configs to let *.qip files remain o…
the-snowwhite Feb 27, 2018
b0f0a21
Bugfix:
the-snowwhite Feb 27, 2018
baa2c9c
remove signaltapfile from DEo_Nano
the-snowwhite Feb 28, 2018
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191 changes: 2 additions & 189 deletions HW/QuartusProjects/DE0_Nano_SoC_Cramps/DE0_Nano_SoC_Cramps.qsf
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2 changes: 1 addition & 1 deletion HW/QuartusProjects/DE0_Nano_SoC_Cramps/Makefile
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Expand Up @@ -120,7 +120,7 @@ AR_REGEX += \
Makefile ip readme.txt ds5 \
altera_avalon* *.qpf *.qsf *.sdc *.v *.sv *.vhd *.qsys *.tcl *.stp \
*.sed quartus.ini *.sof *.rbf *.sopcinfo *.jdi output_files \
hps_isw_handoff */*.svd */synthesis/*.svd *.dts *.dtb *.xml *.sh *.ipx *.in *.mif\
hps_isw_handoff */*.svd */synthesis/*.svd *.dts *.dtb *.xml *.sh *.ipx *.in *.mif *.qip\
$(SOFTWARE_DIR)

AR_FILTER_OUT += %_tb.qsys
Expand Down
22 changes: 2 additions & 20 deletions HW/QuartusProjects/DE10_Nano_FB_Cramps/DE10_Nano_FB_Cramps.sv
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Expand Up @@ -117,15 +117,15 @@ parameter NumIOAddrReg = 6;
wire hps_cold_reset;
wire hps_warm_reset;
wire hps_debug_reset;
wire [27:0] stm_hw_events;
// wire [27:0] stm_hw_events;
wire fpga_clk_50;
wire clk_75;

// connection of internal logics
// assign LED[5:1] = fpga_led_internal | {7'b0000000, led_level};
assign LED[5:1] = fpga_led_internal;
assign fpga_clk_50=FPGA_CLK1_50;
assign stm_hw_events = {{15{1'b0}}, SW, fpga_led_internal, fpga_debounced_buttons};
// assign stm_hw_events = {{15{1'b0}}, SW, fpga_led_internal, fpga_debounced_buttons};
// hm2
wire [AddrWidth-1:2] hm_address;
wire [31:0] hm_datao;
Expand Down Expand Up @@ -261,10 +261,6 @@ soc_system u0 (
.dipsw_pio_external_connection_export ( SW ), // dipsw_pio_external_connection.export
.button_pio_external_connection_export ( fpga_debounced_buttons ), // button_pio_external_connection.export
.hps_0_h2f_reset_reset_n ( hps_fpga_reset_n ), // hps_0_h2f_reset.reset_n
.hps_0_f2h_cold_reset_req_reset_n (~hps_cold_reset ), // hps_0_f2h_cold_reset_req.reset_n
.hps_0_f2h_debug_reset_req_reset_n (~hps_debug_reset ), // hps_0_f2h_debug_reset_req.reset_n
.hps_0_f2h_stm_hw_events_stm_hwevents (stm_hw_events ), // hps_0_f2h_stm_hw_events.stm_hwevents
.hps_0_f2h_warm_reset_req_reset_n (~hps_warm_reset ), // hps_0_f2h_warm_reset_req.reset_n
// hm2reg_io_0_conduit
.mk_io_hm2_datain (busdata_out), // .hm2_datain
.mk_io_hm2_dataout (hm_datai), // hm2reg.hm2_dataout
Expand All @@ -284,31 +280,24 @@ top_io_modules top_io_modules_inst
.reset_n(hps_fpga_reset_n) , // input reset_n_sig
.button_in(KEY) , // input [KEY_WIDTH-1:0] button_in_sig
.button_out(fpga_debounced_buttons) , // output [KEY_WIDTH-1:0] button_out_sig
.hps_cold_reset(hps_cold_reset) , // output hps_cold_reset_sig
.hps_warm_reset(hps_warm_reset) , // output hps_warm_reset_sig
.hps_debug_reset(hps_debug_reset) , // output hps_debug_reset_sig
.LED(LED[0]) // output LED_sig
);

defparam top_io_modules_inst.KEY_WIDTH = 2;

// Mesa code ------------------------------------------------------//

//assign clklow_sig = fpga_clk_50;
assign clkhigh_sig = hm_clk_high;
assign clkmed_sig = hm_clk_med;


genvar ig;
generate for(ig=0;ig<NumGPIO;ig=ig+1) begin : iosigloop
// assign io_leds_sig[ig] = hm2_leds_sig[(ig*MuxLedWidth)+:MuxLedWidth];
assign io_bitsout_sig[ig] = hm2_bitsout_sig[(ig*MuxGPIOIOWidth)+:MuxGPIOIOWidth];
assign io_bitsin_sig[ig] = hm2_bitsin_sig[(ig*MuxGPIOIOWidth)+:MuxGPIOIOWidth];
end
endgenerate

//assign LED[7:6] = ~hm2_leds_sig[1:0];

gpio_adr_decoder_reg gpio_adr_decoder_reg_inst
(
.CLOCK(fpga_clk_50) , // input CLOCK_sig
Expand All @@ -331,9 +320,6 @@ gpio_adr_decoder_reg gpio_adr_decoder_reg_inst
.ADC_SCK_o(ADC_SCK), // output ADC_SCK_o_sig
.ADC_SDI_o(ADC_SDI), // output ADC_SDI_o_sig
.ADC_SDO_i(ADC_SDO), // input ADC_SDO_i_sig
// CAP_Sensors
// .sense({ARDUINO_IO[9],ARDUINO_IO[10],ARDUINO_IO[11],ARDUINO_IO[12]}),
// .charge(ARDUINO_IO[13]),
.buttons(fpga_debounced_buttons)
);

Expand All @@ -342,7 +328,6 @@ defparam gpio_adr_decoder_reg_inst.BusWidth = BusWidth;
defparam gpio_adr_decoder_reg_inst.GPIOWidth = GPIOWidth;
defparam gpio_adr_decoder_reg_inst.MuxGPIOIOWidth = MuxGPIOIOWidth;
defparam gpio_adr_decoder_reg_inst.NumIOAddrReg = NumIOAddrReg;
//defparam gpio_adr_decoder_reg_inst.MuxLedWidth = MuxLedWidth;
defparam gpio_adr_decoder_reg_inst.NumGPIO = NumGPIO;
defparam gpio_adr_decoder_reg_inst.Capsense = Capsense;
defparam gpio_adr_decoder_reg_inst.NumSense = 4;
Expand All @@ -359,12 +344,9 @@ HostMot3_cfg HostMot3_inst
.clkmed(clkmed_sig) , // input clkmed_sig -- Processor clock --> sserialwa, twiddle
.clkhigh(clkhigh_sig) , // input clkhigh_sig -- High speed clock --> most
.intirq(int_sig) , // output int_sig --int => LINT, ---> PCI ?
// .dreq(dreq_sig) , // output dreq_sig
// .demandmode(demandmode_sig) , // output demandmode_sig
.iobitsouttop(hm2_bitsout_sig) , // inout [IOWidth-1:0] --iobits => IOBITS,-- external I/O bits
.iobitsintop(hm2_bitsin_sig) // inout [IOWidth-1:0] --iobits => IOBITS,-- external I/O bits
// .liobits(liobits_sig) , // inout [lIOWidth-1:0] --liobits_sig
// .rates(rates_sig) , // output [4:0] rates_sig
// .leds(hm2_leds_sig) // output [ledcount-1:0] leds_sig --leds => LEDS
);

Expand Down
2 changes: 1 addition & 1 deletion HW/QuartusProjects/DE10_Nano_FB_Cramps/Makefile
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Expand Up @@ -120,7 +120,7 @@ AR_REGEX += \
Makefile ip readme.txt ds5 \
altera_avalon* *.qpf *.qsf *.sdc *.v *.sv *.vhd *.qsys *.tcl *.stp \
*.sed quartus.ini *.sof *.rbf *.sopcinfo *.jdi output_files \
hps_isw_handoff */*.svd */synthesis/*.svd *.dts *.dtb *.xml *.sh *.ipx *.in *.mif\
hps_isw_handoff */*.svd */synthesis/*.svd *.dts *.dtb *.xml *.sh *.ipx *.in *.mif *.qip\
$(SOFTWARE_DIR)

AR_FILTER_OUT += %_tb.qsys
Expand Down
2 changes: 1 addition & 1 deletion HW/QuartusProjects/DE10_Nano_FB_Cramps/hm3_pin_config.qip
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@@ -1,2 +1,2 @@
# I/O Daughterboard adaptor specific:
set_global_assignment -name VHDL_FILE ../../hm2/config/DE10_Nano_FB_Cramps/PIN_3x24_cap.vhd -library pin
set_global_assignment -name VHDL_FILE ../../hm2/config/DE10_Nano_FB_Cramps/PIN_3x24.vhd -library pin
32 changes: 8 additions & 24 deletions HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system.qsys
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Expand Up @@ -413,26 +413,10 @@
internal="dipsw_pio.external_connection"
type="conduit"
dir="end" />
<interface
name="hps_0_f2h_cold_reset_req"
internal="hps_0.f2h_cold_reset_req"
type="reset"
dir="end" />
<interface
name="hps_0_f2h_debug_reset_req"
internal="hps_0.f2h_debug_reset_req"
type="reset"
dir="end" />
<interface
name="hps_0_f2h_stm_hw_events"
internal="hps_0.f2h_stm_hw_events"
type="conduit"
dir="end" />
<interface
name="hps_0_f2h_warm_reset_req"
internal="hps_0.f2h_warm_reset_req"
type="reset"
dir="end" />
<interface name="hps_0_f2h_cold_reset_req" internal="hps_0.f2h_cold_reset_req" />
<interface name="hps_0_f2h_debug_reset_req" internal="hps_0.f2h_debug_reset_req" />
<interface name="hps_0_f2h_stm_hw_events" internal="hps_0.f2h_stm_hw_events" />
<interface name="hps_0_f2h_warm_reset_req" internal="hps_0.f2h_warm_reset_req" />
<interface
name="hps_0_h2f_reset"
internal="hps_0.h2f_reset"
Expand Down Expand Up @@ -680,13 +664,13 @@
<parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" />
<parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" />
<parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" />
<parameter name="F2SCLK_COLDRST_Enable" value="true" />
<parameter name="F2SCLK_DBGRST_Enable" value="true" />
<parameter name="F2SCLK_COLDRST_Enable" value="false" />
<parameter name="F2SCLK_DBGRST_Enable" value="false" />
<parameter name="F2SCLK_PERIPHCLK_Enable" value="false" />
<parameter name="F2SCLK_PERIPHCLK_FREQ" value="0" />
<parameter name="F2SCLK_SDRAMCLK_Enable" value="false" />
<parameter name="F2SCLK_SDRAMCLK_FREQ" value="0" />
<parameter name="F2SCLK_WARMRST_Enable" value="true" />
<parameter name="F2SCLK_WARMRST_Enable" value="false" />
<parameter name="F2SDRAM_Type">Avalon-MM Bidirectional</parameter>
<parameter name="F2SDRAM_Width" value="256" />
<parameter name="F2SINTERRUPT_Enable" value="true" />
Expand Down Expand Up @@ -966,7 +950,7 @@
<parameter name="SPIS1_Mode" value="N/A" />
<parameter name="SPIS1_PinMuxing" value="Unused" />
<parameter name="STARVE_LIMIT" value="10" />
<parameter name="STM_Enable" value="true" />
<parameter name="STM_Enable" value="false" />
<parameter name="SYS_INFO_DEVICE_FAMILY" value="Cyclone V" />
<parameter name="TEST_Enable" value="false" />
<parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
Expand Down
37 changes: 6 additions & 31 deletions HW/hm2/config/DE10_Nano_FB_Cramps/hostmot3_cfg.vhd
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Expand Up @@ -125,33 +125,8 @@ end HostMot3_cfg;

architecture arch of HostMot3_cfg is

signal ibustop_sig : std_logic_vector(BusWidth -1 downto 0);
-- signal obustop_sig : std_logic_vector(BusWidth -1 downto 0);
signal addr_sig : std_logic_vector(AddrWidth -1 downto 2);
signal readstb_sig : std_logic;
signal writestb_sig : std_logic;
signal intirq_sig : std_logic;
signal iobitsouttop_sig : std_logic_vector(IOWidth -1 downto 0);
signal iobitsintop_sig : std_logic_vector(IOWidth -1 downto 0);
signal leds_sig : std_logic_vector(LEDCount -1 downto 0);

begin

process (clkhigh)
begin
if rising_edge(clkhigh) then
ibustop_sig <= ibustop;
-- obustop <= obustop_sig;
addr_sig <= addr;
readstb_sig <= readstb;
writestb_sig <= writestb;
-- intirq <= intirq_sig;
-- iobitsouttop <= iobitsouttop_sig;
iobitsintop_sig <= iobitsintop;
-- leds <= leds_sig;
end if;
end process;

aHostMot3_cfg: entity work.HostMot3
generic map (
ThePinDesc => PinDesc,
Expand Down Expand Up @@ -184,20 +159,20 @@ begin
RegStride0 => 256,
RegStride1 => 256 )
port map (
ibustop => ibustop_sig,
ibustop => ibustop,
obustop => obustop,
addr => addr_sig,
readstb => readstb_sig,
writestb => writestb_sig,
addr => addr,
readstb => readstb,
writestb => writestb,
clklow => clklow,
clkmed => clkmed,
clkhigh => clkhigh,
intirq => intirq,
dreq => dreq,
demandmode => demandmode,
iobitsouttop => iobitsouttop,
iobitsintop => iobitsintop_sig,
iobitsintop => iobitsintop,
-- liobits => liobits,
-- rates => rates,
leds => leds );
end arch;
end arch;