diff --git a/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system.qsys b/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system.qsys index b3c13526..9de94339 100644 --- a/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system.qsys +++ b/HW/QuartusProjects/DE0_Nano_SoC_Cramps/soc_system.qsys @@ -13,7 +13,7 @@ { datum _sortIndex { - value = "3"; + value = "10"; type = "int"; } } @@ -26,7 +26,7 @@ } datum baseAddress { - value = "65728"; + value = "20480"; type = "String"; } } @@ -34,7 +34,7 @@ { datum _sortIndex { - value = "10"; + value = "0"; type = "int"; } } @@ -42,7 +42,7 @@ { datum _sortIndex { - value = "4"; + value = "9"; type = "int"; } } @@ -63,7 +63,7 @@ } datum baseAddress { - value = "65664"; + value = "16512"; type = "String"; } } @@ -71,7 +71,7 @@ { datum _sortIndex { - value = "8"; + value = "3"; type = "int"; } } @@ -79,12 +79,17 @@ { datum _sortIndex { - value = "11"; + value = "12"; type = "int"; } } element hm2reg_io_0.slave { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } datum baseAddress { value = "262144"; @@ -95,7 +100,7 @@ { datum _sortIndex { - value = "0"; + value = "1"; type = "int"; } } @@ -111,7 +116,7 @@ { datum _sortIndex { - value = "1"; + value = "2"; type = "int"; } } @@ -119,7 +124,7 @@ { datum _sortIndex { - value = "9"; + value = "5"; type = "int"; } } @@ -137,7 +142,7 @@ } datum baseAddress { - value = "196608"; + value = "3840"; type = "String"; } } @@ -158,7 +163,7 @@ } datum baseAddress { - value = "131072"; + value = "8192"; type = "String"; } } @@ -166,7 +171,7 @@ { datum _sortIndex { - value = "5"; + value = "8"; type = "int"; } } @@ -179,23 +184,44 @@ } datum baseAddress { - value = "65600"; + value = "12288"; type = "String"; } } + element mm_bridge_0 + { + datum _sortIndex + { + value = "4"; + type = "int"; + } + } + element mm_bridge_0.s0 + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + } element onchip_memory2_0 { datum _sortIndex { - value = "6"; + value = "11"; type = "int"; } } element onchip_memory2_0.s1 { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } datum baseAddress { - value = "0"; + value = "65536"; type = "String"; } } @@ -339,7 +365,7 @@ { datum _sortIndex { - value = "2"; + value = "6"; type = "int"; } } @@ -352,7 +378,7 @@ } datum baseAddress { - value = "65536"; + value = "4096"; type = "String"; } } @@ -1057,6 +1083,26 @@ + + + + + + + + + + + + + + + + + start="hps_0.h2f_lw_axi_master" + end="mm_bridge_0.s0"> @@ -1106,52 +1152,57 @@ - + - + - + - + + + + + + + start="mm_bridge_0.m0" + end="onchip_memory2_0.s1"> - + @@ -1163,7 +1214,7 @@ start="fpga_only_master.master" end="jtag_uart.avalon_jtag_slave"> - + - + - + - + - + - + - + + - + - + - + - + + + + + + + + hm_chipsel, -- .hm2_chipsel mk_io_hm2_int_in => irq, -- .hm2_int_in clk_100mhz_out_clk => hm_clk_med, -- clk_100mhz_out.clk - clk_200mhz_out_clk => hm_clk_high, -- clk_100mhz_out.clk - adc_io_convst => ADC_CONVST, -- adc.CONVST - adc_io_sck => ADC_SCK, -- .SCK - adc_io_sdi => ADC_SDI, -- .SDI - adc_io_sdo => ADC_SDO -- .SDO --- axi_str_data => out_data[7:0], -- stream_port.data --- axi_str_valid => out_data[8], -- .valid --- axi_str_ready => ar_in_sig[1]) -- .ready + clk_200mhz_out_clk => hm_clk_high -- clk_100mhz_out.clk ); -- Debounce logic to clean out glitches within 1ms diff --git a/HW/QuartusProjects/DE0_Nano_SoC_DB25/soc_system.qsys b/HW/QuartusProjects/DE0_Nano_SoC_DB25/soc_system.qsys index 6d33c8aa..cd3dd2d3 100644 --- a/HW/QuartusProjects/DE0_Nano_SoC_DB25/soc_system.qsys +++ b/HW/QuartusProjects/DE0_Nano_SoC_DB25/soc_system.qsys @@ -9,27 +9,11 @@ categories="System" /> - + DE0_Nano_SoC_DB25.qpf - - @@ -502,7 +510,6 @@ - @@ -1087,6 +1094,26 @@ + + + + + + + + + + + + + + + + + start="hps_0.h2f_lw_axi_master" + end="mm_bridge_0.s0"> @@ -1136,64 +1163,60 @@ - + - + - + - + - + - + + start="mm_bridge_0.m0" + end="onchip_memory2_0.s1"> - + + start="mm_bridge_0.m0" + end="hm2reg_io_0.slave"> - + - + - + - + - + - + - + - + - - - - - + - - - + - + - + - + + end="mm_bridge_0.reset" /> + end="onchip_memory2_0.reset1" /> + end="intr_capturer_0.reset_sink" /> + + + + + end="mm_bridge_0.reset" /> + end="mm_bridge_0.reset" /> + end="onchip_memory2_0.reset1" /> + end="onchip_memory2_0.reset1" /> + end="intr_capturer_0.reset_sink" /> + end="intr_capturer_0.reset_sink" /> diff --git a/HW/QuartusProjects/DE0_Nano_SoC_DB25/soc_system_pkg.vhd b/HW/QuartusProjects/DE0_Nano_SoC_DB25/soc_system_pkg.vhd index 0ef76786..17d52d8e 100755 --- a/HW/QuartusProjects/DE0_Nano_SoC_DB25/soc_system_pkg.vhd +++ b/HW/QuartusProjects/DE0_Nano_SoC_DB25/soc_system_pkg.vhd @@ -5,10 +5,6 @@ package soc_pkg is -- From: soc_system/soc_system.cmp component soc_system is port ( - adc_io_convst : out std_logic; -- convst - adc_io_sck : out std_logic; -- sck - adc_io_sdi : out std_logic; -- sdi - adc_io_sdo : in std_logic := 'X'; -- sdo button_pio_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export clk_clk : in std_logic := 'X'; -- clk clk_100mhz_out_clk : out std_logic; -- clk diff --git a/HW/QuartusProjects/DE10_Nano_FB_Cramps/DE10_Nano_FB_Cramps.sv b/HW/QuartusProjects/DE10_Nano_FB_Cramps/DE10_Nano_FB_Cramps.sv index 44bc0c30..0cd8fa48 100644 --- a/HW/QuartusProjects/DE10_Nano_FB_Cramps/DE10_Nano_FB_Cramps.sv +++ b/HW/QuartusProjects/DE10_Nano_FB_Cramps/DE10_Nano_FB_Cramps.sv @@ -119,7 +119,7 @@ parameter NumIOAddrReg = 6; wire hps_debug_reset; // wire [27:0] stm_hw_events; wire fpga_clk_50; - wire clk_75; + wire lcd_clk; // connection of internal logics // assign LED[5:1] = fpga_led_internal | {7'b0000000, led_level}; @@ -166,13 +166,13 @@ I2C_HDMI_Config u_I2C_HDMI_Config ( .HDMI_TX_INT(HDMI_TX_INT) ); - assign HDMI_TX_CLK = clk_75; + assign HDMI_TX_CLK = lcd_clk; soc_system u0 ( //Clock&Reset .clk_clk (FPGA_CLK1_50 ), // clk.clk .reset_reset_n (hps_fpga_reset_n ), // reset.reset_n - .alt_vip_itc_0_clocked_video_vid_clk (clk_75 ), // alt_vip_itc_0_clocked_video.vid_clk + .alt_vip_itc_0_clocked_video_vid_clk (lcd_clk ), // alt_vip_itc_0_clocked_video.vid_clk .alt_vip_itc_0_clocked_video_vid_data (HDMI_TX_D ), // .vid_data .alt_vip_itc_0_clocked_video_underflow ( ), // .underflow .alt_vip_itc_0_clocked_video_vid_datavalid (HDMI_TX_DE), // .vid_datavalid @@ -181,7 +181,7 @@ soc_system u0 ( .alt_vip_itc_0_clocked_video_vid_f ( ), // .vid_f .alt_vip_itc_0_clocked_video_vid_h ( ), // .vid_h .alt_vip_itc_0_clocked_video_vid_v ( ), // .vid_v - .lcd_clk_clk (clk_75), // lcd_clk.clk + .lcd_clk_clk (lcd_clk), // lcd_clk.clk .pll_stream_locked_export (), // pll_stream_locked.export //HPS ddr3 .memory_mem_a ( HPS_DDR3_ADDR), // memory.mem_a diff --git a/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system.qsys b/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system.qsys index e1af332e..c97750f0 100644 --- a/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system.qsys +++ b/HW/QuartusProjects/DE10_Nano_FB_Cramps/soc_system.qsys @@ -13,7 +13,7 @@ { datum _sortIndex { - value = "10"; + value = "12"; type = "int"; } } @@ -21,12 +21,12 @@ { datum _lockedAddress { - value = "0"; + value = "1"; type = "boolean"; } datum baseAddress { - value = "327680"; + value = "196608"; type = "String"; } } @@ -34,7 +34,7 @@ { datum _sortIndex { - value = "12"; + value = "14"; type = "int"; } } @@ -42,7 +42,7 @@ { datum _sortIndex { - value = "11"; + value = "13"; type = "int"; } } @@ -50,7 +50,7 @@ { datum _lockedAddress { - value = "0"; + value = "1"; type = "boolean"; } datum baseAddress @@ -63,7 +63,7 @@ { datum _sortIndex { - value = "7"; + value = "11"; type = "int"; } datum sopceditor_expanded @@ -102,7 +102,7 @@ { datum _sortIndex { - value = "8"; + value = "10"; type = "int"; } datum sopceditor_expanded @@ -136,7 +136,7 @@ { datum _sortIndex { - value = "5"; + value = "4"; type = "int"; } datum sopceditor_expanded @@ -155,6 +155,11 @@ } element hm2reg_io_0.slave { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } datum baseAddress { value = "262144"; @@ -165,7 +170,7 @@ { datum _sortIndex { - value = "1"; + value = "2"; type = "int"; } datum sopceditor_expanded @@ -207,15 +212,20 @@ { datum _sortIndex { - value = "14"; + value = "6"; type = "int"; } } element intr_capturer_0.avalon_slave_0 { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } datum baseAddress { - value = "196608"; + value = "28416"; type = "String"; } } @@ -223,7 +233,7 @@ { datum _sortIndex { - value = "2"; + value = "8"; type = "int"; } datum sopceditor_expanded @@ -275,7 +285,7 @@ { datum _sortIndex { - value = "6"; + value = "5"; type = "int"; } } @@ -287,11 +297,11 @@ type = "boolean"; } } - element pll_stream + element pll_lcd { datum _sortIndex { - value = "13"; + value = "1"; type = "int"; } } @@ -339,7 +349,7 @@ { datum _sortIndex { - value = "4"; + value = "7"; type = "int"; } datum sopceditor_expanded @@ -423,7 +433,7 @@ type="reset" dir="start" /> - + @@ -444,7 +454,7 @@ enabled="1"> - + @@ -483,8 +493,8 @@ - - + + @@ -644,7 +654,7 @@ - + @@ -1152,7 +1162,7 @@ - + @@ -1271,8 +1281,8 @@ - - + + @@ -1396,7 +1406,7 @@ start="mm_bridge_0.m0" end="ILC.avalon_slave"> - + - + - + - + - + - + - + - + - + + end="button_pio.irq"> - + end="dipsw_pio.irq"> + - + - + - + - + + + + + end="pll_lcd.reset" /> + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/DE10_Nano_SoC_FB_DB25.vhd b/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/DE10_Nano_SoC_FB_DB25.vhd index 0eef6e68..59ec800f 100755 --- a/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/DE10_Nano_SoC_FB_DB25.vhd +++ b/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/DE10_Nano_SoC_FB_DB25.vhd @@ -52,7 +52,7 @@ entity DE10_Nano_SoC_FB_DB25 is HDMI_TX_HS : out std_logic; HDMI_TX_INT : in std_logic; HDMI_TX_VS : out std_logic; - + --------- ADC --------- ADC_CONVST : out std_logic; ADC_SCK : out std_logic; @@ -291,13 +291,6 @@ begin mk_io_hm2_int_in => irq, -- .hm2_int_in clk_100mhz_out_clk => hm_clk_med, -- clk_100mhz_out.clk clk_200mhz_out_clk => hm_clk_high, -- clk_100mhz_out.clk - adc_io_convst => ADC_CONVST, -- adc.CONVST - adc_io_sck => ADC_SCK, -- .SCK - adc_io_sdi => ADC_SDI, -- .SDI - adc_io_sdo => ADC_SDO, -- .SDO --- axi_str_data => out_data[7:0], -- stream_port.data --- axi_str_valid => out_data[8], -- .valid --- axi_str_ready => ar_in_sig[1]) -- .ready alt_vip_itc_0_clocked_video_vid_clk => lcd_clk, -- alt_vip_itc_0_clocked_video.vid_clk alt_vip_itc_0_clocked_video_vid_data (23 downto 0) => HDMI_TX_D, -- .vid_data -- alt_vip_itc_0_clocked_video_underflow => CONNECTED_TO_alt_vip_itc_0_clocked_video_underflow, -- .underflow @@ -386,12 +379,12 @@ begin I2C_HDMI_Config_inst : I2C_HDMI_Config port map ( - iCLK => fpga_clk_50, + iCLK => fpga_clk_50, iRST_N => '1', I2C_SCLK => HDMI_I2C_SCL, I2C_SDAT => HDMI_I2C_SDA, HDMI_TX_INT => HDMI_TX_INT --- READY => +-- READY => ); diff --git a/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/README.md b/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/README.md new file mode 100644 index 00000000..903f8c45 --- /dev/null +++ b/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/README.md @@ -0,0 +1,8 @@ +This project is a clone of the DE0_Nano_SoC_DB25 project only with an added framebuffer driving the HDMI output. + +The current screen resolution is: 1024x768x8bpp @60Hz. + + +The frame reader runs on a separate bus (f2h_sdram) as bus master, making it noticably faster than a cpu alone fb. + +This project uses the hm2 config files from the DE0_Nano_SoC_DB25 project folder, so it will run with the same hm2 soc configs. diff --git a/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/soc_system.qsys b/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/soc_system.qsys index b3ceb120..07f259fc 100644 --- a/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/soc_system.qsys +++ b/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/soc_system.qsys @@ -9,27 +9,11 @@ categories="System" /> - - @@ -469,8 +463,8 @@ - - + + @@ -639,7 +633,7 @@ - + @@ -1473,15 +1467,6 @@ - - - - - - + - - - - - - + end="clock_bridge_0.in_clk" /> + start="pll_lcd.outclk0" + end="alt_vip_vfr_hdmi.clock_master" /> + start="pll_lcd.outclk0" + end="alt_vip_vfr_hdmi.clock_reset" /> + start="pll_lcd.outclk0" + end="hps_0.f2h_sdram0_clock" /> - + end="dipsw_pio.irq"> + end="button_pio.irq"> + end="dipsw_pio.irq"> + end="button_pio.irq"> + end="intr_capturer_0.reset_sink" /> + start="fpga_only_master.master_reset" + end="fpga_only_master.clk_reset" /> + + + + + + + + + + end="button_pio.reset" /> + + end="dipsw_pio.reset" /> + + + + + + + + + + + + + + + diff --git a/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/soc_system_pkg.vhd b/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/soc_system_pkg.vhd index b3b61b0d..1fbd7b14 100755 --- a/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/soc_system_pkg.vhd +++ b/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/soc_system_pkg.vhd @@ -5,10 +5,6 @@ package soc_pkg is -- From: soc_system/soc_system.cmp component soc_system is port ( - adc_io_convst : out std_logic; -- convst - adc_io_sck : out std_logic; -- sck - adc_io_sdi : out std_logic; -- sdi - adc_io_sdo : in std_logic := 'X'; -- sdo alt_vip_itc_0_clocked_video_vid_clk : in std_logic := 'X'; -- vid_clk alt_vip_itc_0_clocked_video_vid_data : out std_logic_vector(31 downto 0); -- vid_data alt_vip_itc_0_clocked_video_underflow : out std_logic; -- underflow