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Separate repositories for HDL code

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commit 0d7e78aaf3c9248ff6e5241bef5e1a2e5079940f 1 parent 17a62d9
@makestuff authored
Showing with 113 additions and 9,754 deletions.
  1. +7 −6 Makefile
  2. +7 −10 hdl/README
  3. +0 −69 hdl/build.sh
  4. +0 −40 hdl/common/altera.mk
  5. +0 −73 hdl/common/top.mk
  6. +0 −4 hdl/common/verilog/fifo_gen/README
  7. +0 −24 hdl/common/verilog/fifo_gen/altera.mk
  8. +0 −214 hdl/common/verilog/fifo_gen/atlys/fifo_gen.batch
  9. +0 −7 hdl/common/verilog/fifo_gen/ep2c5/fifo_gen.batch
  10. +0 −56 hdl/common/verilog/fifo_gen/fifo_wrapper_altera.v
  11. +0 −56 hdl/common/verilog/fifo_gen/fifo_wrapper_xilinx.v
  12. +0 −214 hdl/common/verilog/fifo_gen/lx9/fifo_gen.batch
  13. +0 −214 hdl/common/verilog/fifo_gen/nexys2-1200/fifo_gen.batch
  14. +0 −214 hdl/common/verilog/fifo_gen/nexys2-500/fifo_gen.batch
  15. +0 −214 hdl/common/verilog/fifo_gen/nexys3/fifo_gen.batch
  16. +0 −214 hdl/common/verilog/fifo_gen/s3board/fifo_gen.batch
  17. +0 −27 hdl/common/verilog/fifo_gen/xilinx.mk
  18. +0 −214 hdl/common/verilog/fifo_gen/xylo-l/fifo_gen.batch
  19. +0 −46 hdl/common/verilog/seven_seg/Makefile
  20. +0 −5 hdl/common/verilog/seven_seg/README
  21. +0 −90 hdl/common/verilog/seven_seg/seven_seg.v
  22. +0 −46 hdl/common/verilog/timer/Makefile
  23. +0 −16 hdl/common/verilog/timer/README
  24. +0 −58 hdl/common/verilog/timer/timer.v
  25. +0 −4 hdl/common/vhdl/fifo_gen/README
  26. +0 −27 hdl/common/vhdl/fifo_gen/altera.mk
  27. +0 −214 hdl/common/vhdl/fifo_gen/atlys/fifo_gen.batch
  28. +0 −7 hdl/common/vhdl/fifo_gen/ep2c5/fifo_gen.batch
  29. +0 −65 hdl/common/vhdl/fifo_gen/fifo_wrapper_altera.vhdl
  30. +0 −65 hdl/common/vhdl/fifo_gen/fifo_wrapper_xilinx.vhdl
  31. +0 −214 hdl/common/vhdl/fifo_gen/lx9/fifo_gen.batch
  32. +0 −214 hdl/common/vhdl/fifo_gen/nexys2-1200/fifo_gen.batch
  33. +0 −214 hdl/common/vhdl/fifo_gen/nexys2-500/fifo_gen.batch
  34. +0 −214 hdl/common/vhdl/fifo_gen/nexys3/fifo_gen.batch
  35. +0 −214 hdl/common/vhdl/fifo_gen/s3board/fifo_gen.batch
  36. +0 −30 hdl/common/vhdl/fifo_gen/xilinx.mk
  37. +0 −214 hdl/common/vhdl/fifo_gen/xylo-l/fifo_gen.batch
  38. +0 −76 hdl/common/vhdl/seven_seg/Makefile
  39. +0 −5 hdl/common/vhdl/seven_seg/README
  40. +0 −101 hdl/common/vhdl/seven_seg/seven_seg.vhdl
  41. +0 −84 hdl/common/vhdl/seven_seg/seven_seg_tb.vhdl
  42. +0 −70 hdl/common/vhdl/timer/Makefile
  43. +0 −16 hdl/common/vhdl/timer/README
  44. +0 −69 hdl/common/vhdl/timer/timer.vhdl
  45. +0 −87 hdl/common/vhdl/timer/timer_tb.vhdl
  46. +0 −50 hdl/common/xilinx.mk
  47. +0 −25 hdl/epp/README
  48. +0 −74 hdl/epp/platforms/ep2c5/platform.qsf
  49. +0 −1  hdl/epp/platforms/ep2c5/platform.sdc
  50. +0 −77 hdl/epp/platforms/nexys2-1200/platform-fx2.ucf
  51. +0 −6 hdl/epp/platforms/nexys2-1200/platform.batch
  52. +0 −77 hdl/epp/platforms/nexys2-1200/platform.ucf
  53. +0 −22 hdl/epp/platforms/nexys2-1200/platform.ut
  54. +0 −56 hdl/epp/platforms/nexys2-1200/platform.xst
  55. +0 −28 hdl/epp/platforms/pcs/platform.qsf
  56. +0 −1  hdl/epp/platforms/pcs/platform.sdc
  57. +0 −46 hdl/epp/verilog/comm_fpga/Makefile
  58. +0 −19 hdl/epp/verilog/comm_fpga/README
  59. +0 −165 hdl/epp/verilog/comm_fpga/comm_fpga_epp.v
  60. +0 −27 hdl/epp/verilog/ex_cksum/Makefile
  61. +0 −38 hdl/epp/verilog/ex_cksum/README
  62. +0 −125 hdl/epp/verilog/ex_cksum/top_level.v
  63. +0 −29 hdl/epp/verilog/ex_fifo/Makefile
  64. +0 −98 hdl/epp/verilog/ex_fifo/README
  65. +0 −183 hdl/epp/verilog/ex_fifo/top_level.v
  66. +0 −25 hdl/epp/vhdl/blinky/Makefile
  67. +0 −3  hdl/epp/vhdl/blinky/README
  68. +0 −51 hdl/epp/vhdl/blinky/top_level.vhdl
  69. +0 −84 hdl/epp/vhdl/comm_fpga/Makefile
  70. +0 −19 hdl/epp/vhdl/comm_fpga/README
  71. +0 −160 hdl/epp/vhdl/comm_fpga/comm_fpga_epp.vhdl
  72. +0 −245 hdl/epp/vhdl/comm_fpga/comm_fpga_epp_tb.vhdl
  73. +0 −27 hdl/epp/vhdl/ex_cksum/Makefile
  74. +0 −38 hdl/epp/vhdl/ex_cksum/README
  75. +0 −131 hdl/epp/vhdl/ex_cksum/top_level.vhdl
  76. +0 −29 hdl/epp/vhdl/ex_fifo/Makefile
  77. +0 −98 hdl/epp/vhdl/ex_fifo/README
  78. +0 −209 hdl/epp/vhdl/ex_fifo/top_level.vhdl
  79. +0 −25 hdl/fx2/README
  80. +0 −5 hdl/fx2/platforms/atlys/platform.batch
  81. +0 −82 hdl/fx2/platforms/atlys/platform.ucf
  82. +0 −21 hdl/fx2/platforms/atlys/platform.ut
  83. +0 −53 hdl/fx2/platforms/atlys/platform.xst
  84. +0 −6 hdl/fx2/platforms/lx9/platform.batch
  85. +0 −81 hdl/fx2/platforms/lx9/platform.ucf
  86. +0 −21 hdl/fx2/platforms/lx9/platform.ut
  87. +0 −53 hdl/fx2/platforms/lx9/platform.xst
  88. +0 −6 hdl/fx2/platforms/nexys2-1200/platform.batch
  89. +0 −82 hdl/fx2/platforms/nexys2-1200/platform.ucf
  90. +0 −22 hdl/fx2/platforms/nexys2-1200/platform.ut
  91. +0 −56 hdl/fx2/platforms/nexys2-1200/platform.xst
  92. +0 −6 hdl/fx2/platforms/nexys2-500/platform.batch
  93. +0 −82 hdl/fx2/platforms/nexys2-500/platform.ucf
  94. +0 −22 hdl/fx2/platforms/nexys2-500/platform.ut
  95. +0 −56 hdl/fx2/platforms/nexys2-500/platform.xst
  96. +0 −5 hdl/fx2/platforms/nexys3/platform.batch
  97. +0 −81 hdl/fx2/platforms/nexys3/platform.ucf
  98. +0 −21 hdl/fx2/platforms/nexys3/platform.ut
  99. +0 −53 hdl/fx2/platforms/nexys3/platform.xst
  100. +0 −6 hdl/fx2/platforms/s3board/platform.batch
  101. +0 −81 hdl/fx2/platforms/s3board/platform.ucf
  102. +0 −29 hdl/fx2/platforms/s3board/platform.ut
  103. +0 −56 hdl/fx2/platforms/s3board/platform.xst
  104. +0 −5 hdl/fx2/platforms/xylo-l/platform.batch
  105. +0 −82 hdl/fx2/platforms/xylo-l/platform.ucf
  106. +0 −22 hdl/fx2/platforms/xylo-l/platform.ut
  107. +0 −56 hdl/fx2/platforms/xylo-l/platform.xst
  108. +0 −46 hdl/fx2/verilog/comm_fpga/Makefile
  109. +0 −18 hdl/fx2/verilog/comm_fpga/README
  110. +0 −233 hdl/fx2/verilog/comm_fpga/comm_fpga_fx2.v
  111. +0 −27 hdl/fx2/verilog/ex_cksum/Makefile
  112. +0 −38 hdl/fx2/verilog/ex_cksum/README
  113. +0 −146 hdl/fx2/verilog/ex_cksum/top_level.v
  114. +0 −29 hdl/fx2/verilog/ex_fifo/Makefile
  115. +0 −98 hdl/fx2/verilog/ex_fifo/README
  116. +0 −202 hdl/fx2/verilog/ex_fifo/top_level.v
  117. +0 −90 hdl/fx2/vhdl/comm_fpga/Makefile
  118. +0 −18 hdl/fx2/vhdl/comm_fpga/README
  119. +0 −223 hdl/fx2/vhdl/comm_fpga/comm_fpga_fx2.vhdl
  120. +0 −197 hdl/fx2/vhdl/comm_fpga/comm_fpga_fx2_tb.vhdl
  121. +0 −4 hdl/fx2/vhdl/comm_fpga/fifoop.txt
  122. +0 −27 hdl/fx2/vhdl/ex_cksum/Makefile
  123. +0 −38 hdl/fx2/vhdl/ex_cksum/README
  124. +0 −148 hdl/fx2/vhdl/ex_cksum/top_level.vhdl
  125. +0 −29 hdl/fx2/vhdl/ex_fifo/Makefile
  126. +0 −98 hdl/fx2/vhdl/ex_fifo/README
  127. +0 −224 hdl/fx2/vhdl/ex_fifo/top_level.vhdl
  128. +0 −16 hdl/hdl.dot
  129. +66 −0 hdlbuild.sh
  130. +33 −28 tests-unit/testCsvf.cpp
View
13 Makefile
@@ -17,11 +17,11 @@
ROOT := $(realpath ../..)
DEPS := error usbwrap fx2loader nero buffer
TYPE := dll
-SUBDIRS := tests-unit
+#SUBDIRS := tests-unit
PRE_BUILD := $(ROOT)/3rd/fx2lib/lib/fx2.lib gen_fw
-POST_BUILD := tools gen_csvf
+POST_BUILD := tools
EXTRA_CC_SRCS := gen_fw/ramFirmware.c gen_fw/eepromWithBootFirmware.c gen_fw/eepromNoBootFirmware.c
-EXTRA_CLEAN := gen_svf gen_xsvf gen_csvf gen_fw
+EXTRA_CLEAN := gen_fw #gen_svf gen_xsvf gen_csvf
EXTRA_CLEAN_DIRS := mkfw firmware/fx2 xsvf2csvf dump
-include $(ROOT)/common/top.mk
@@ -61,11 +61,12 @@ gen_fw: $(MKFW)
$(MKFW) gen_fw/eepromWithBootFirmware1.hex gen_fw/eepromWithBootFirmware2.hex eepromWithBoot iic > gen_fw/eepromWithBootFirmware.c
$(MKFW) gen_fw/eepromNoBootFirmware1.hex gen_fw/eepromNoBootFirmware2.hex eepromNoBoot iic > gen_fw/eepromNoBootFirmware.c
-gen_csvf:
- cd hdl && ./build.sh $(X2C)
+hdl:
+ ./hdlbuild.sh $(X2C)
$(ROOT)/3rd/fx2lib/lib/fx2.lib: $(ROOT)/3rd/fx2lib
make -C $<
tests: FORCE
- make -C tests rel
+ make -C tests-unit rel
+ make -C tests-integration rel
View
17 hdl/README
@@ -1,11 +1,8 @@
------------------ COMMFPGA HARDWARE DESCRIPTION LANGUAGE CODE ------------------
+---------------- BUILD AND TEST HDL APPLICATIONS AND LIBRARIES -----------------
-In this directory you will find Hardware Description Language code which
-implements the FPGA side of the CommFPGA protocol used by FPGALink devices. The
-design is modular, vendor-neutral and implementations are provided in both VHDL
-and Verilog.
-
-Subdirectories:
- common - Makefiles needed to build the HDL code for Xilinx or Altera tools.
- fx2 - A CommFPGA implementation using Cypress FX2LP synchronous slave FIFOs.
- epp - A CommFPGA implementation using the asynchronous EPP protocol.
+The hdlmake.py script automates the process of HDL validation, simulation and
+synthesis. It works by reading simple YAML config files from your working dirs
+and generating from them the files necessary to correctly invoke the
+simulation and synthesis tools. It supports synthesis tools from Altera and
+Xilinx, and simulation with GHDL and GTKWave. Support for Icarus Verilog and
+ModelSim is planned.
View
69 hdl/build.sh
@@ -1,69 +0,0 @@
-#!/bin/bash
-
-if [ $# != 1 ]; then
- echo "Synopsis: $0 <xsvf2csvf path>"
- exit 1
-fi
-
-export HDL=$(pwd)
-export X2C=${HDL}/../$1
-
-echo HDL build starting at $(date)...
-
-rm -rf ../gen_svf ../gen_xsvf ../gen_csvf
-mkdir ../gen_svf ../gen_xsvf ../gen_csvf
-for p in atlys lx9 nexys2-1200 nexys2-500 nexys3 s3board xylo-l; do
- echo Building for FX2 platform: ${p}...
- for l in vhdl verilog; do
- # cksum example
- cd ${HDL}/fx2/${l}/ex_cksum
- make clean
- make PLATFORM=${p}
- cp top_level.svf ${HDL}/../gen_svf/ex_cksum_${p}_fx2_${l}.svf
- if [ -e top_level.xsvf ]; then
- cp top_level.xsvf ${HDL}/../gen_xsvf/ex_cksum_${p}_fx2_${l}.xsvf
- fi
- ${X2C} ${HDL}/../gen_svf/ex_cksum_${p}_fx2_${l}.svf ${HDL}/../gen_csvf/ex_cksum_${p}_fx2_${l}.csvf
- make clean
-
- # fifo example
- cd ${HDL}/fx2/${l}/ex_fifo
- make clean fifoclean
- make PLATFORM=${p}
- cp top_level.svf ${HDL}/../gen_svf/ex_fifo_${p}_fx2_${l}.svf
- if [ -e top_level.xsvf ]; then
- cp top_level.xsvf ${HDL}/../gen_xsvf/ex_fifo_${p}_fx2_${l}.xsvf
- fi
- ${X2C} ${HDL}/../gen_svf/ex_fifo_${p}_fx2_${l}.svf ${HDL}/../gen_csvf/ex_fifo_${p}_fx2_${l}.csvf
- make clean fifoclean
- done
-done
-
-for p in nexys2-1200 ep2c5; do
- echo Building for EPP platform: ${p}...
- for l in vhdl verilog; do
- # cksum example
- cd ${HDL}/epp/${l}/ex_cksum
- make clean
- make PLATFORM=${p}
- cp top_level.svf ${HDL}/../gen_svf/ex_cksum_${p}_epp_${l}.svf
- if [ -e top_level.xsvf ]; then
- cp top_level.xsvf ${HDL}/../gen_xsvf/ex_cksum_${p}_epp_${l}.xsvf
- fi
- ${X2C} ${HDL}/../gen_svf/ex_cksum_${p}_epp_${l}.svf ${HDL}/../gen_csvf/ex_cksum_${p}_epp_${l}.csvf
- make clean
-
- # fifo example
- cd ${HDL}/epp/${l}/ex_fifo
- make clean fifoclean
- make PLATFORM=${p}
- cp top_level.svf ${HDL}/../gen_svf/ex_fifo_${p}_epp_${l}.svf
- if [ -e top_level.xsvf ]; then
- cp top_level.xsvf ${HDL}/../gen_xsvf/ex_fifo_${p}_epp_${l}.xsvf
- fi
- ${X2C} ${HDL}/../gen_svf/ex_fifo_${p}_epp_${l}.svf ${HDL}/../gen_csvf/ex_fifo_${p}_epp_${l}.csvf
- make clean fifoclean
- done
-done
-
-echo HDL build finished at $(date)
View
40 hdl/common/altera.mk
@@ -1,40 +0,0 @@
-#
-# Copyright (C) 2009-2012 Chris McClelland
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU Lesser General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU Lesser General Public License for more details.
-#
-# You should have received a copy of the GNU Lesser General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-ifeq ($(HDL),vhdl)
- HDL_EXT := vhdl
-else ifeq ($(HDL),verilog)
- HDL_EXT := v
-endif
-
-$(TOP_LEVEL).qsf: ../../platforms/$(PLATFORM)/platform.qsf $(HDLS)
- cp $< $@
- for i in $+; do if [ "$${i##*.}" = "vhdl" ]; then echo "set_global_assignment -name VHDL_FILE $$i"; elif [ "$${i##*.}" = "v" ]; then echo "set_global_assignment -name VERILOG_FILE $$i"; fi; done >> $@
-
-$(TOP_LEVEL).svf: $(TOP_LEVEL).qsf $(TOP_LEVEL).fit.rpt
- quartus_asm --read_settings_files=on --write_settings_files=off $(TOP_LEVEL) -c $(TOP_LEVEL)
-
-$(TOP_LEVEL).fit.rpt: $(TOP_LEVEL).map.rpt
- quartus_fit --parallel=1 --read_settings_files=on --write_settings_files=off $(TOP_LEVEL) -c $(TOP_LEVEL)
-
-$(TOP_LEVEL).sdc: ../../platforms/$(PLATFORM)/platform.sdc
- cp $< $@
-
-$(TOP_LEVEL).map.rpt: $(TOP_LEVEL).$(HDL_EXT) $(TOP_LEVEL).sdc
- echo '{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 1 0 "" 0 -1}' > $(TOP_LEVEL).srf
- quartus_map --parallel=1 --read_settings_files=on --write_settings_files=off $(TOP_LEVEL) -c $(TOP_LEVEL)
-
-FORCE:
View
73 hdl/common/top.mk
@@ -1,73 +0,0 @@
-#
-# Copyright (C) 2009-2012 Chris McClelland
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU Lesser General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU Lesser General Public License for more details.
-#
-# You should have received a copy of the GNU Lesser General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-X2C := xsvf2csvf
-
-all: $(EXTRAS) $(TOP_LEVEL).svf
-
-csvf: $(TOP_LEVEL).svf
- $(X2C) $(TOP_LEVEL).svf $(TOP_LEVEL).csvf
-
-THISDIR := $(dir $(lastword $(MAKEFILE_LIST)))
-ifeq ($(PLATFORM),s3board)
- VENDOR := xilinx
- FPGA := xc3s200-ft256-4
- MAPFLAGS := -cm area
- PARFLAGS := -t 1
-else ifeq ($(PLATFORM),nexys2-500)
- VENDOR := xilinx
- FPGA := xc3s500e-fg320-4
- MAPFLAGS := -cm area
- PARFLAGS := -t 1
-else ifeq ($(PLATFORM),nexys2-1200)
- VENDOR := xilinx
- FPGA := xc3s1200e-fg320-4
- MAPFLAGS := -cm area
- PARFLAGS := -t 1
-else ifeq ($(PLATFORM),atlys)
- VENDOR := xilinx
- FPGA := xc6slx45-csg324-3
- MAPFLAGS :=
- PARFLAGS :=
-else ifeq ($(PLATFORM),nexys3)
- VENDOR := xilinx
- FPGA := xc6slx16-csg324-3
- MAPFLAGS :=
- PARFLAGS :=
-else ifeq ($(PLATFORM),xylo-l)
- VENDOR := xilinx
- FPGA := xc3s500e-pq208-4
- MAPFLAGS := -cm area
- PARFLAGS := -t 1
-else ifeq ($(PLATFORM),lx9)
- VENDOR := xilinx
- FPGA := xc6slx9-tqg144-2
- MAPFLAGS :=
- PARFLAGS :=
-else ifeq ($(PLATFORM),ep2c5)
- VENDOR := altera
-else ifeq ($(PLATFORM),pcs)
- VENDOR := altera
-endif
-
-clean: FORCE
- rm -rf \
- *.qsf *.svf db incremental_db *.rpt *.summary *.pin *.qpf *.dpf *.smsg *.jdi *.pof *.sof *.done *.bak *.sdc *.srf \
- *.edif *.xsvf *.csvf _ngo *.bgn *.drc *.ncd *.ntrc_log *.prj *.twr *.csv *.html fx2fpga_xdb _xmsgs *.bit *.gise \
- *.ngc *.pad *.ptwx *.twx *.ngm *.txt *.xml *.xrpt *.bld *.ise *.ngd *.par *.stx *.map *.twr auto_project_xdb *.cmd_log \
- *.lso *.ngr *.pcf *.syr *.unroutes *.xpi *.mrp xst *.log *.cmd *.xwbt iseconfig xlnx_auto_0_xdb
-
-FORCE:
View
4 hdl/common/verilog/fifo_gen/README
@@ -1,4 +0,0 @@
-------------------------- VERILOG COREGEN FIFO MODULE --------------------------
-
-A COREgen project which generates a FIFO for use by the ex_fifo examples. There
-is also a wrapper which follows the more usual {data,valid,ready} convention.
View
24 hdl/common/verilog/fifo_gen/altera.mk
@@ -1,24 +0,0 @@
-#
-# Copyright (C) 2009-2012 Chris McClelland
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU Lesser General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU Lesser General Public License for more details.
-#
-# You should have received a copy of the GNU Lesser General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-EXTRAS := $(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo.v
-HDLS += $(COMMON)/$(HDL)/fifo_gen/fifo_wrapper_altera.v $(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo.v
-
-$(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo.v $(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo.ngc: $(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo_gen.batch
- cd $(COMMON)/$(HDL)/fifo_gen/$(PLATFORM) && qmegawiz -silent module=scfifo -f:fifo_gen.batch fifo.v
-
-fifoclean: FORCE
- cd $(COMMON)/$(HDL)/fifo_gen && for i in $$(find . -maxdepth 1 -mindepth 1 -type d); do mv $$i/fifo_gen.batch .; rm -rf $$i; mkdir $$i; mv fifo_gen.batch $$i; done
View
214 hdl/common/verilog/fifo_gen/atlys/fifo_gen.batch
@@ -1,214 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 13.1
-# Date: Thu May 3 23:21:50 2012
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-NEWPROJECT .
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc6slx45
-SET devicefamily = spartan6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = csg324
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.1
-# END Select
-# BEGIN Parameters
-CSET add_ngc_constraint_axi=false
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET aruser_width=1
-CSET awuser_width=1
-CSET axi_address_width=32
-CSET axi_data_width=64
-CSET axi_type=AXI4_Stream
-CSET axis_type=FIFO
-CSET buser_width=1
-CSET clock_enable_type=Slave_Interface_Clock_Enable
-CSET clock_type_axi=Common_Clock
-CSET component_name=fifo
-CSET data_count=true
-CSET data_count_width=8
-CSET disable_timing_violations=false
-CSET disable_timing_violations_axi=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_assert_value_axis=1022
-CSET empty_threshold_assert_value_rach=1022
-CSET empty_threshold_assert_value_rdch=1022
-CSET empty_threshold_assert_value_wach=1022
-CSET empty_threshold_assert_value_wdch=1022
-CSET empty_threshold_assert_value_wrch=1022
-CSET empty_threshold_negate_value=5
-CSET enable_aruser=false
-CSET enable_awuser=false
-CSET enable_buser=false
-CSET enable_common_overflow=false
-CSET enable_common_underflow=false
-CSET enable_data_counts_axis=false
-CSET enable_data_counts_rach=false
-CSET enable_data_counts_rdch=false
-CSET enable_data_counts_wach=false
-CSET enable_data_counts_wdch=false
-CSET enable_data_counts_wrch=false
-CSET enable_ecc=false
-CSET enable_ecc_axis=false
-CSET enable_ecc_rach=false
-CSET enable_ecc_rdch=false
-CSET enable_ecc_wach=false
-CSET enable_ecc_wdch=false
-CSET enable_ecc_wrch=false
-CSET enable_handshake_flag_options_axis=false
-CSET enable_handshake_flag_options_rach=false
-CSET enable_handshake_flag_options_rdch=false
-CSET enable_handshake_flag_options_wach=false
-CSET enable_handshake_flag_options_wdch=false
-CSET enable_handshake_flag_options_wrch=false
-CSET enable_read_channel=false
-CSET enable_read_pointer_increment_by2=false
-CSET enable_reset_synchronization=true
-CSET enable_ruser=false
-CSET enable_tdata=false
-CSET enable_tdest=false
-CSET enable_tid=false
-CSET enable_tkeep=false
-CSET enable_tlast=false
-CSET enable_tready=true
-CSET enable_tstrobe=false
-CSET enable_tuser=false
-CSET enable_write_channel=false
-CSET enable_wuser=false
-CSET fifo_application_type_axis=Data_FIFO
-CSET fifo_application_type_rach=Data_FIFO
-CSET fifo_application_type_rdch=Data_FIFO
-CSET fifo_application_type_wach=Data_FIFO
-CSET fifo_application_type_wdch=Data_FIFO
-CSET fifo_application_type_wrch=Data_FIFO
-CSET fifo_implementation=Common_Clock_Block_RAM
-CSET fifo_implementation_axis=Common_Clock_Block_RAM
-CSET fifo_implementation_rach=Common_Clock_Block_RAM
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wach=Common_Clock_Block_RAM
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM
-CSET full_flags_reset_value=0
-CSET full_threshold_assert_value=127
-CSET full_threshold_assert_value_axis=1023
-CSET full_threshold_assert_value_rach=1023
-CSET full_threshold_assert_value_rdch=1023
-CSET full_threshold_assert_value_wach=1023
-CSET full_threshold_assert_value_wdch=1023
-CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=126
-CSET id_width=4
-CSET inject_dbit_error=false
-CSET inject_dbit_error_axis=false
-CSET inject_dbit_error_rach=false
-CSET inject_dbit_error_rdch=false
-CSET inject_dbit_error_wach=false
-CSET inject_dbit_error_wdch=false
-CSET inject_dbit_error_wrch=false
-CSET inject_sbit_error=false
-CSET inject_sbit_error_axis=false
-CSET inject_sbit_error_rach=false
-CSET inject_sbit_error_rdch=false
-CSET inject_sbit_error_wach=false
-CSET inject_sbit_error_wdch=false
-CSET inject_sbit_error_wrch=false
-CSET input_data_width=8
-CSET input_depth=128
-CSET input_depth_axis=1024
-CSET input_depth_rach=16
-CSET input_depth_rdch=1024
-CSET input_depth_wach=16
-CSET input_depth_wdch=1024
-CSET input_depth_wrch=16
-CSET interface_type=Native
-CSET output_data_width=8
-CSET output_depth=128
-CSET overflow_flag=false
-CSET overflow_flag_axi=false
-CSET overflow_sense=Active_High
-CSET overflow_sense_axi=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_axis=Empty
-CSET programmable_empty_type_rach=Empty
-CSET programmable_empty_type_rdch=Empty
-CSET programmable_empty_type_wach=Empty
-CSET programmable_empty_type_wdch=Empty
-CSET programmable_empty_type_wrch=Empty
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET programmable_full_type_axis=Full
-CSET programmable_full_type_rach=Full
-CSET programmable_full_type_rdch=Full
-CSET programmable_full_type_wach=Full
-CSET programmable_full_type_wdch=Full
-CSET programmable_full_type_wrch=Full
-CSET rach_type=FIFO
-CSET rdch_type=FIFO
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=8
-CSET register_slice_mode_axis=Fully_Registered
-CSET register_slice_mode_rach=Fully_Registered
-CSET register_slice_mode_rdch=Fully_Registered
-CSET register_slice_mode_wach=Fully_Registered
-CSET register_slice_mode_wdch=Fully_Registered
-CSET register_slice_mode_wrch=Fully_Registered
-CSET reset_pin=false
-CSET reset_type=Asynchronous_Reset
-CSET ruser_width=1
-CSET tdata_width=64
-CSET tdest_width=4
-CSET tid_width=8
-CSET tkeep_width=4
-CSET tstrb_width=4
-CSET tuser_width=4
-CSET underflow_flag=false
-CSET underflow_flag_axi=false
-CSET underflow_sense=Active_High
-CSET underflow_sense_axi=Active_High
-CSET use_clock_enable=false
-CSET use_dout_reset=false
-CSET use_embedded_registers=false
-CSET use_extra_logic=true
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET wach_type=FIFO
-CSET wdch_type=FIFO
-CSET wrch_type=FIFO
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=8
-CSET wuser_width=1
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2011-02-03T22:23:32.000Z
-# END Extra information
-GENERATE
-# CRC: c4027d18
View
7 hdl/common/verilog/fifo_gen/ep2c5/fifo_gen.batch
@@ -1,7 +0,0 @@
-INTENDED_DEVICE_FAMILY="Cyclone II"
-LPM_NUMWORDS=256
-LPM_SHOWAHEAD=ON
-LPM_WIDTHU=8
-Full=1
-Empty=1
-UsedW=1
View
56 hdl/common/verilog/fifo_gen/fifo_wrapper_altera.v
@@ -1,56 +0,0 @@
-//
-// Copyright (C) 2009-2012 Chris McClelland
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU Lesser General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU Lesser General Public License for more details.
-//
-// You should have received a copy of the GNU Lesser General Public License
-// along with this program. If not, see <http://www.gnu.org/licenses/>.
-//
-module
- fifo_wrapper(
- // Clock and depth
- input wire clk_in,
- output wire[7:0] depth_out,
-
- // Data is clocked into the FIFO on each clock edge where both valid & ready are high
- input wire[7:0] inputData_in,
- input wire inputValid_in,
- output wire inputReady_out,
-
- // Data is clocked out of the FIFO on each clock edge where both valid & ready are high
- output wire[7:0] outputData_out,
- output wire outputValid_out,
- input wire outputReady_in
- );
-
- wire inputFull;
- wire outputEmpty;
-
- // Invert "full/empty" signals to give "ready/valid" signals
- assign inputReady_out = ~inputFull;
- assign outputValid_out = ~outputEmpty;
-
- // The encapsulated FIFO
- fifo fifo(
- .clock(clk_in),
- .usedw(depth_out),
-
- // Production end
- .data(inputData_in),
- .wrreq(inputValid_in),
- .full(inputFull),
-
- // Consumption end
- .q(outputData_out),
- .empty(outputEmpty),
- .rdreq(outputReady_in)
- );
-endmodule
View
56 hdl/common/verilog/fifo_gen/fifo_wrapper_xilinx.v
@@ -1,56 +0,0 @@
-//
-// Copyright (C) 2009-2012 Chris McClelland
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU Lesser General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU Lesser General Public License for more details.
-//
-// You should have received a copy of the GNU Lesser General Public License
-// along with this program. If not, see <http://www.gnu.org/licenses/>.
-//
-module
- fifo_wrapper(
- // Clock and depth
- input wire clk_in,
- output wire[7:0] depth_out,
-
- // Data is clocked into the FIFO on each clock edge where both valid & ready are high
- input wire[7:0] inputData_in,
- input wire inputValid_in,
- output wire inputReady_out,
-
- // Data is clocked out of the FIFO on each clock edge where both valid & ready are high
- output wire[7:0] outputData_out,
- output wire outputValid_out,
- input wire outputReady_in
- );
-
- wire inputFull;
- wire outputEmpty;
-
- // Invert "full/empty" signals to give "ready/valid" signals
- assign inputReady_out = ~inputFull;
- assign outputValid_out = ~outputEmpty;
-
- // The encapsulated FIFO
- fifo fifo(
- .clk(clk_in),
- .data_count(depth_out),
-
- // Production end
- .din(inputData_in),
- .wr_en(inputValid_in),
- .full(inputFull),
-
- // Consumption end
- .dout(outputData_out),
- .empty(outputEmpty),
- .rd_en(outputReady_in)
- );
-endmodule
View
214 hdl/common/verilog/fifo_gen/lx9/fifo_gen.batch
@@ -1,214 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 13.1
-# Date: Thu May 3 23:21:50 2012
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-NEWPROJECT .
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc6slx9
-SET devicefamily = spartan6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = tqg144
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -2
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.1
-# END Select
-# BEGIN Parameters
-CSET add_ngc_constraint_axi=false
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET aruser_width=1
-CSET awuser_width=1
-CSET axi_address_width=32
-CSET axi_data_width=64
-CSET axi_type=AXI4_Stream
-CSET axis_type=FIFO
-CSET buser_width=1
-CSET clock_enable_type=Slave_Interface_Clock_Enable
-CSET clock_type_axi=Common_Clock
-CSET component_name=fifo
-CSET data_count=true
-CSET data_count_width=8
-CSET disable_timing_violations=false
-CSET disable_timing_violations_axi=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_assert_value_axis=1022
-CSET empty_threshold_assert_value_rach=1022
-CSET empty_threshold_assert_value_rdch=1022
-CSET empty_threshold_assert_value_wach=1022
-CSET empty_threshold_assert_value_wdch=1022
-CSET empty_threshold_assert_value_wrch=1022
-CSET empty_threshold_negate_value=5
-CSET enable_aruser=false
-CSET enable_awuser=false
-CSET enable_buser=false
-CSET enable_common_overflow=false
-CSET enable_common_underflow=false
-CSET enable_data_counts_axis=false
-CSET enable_data_counts_rach=false
-CSET enable_data_counts_rdch=false
-CSET enable_data_counts_wach=false
-CSET enable_data_counts_wdch=false
-CSET enable_data_counts_wrch=false
-CSET enable_ecc=false
-CSET enable_ecc_axis=false
-CSET enable_ecc_rach=false
-CSET enable_ecc_rdch=false
-CSET enable_ecc_wach=false
-CSET enable_ecc_wdch=false
-CSET enable_ecc_wrch=false
-CSET enable_handshake_flag_options_axis=false
-CSET enable_handshake_flag_options_rach=false
-CSET enable_handshake_flag_options_rdch=false
-CSET enable_handshake_flag_options_wach=false
-CSET enable_handshake_flag_options_wdch=false
-CSET enable_handshake_flag_options_wrch=false
-CSET enable_read_channel=false
-CSET enable_read_pointer_increment_by2=false
-CSET enable_reset_synchronization=true
-CSET enable_ruser=false
-CSET enable_tdata=false
-CSET enable_tdest=false
-CSET enable_tid=false
-CSET enable_tkeep=false
-CSET enable_tlast=false
-CSET enable_tready=true
-CSET enable_tstrobe=false
-CSET enable_tuser=false
-CSET enable_write_channel=false
-CSET enable_wuser=false
-CSET fifo_application_type_axis=Data_FIFO
-CSET fifo_application_type_rach=Data_FIFO
-CSET fifo_application_type_rdch=Data_FIFO
-CSET fifo_application_type_wach=Data_FIFO
-CSET fifo_application_type_wdch=Data_FIFO
-CSET fifo_application_type_wrch=Data_FIFO
-CSET fifo_implementation=Common_Clock_Block_RAM
-CSET fifo_implementation_axis=Common_Clock_Block_RAM
-CSET fifo_implementation_rach=Common_Clock_Block_RAM
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wach=Common_Clock_Block_RAM
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM
-CSET full_flags_reset_value=0
-CSET full_threshold_assert_value=127
-CSET full_threshold_assert_value_axis=1023
-CSET full_threshold_assert_value_rach=1023
-CSET full_threshold_assert_value_rdch=1023
-CSET full_threshold_assert_value_wach=1023
-CSET full_threshold_assert_value_wdch=1023
-CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=126
-CSET id_width=4
-CSET inject_dbit_error=false
-CSET inject_dbit_error_axis=false
-CSET inject_dbit_error_rach=false
-CSET inject_dbit_error_rdch=false
-CSET inject_dbit_error_wach=false
-CSET inject_dbit_error_wdch=false
-CSET inject_dbit_error_wrch=false
-CSET inject_sbit_error=false
-CSET inject_sbit_error_axis=false
-CSET inject_sbit_error_rach=false
-CSET inject_sbit_error_rdch=false
-CSET inject_sbit_error_wach=false
-CSET inject_sbit_error_wdch=false
-CSET inject_sbit_error_wrch=false
-CSET input_data_width=8
-CSET input_depth=128
-CSET input_depth_axis=1024
-CSET input_depth_rach=16
-CSET input_depth_rdch=1024
-CSET input_depth_wach=16
-CSET input_depth_wdch=1024
-CSET input_depth_wrch=16
-CSET interface_type=Native
-CSET output_data_width=8
-CSET output_depth=128
-CSET overflow_flag=false
-CSET overflow_flag_axi=false
-CSET overflow_sense=Active_High
-CSET overflow_sense_axi=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_axis=Empty
-CSET programmable_empty_type_rach=Empty
-CSET programmable_empty_type_rdch=Empty
-CSET programmable_empty_type_wach=Empty
-CSET programmable_empty_type_wdch=Empty
-CSET programmable_empty_type_wrch=Empty
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET programmable_full_type_axis=Full
-CSET programmable_full_type_rach=Full
-CSET programmable_full_type_rdch=Full
-CSET programmable_full_type_wach=Full
-CSET programmable_full_type_wdch=Full
-CSET programmable_full_type_wrch=Full
-CSET rach_type=FIFO
-CSET rdch_type=FIFO
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=8
-CSET register_slice_mode_axis=Fully_Registered
-CSET register_slice_mode_rach=Fully_Registered
-CSET register_slice_mode_rdch=Fully_Registered
-CSET register_slice_mode_wach=Fully_Registered
-CSET register_slice_mode_wdch=Fully_Registered
-CSET register_slice_mode_wrch=Fully_Registered
-CSET reset_pin=false
-CSET reset_type=Asynchronous_Reset
-CSET ruser_width=1
-CSET tdata_width=64
-CSET tdest_width=4
-CSET tid_width=8
-CSET tkeep_width=4
-CSET tstrb_width=4
-CSET tuser_width=4
-CSET underflow_flag=false
-CSET underflow_flag_axi=false
-CSET underflow_sense=Active_High
-CSET underflow_sense_axi=Active_High
-CSET use_clock_enable=false
-CSET use_dout_reset=false
-CSET use_embedded_registers=false
-CSET use_extra_logic=true
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET wach_type=FIFO
-CSET wdch_type=FIFO
-CSET wrch_type=FIFO
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=8
-CSET wuser_width=1
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2011-02-03T22:23:32.000Z
-# END Extra information
-GENERATE
-# CRC: c4027d18
View
214 hdl/common/verilog/fifo_gen/nexys2-1200/fifo_gen.batch
@@ -1,214 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 13.1
-# Date: Thu May 3 23:21:50 2012
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-NEWPROJECT .
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc3s1200e
-SET devicefamily = spartan3e
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = fg320
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -4
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.1
-# END Select
-# BEGIN Parameters
-CSET add_ngc_constraint_axi=false
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET aruser_width=1
-CSET awuser_width=1
-CSET axi_address_width=32
-CSET axi_data_width=64
-CSET axi_type=AXI4_Stream
-CSET axis_type=FIFO
-CSET buser_width=1
-CSET clock_enable_type=Slave_Interface_Clock_Enable
-CSET clock_type_axi=Common_Clock
-CSET component_name=fifo
-CSET data_count=true
-CSET data_count_width=8
-CSET disable_timing_violations=false
-CSET disable_timing_violations_axi=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_assert_value_axis=1022
-CSET empty_threshold_assert_value_rach=1022
-CSET empty_threshold_assert_value_rdch=1022
-CSET empty_threshold_assert_value_wach=1022
-CSET empty_threshold_assert_value_wdch=1022
-CSET empty_threshold_assert_value_wrch=1022
-CSET empty_threshold_negate_value=5
-CSET enable_aruser=false
-CSET enable_awuser=false
-CSET enable_buser=false
-CSET enable_common_overflow=false
-CSET enable_common_underflow=false
-CSET enable_data_counts_axis=false
-CSET enable_data_counts_rach=false
-CSET enable_data_counts_rdch=false
-CSET enable_data_counts_wach=false
-CSET enable_data_counts_wdch=false
-CSET enable_data_counts_wrch=false
-CSET enable_ecc=false
-CSET enable_ecc_axis=false
-CSET enable_ecc_rach=false
-CSET enable_ecc_rdch=false
-CSET enable_ecc_wach=false
-CSET enable_ecc_wdch=false
-CSET enable_ecc_wrch=false
-CSET enable_handshake_flag_options_axis=false
-CSET enable_handshake_flag_options_rach=false
-CSET enable_handshake_flag_options_rdch=false
-CSET enable_handshake_flag_options_wach=false
-CSET enable_handshake_flag_options_wdch=false
-CSET enable_handshake_flag_options_wrch=false
-CSET enable_read_channel=false
-CSET enable_read_pointer_increment_by2=false
-CSET enable_reset_synchronization=true
-CSET enable_ruser=false
-CSET enable_tdata=false
-CSET enable_tdest=false
-CSET enable_tid=false
-CSET enable_tkeep=false
-CSET enable_tlast=false
-CSET enable_tready=true
-CSET enable_tstrobe=false
-CSET enable_tuser=false
-CSET enable_write_channel=false
-CSET enable_wuser=false
-CSET fifo_application_type_axis=Data_FIFO
-CSET fifo_application_type_rach=Data_FIFO
-CSET fifo_application_type_rdch=Data_FIFO
-CSET fifo_application_type_wach=Data_FIFO
-CSET fifo_application_type_wdch=Data_FIFO
-CSET fifo_application_type_wrch=Data_FIFO
-CSET fifo_implementation=Common_Clock_Block_RAM
-CSET fifo_implementation_axis=Common_Clock_Block_RAM
-CSET fifo_implementation_rach=Common_Clock_Block_RAM
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wach=Common_Clock_Block_RAM
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM
-CSET full_flags_reset_value=0
-CSET full_threshold_assert_value=127
-CSET full_threshold_assert_value_axis=1023
-CSET full_threshold_assert_value_rach=1023
-CSET full_threshold_assert_value_rdch=1023
-CSET full_threshold_assert_value_wach=1023
-CSET full_threshold_assert_value_wdch=1023
-CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=126
-CSET id_width=4
-CSET inject_dbit_error=false
-CSET inject_dbit_error_axis=false
-CSET inject_dbit_error_rach=false
-CSET inject_dbit_error_rdch=false
-CSET inject_dbit_error_wach=false
-CSET inject_dbit_error_wdch=false
-CSET inject_dbit_error_wrch=false
-CSET inject_sbit_error=false
-CSET inject_sbit_error_axis=false
-CSET inject_sbit_error_rach=false
-CSET inject_sbit_error_rdch=false
-CSET inject_sbit_error_wach=false
-CSET inject_sbit_error_wdch=false
-CSET inject_sbit_error_wrch=false
-CSET input_data_width=8
-CSET input_depth=128
-CSET input_depth_axis=1024
-CSET input_depth_rach=16
-CSET input_depth_rdch=1024
-CSET input_depth_wach=16
-CSET input_depth_wdch=1024
-CSET input_depth_wrch=16
-CSET interface_type=Native
-CSET output_data_width=8
-CSET output_depth=128
-CSET overflow_flag=false
-CSET overflow_flag_axi=false
-CSET overflow_sense=Active_High
-CSET overflow_sense_axi=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_axis=Empty
-CSET programmable_empty_type_rach=Empty
-CSET programmable_empty_type_rdch=Empty
-CSET programmable_empty_type_wach=Empty
-CSET programmable_empty_type_wdch=Empty
-CSET programmable_empty_type_wrch=Empty
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET programmable_full_type_axis=Full
-CSET programmable_full_type_rach=Full
-CSET programmable_full_type_rdch=Full
-CSET programmable_full_type_wach=Full
-CSET programmable_full_type_wdch=Full
-CSET programmable_full_type_wrch=Full
-CSET rach_type=FIFO
-CSET rdch_type=FIFO
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=8
-CSET register_slice_mode_axis=Fully_Registered
-CSET register_slice_mode_rach=Fully_Registered
-CSET register_slice_mode_rdch=Fully_Registered
-CSET register_slice_mode_wach=Fully_Registered
-CSET register_slice_mode_wdch=Fully_Registered
-CSET register_slice_mode_wrch=Fully_Registered
-CSET reset_pin=false
-CSET reset_type=Asynchronous_Reset
-CSET ruser_width=1
-CSET tdata_width=64
-CSET tdest_width=4
-CSET tid_width=8
-CSET tkeep_width=4
-CSET tstrb_width=4
-CSET tuser_width=4
-CSET underflow_flag=false
-CSET underflow_flag_axi=false
-CSET underflow_sense=Active_High
-CSET underflow_sense_axi=Active_High
-CSET use_clock_enable=false
-CSET use_dout_reset=false
-CSET use_embedded_registers=false
-CSET use_extra_logic=true
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET wach_type=FIFO
-CSET wdch_type=FIFO
-CSET wrch_type=FIFO
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=8
-CSET wuser_width=1
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2011-02-03T22:23:32.000Z
-# END Extra information
-GENERATE
-# CRC: c4027d18
View
214 hdl/common/verilog/fifo_gen/nexys2-500/fifo_gen.batch
@@ -1,214 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 13.1
-# Date: Thu May 3 23:21:50 2012
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-NEWPROJECT .
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc3s500e
-SET devicefamily = spartan3e
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = fg320
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -4
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.1
-# END Select
-# BEGIN Parameters
-CSET add_ngc_constraint_axi=false
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET aruser_width=1
-CSET awuser_width=1
-CSET axi_address_width=32
-CSET axi_data_width=64
-CSET axi_type=AXI4_Stream
-CSET axis_type=FIFO
-CSET buser_width=1
-CSET clock_enable_type=Slave_Interface_Clock_Enable
-CSET clock_type_axi=Common_Clock
-CSET component_name=fifo
-CSET data_count=true
-CSET data_count_width=8
-CSET disable_timing_violations=false
-CSET disable_timing_violations_axi=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_assert_value_axis=1022
-CSET empty_threshold_assert_value_rach=1022
-CSET empty_threshold_assert_value_rdch=1022
-CSET empty_threshold_assert_value_wach=1022
-CSET empty_threshold_assert_value_wdch=1022
-CSET empty_threshold_assert_value_wrch=1022
-CSET empty_threshold_negate_value=5
-CSET enable_aruser=false
-CSET enable_awuser=false
-CSET enable_buser=false
-CSET enable_common_overflow=false
-CSET enable_common_underflow=false
-CSET enable_data_counts_axis=false
-CSET enable_data_counts_rach=false
-CSET enable_data_counts_rdch=false
-CSET enable_data_counts_wach=false
-CSET enable_data_counts_wdch=false
-CSET enable_data_counts_wrch=false
-CSET enable_ecc=false
-CSET enable_ecc_axis=false
-CSET enable_ecc_rach=false
-CSET enable_ecc_rdch=false
-CSET enable_ecc_wach=false
-CSET enable_ecc_wdch=false
-CSET enable_ecc_wrch=false
-CSET enable_handshake_flag_options_axis=false
-CSET enable_handshake_flag_options_rach=false
-CSET enable_handshake_flag_options_rdch=false
-CSET enable_handshake_flag_options_wach=false
-CSET enable_handshake_flag_options_wdch=false
-CSET enable_handshake_flag_options_wrch=false
-CSET enable_read_channel=false
-CSET enable_read_pointer_increment_by2=false
-CSET enable_reset_synchronization=true
-CSET enable_ruser=false
-CSET enable_tdata=false
-CSET enable_tdest=false
-CSET enable_tid=false
-CSET enable_tkeep=false
-CSET enable_tlast=false
-CSET enable_tready=true
-CSET enable_tstrobe=false
-CSET enable_tuser=false
-CSET enable_write_channel=false
-CSET enable_wuser=false
-CSET fifo_application_type_axis=Data_FIFO
-CSET fifo_application_type_rach=Data_FIFO
-CSET fifo_application_type_rdch=Data_FIFO
-CSET fifo_application_type_wach=Data_FIFO
-CSET fifo_application_type_wdch=Data_FIFO
-CSET fifo_application_type_wrch=Data_FIFO
-CSET fifo_implementation=Common_Clock_Block_RAM
-CSET fifo_implementation_axis=Common_Clock_Block_RAM
-CSET fifo_implementation_rach=Common_Clock_Block_RAM
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wach=Common_Clock_Block_RAM
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM
-CSET full_flags_reset_value=0
-CSET full_threshold_assert_value=127
-CSET full_threshold_assert_value_axis=1023
-CSET full_threshold_assert_value_rach=1023
-CSET full_threshold_assert_value_rdch=1023
-CSET full_threshold_assert_value_wach=1023
-CSET full_threshold_assert_value_wdch=1023
-CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=126
-CSET id_width=4
-CSET inject_dbit_error=false
-CSET inject_dbit_error_axis=false
-CSET inject_dbit_error_rach=false
-CSET inject_dbit_error_rdch=false
-CSET inject_dbit_error_wach=false
-CSET inject_dbit_error_wdch=false
-CSET inject_dbit_error_wrch=false
-CSET inject_sbit_error=false
-CSET inject_sbit_error_axis=false
-CSET inject_sbit_error_rach=false
-CSET inject_sbit_error_rdch=false
-CSET inject_sbit_error_wach=false
-CSET inject_sbit_error_wdch=false
-CSET inject_sbit_error_wrch=false
-CSET input_data_width=8
-CSET input_depth=128
-CSET input_depth_axis=1024
-CSET input_depth_rach=16
-CSET input_depth_rdch=1024
-CSET input_depth_wach=16
-CSET input_depth_wdch=1024
-CSET input_depth_wrch=16
-CSET interface_type=Native
-CSET output_data_width=8
-CSET output_depth=128
-CSET overflow_flag=false
-CSET overflow_flag_axi=false
-CSET overflow_sense=Active_High
-CSET overflow_sense_axi=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_axis=Empty
-CSET programmable_empty_type_rach=Empty
-CSET programmable_empty_type_rdch=Empty
-CSET programmable_empty_type_wach=Empty
-CSET programmable_empty_type_wdch=Empty
-CSET programmable_empty_type_wrch=Empty
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET programmable_full_type_axis=Full
-CSET programmable_full_type_rach=Full
-CSET programmable_full_type_rdch=Full
-CSET programmable_full_type_wach=Full
-CSET programmable_full_type_wdch=Full
-CSET programmable_full_type_wrch=Full
-CSET rach_type=FIFO
-CSET rdch_type=FIFO
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=8
-CSET register_slice_mode_axis=Fully_Registered
-CSET register_slice_mode_rach=Fully_Registered
-CSET register_slice_mode_rdch=Fully_Registered
-CSET register_slice_mode_wach=Fully_Registered
-CSET register_slice_mode_wdch=Fully_Registered
-CSET register_slice_mode_wrch=Fully_Registered
-CSET reset_pin=false
-CSET reset_type=Asynchronous_Reset
-CSET ruser_width=1
-CSET tdata_width=64
-CSET tdest_width=4
-CSET tid_width=8
-CSET tkeep_width=4
-CSET tstrb_width=4
-CSET tuser_width=4
-CSET underflow_flag=false
-CSET underflow_flag_axi=false
-CSET underflow_sense=Active_High
-CSET underflow_sense_axi=Active_High
-CSET use_clock_enable=false
-CSET use_dout_reset=false
-CSET use_embedded_registers=false
-CSET use_extra_logic=true
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET wach_type=FIFO
-CSET wdch_type=FIFO
-CSET wrch_type=FIFO
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=8
-CSET wuser_width=1
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2011-02-03T22:23:32.000Z
-# END Extra information
-GENERATE
-# CRC: c4027d18
View
214 hdl/common/verilog/fifo_gen/nexys3/fifo_gen.batch
@@ -1,214 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 13.1
-# Date: Thu May 3 23:21:50 2012
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-NEWPROJECT .
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc6slx16
-SET devicefamily = spartan6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = csg324
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.1
-# END Select
-# BEGIN Parameters
-CSET add_ngc_constraint_axi=false
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET aruser_width=1
-CSET awuser_width=1
-CSET axi_address_width=32
-CSET axi_data_width=64
-CSET axi_type=AXI4_Stream
-CSET axis_type=FIFO
-CSET buser_width=1
-CSET clock_enable_type=Slave_Interface_Clock_Enable
-CSET clock_type_axi=Common_Clock
-CSET component_name=fifo
-CSET data_count=true
-CSET data_count_width=8
-CSET disable_timing_violations=false
-CSET disable_timing_violations_axi=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_assert_value_axis=1022
-CSET empty_threshold_assert_value_rach=1022
-CSET empty_threshold_assert_value_rdch=1022
-CSET empty_threshold_assert_value_wach=1022
-CSET empty_threshold_assert_value_wdch=1022
-CSET empty_threshold_assert_value_wrch=1022
-CSET empty_threshold_negate_value=5
-CSET enable_aruser=false
-CSET enable_awuser=false
-CSET enable_buser=false
-CSET enable_common_overflow=false
-CSET enable_common_underflow=false
-CSET enable_data_counts_axis=false
-CSET enable_data_counts_rach=false
-CSET enable_data_counts_rdch=false
-CSET enable_data_counts_wach=false
-CSET enable_data_counts_wdch=false
-CSET enable_data_counts_wrch=false
-CSET enable_ecc=false
-CSET enable_ecc_axis=false
-CSET enable_ecc_rach=false
-CSET enable_ecc_rdch=false
-CSET enable_ecc_wach=false
-CSET enable_ecc_wdch=false
-CSET enable_ecc_wrch=false
-CSET enable_handshake_flag_options_axis=false
-CSET enable_handshake_flag_options_rach=false
-CSET enable_handshake_flag_options_rdch=false
-CSET enable_handshake_flag_options_wach=false
-CSET enable_handshake_flag_options_wdch=false
-CSET enable_handshake_flag_options_wrch=false
-CSET enable_read_channel=false
-CSET enable_read_pointer_increment_by2=false
-CSET enable_reset_synchronization=true
-CSET enable_ruser=false
-CSET enable_tdata=false
-CSET enable_tdest=false
-CSET enable_tid=false
-CSET enable_tkeep=false
-CSET enable_tlast=false
-CSET enable_tready=true
-CSET enable_tstrobe=false
-CSET enable_tuser=false
-CSET enable_write_channel=false
-CSET enable_wuser=false
-CSET fifo_application_type_axis=Data_FIFO
-CSET fifo_application_type_rach=Data_FIFO
-CSET fifo_application_type_rdch=Data_FIFO
-CSET fifo_application_type_wach=Data_FIFO
-CSET fifo_application_type_wdch=Data_FIFO
-CSET fifo_application_type_wrch=Data_FIFO
-CSET fifo_implementation=Common_Clock_Block_RAM
-CSET fifo_implementation_axis=Common_Clock_Block_RAM
-CSET fifo_implementation_rach=Common_Clock_Block_RAM
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wach=Common_Clock_Block_RAM
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM
-CSET full_flags_reset_value=0
-CSET full_threshold_assert_value=127
-CSET full_threshold_assert_value_axis=1023
-CSET full_threshold_assert_value_rach=1023
-CSET full_threshold_assert_value_rdch=1023
-CSET full_threshold_assert_value_wach=1023
-CSET full_threshold_assert_value_wdch=1023
-CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=126
-CSET id_width=4
-CSET inject_dbit_error=false
-CSET inject_dbit_error_axis=false
-CSET inject_dbit_error_rach=false
-CSET inject_dbit_error_rdch=false
-CSET inject_dbit_error_wach=false
-CSET inject_dbit_error_wdch=false
-CSET inject_dbit_error_wrch=false
-CSET inject_sbit_error=false
-CSET inject_sbit_error_axis=false
-CSET inject_sbit_error_rach=false
-CSET inject_sbit_error_rdch=false
-CSET inject_sbit_error_wach=false
-CSET inject_sbit_error_wdch=false
-CSET inject_sbit_error_wrch=false
-CSET input_data_width=8
-CSET input_depth=128
-CSET input_depth_axis=1024
-CSET input_depth_rach=16
-CSET input_depth_rdch=1024
-CSET input_depth_wach=16
-CSET input_depth_wdch=1024
-CSET input_depth_wrch=16
-CSET interface_type=Native
-CSET output_data_width=8
-CSET output_depth=128
-CSET overflow_flag=false
-CSET overflow_flag_axi=false
-CSET overflow_sense=Active_High
-CSET overflow_sense_axi=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_axis=Empty
-CSET programmable_empty_type_rach=Empty
-CSET programmable_empty_type_rdch=Empty
-CSET programmable_empty_type_wach=Empty
-CSET programmable_empty_type_wdch=Empty
-CSET programmable_empty_type_wrch=Empty
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET programmable_full_type_axis=Full
-CSET programmable_full_type_rach=Full
-CSET programmable_full_type_rdch=Full
-CSET programmable_full_type_wach=Full
-CSET programmable_full_type_wdch=Full
-CSET programmable_full_type_wrch=Full
-CSET rach_type=FIFO
-CSET rdch_type=FIFO
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=8
-CSET register_slice_mode_axis=Fully_Registered
-CSET register_slice_mode_rach=Fully_Registered
-CSET register_slice_mode_rdch=Fully_Registered
-CSET register_slice_mode_wach=Fully_Registered
-CSET register_slice_mode_wdch=Fully_Registered
-CSET register_slice_mode_wrch=Fully_Registered
-CSET reset_pin=false
-CSET reset_type=Asynchronous_Reset
-CSET ruser_width=1
-CSET tdata_width=64
-CSET tdest_width=4
-CSET tid_width=8
-CSET tkeep_width=4
-CSET tstrb_width=4
-CSET tuser_width=4
-CSET underflow_flag=false
-CSET underflow_flag_axi=false
-CSET underflow_sense=Active_High
-CSET underflow_sense_axi=Active_High
-CSET use_clock_enable=false
-CSET use_dout_reset=false
-CSET use_embedded_registers=false
-CSET use_extra_logic=true
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET wach_type=FIFO
-CSET wdch_type=FIFO
-CSET wrch_type=FIFO
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=8
-CSET wuser_width=1
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2011-02-03T22:23:32.000Z
-# END Extra information
-GENERATE
-# CRC: c4027d18
View
214 hdl/common/verilog/fifo_gen/s3board/fifo_gen.batch
@@ -1,214 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 13.1
-# Date: Thu May 3 23:21:50 2012
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-NEWPROJECT .
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc3s200
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = ft256
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -4
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.1
-# END Select
-# BEGIN Parameters
-CSET add_ngc_constraint_axi=false
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET aruser_width=1
-CSET awuser_width=1
-CSET axi_address_width=32
-CSET axi_data_width=64
-CSET axi_type=AXI4_Stream
-CSET axis_type=FIFO
-CSET buser_width=1
-CSET clock_enable_type=Slave_Interface_Clock_Enable
-CSET clock_type_axi=Common_Clock
-CSET component_name=fifo
-CSET data_count=true
-CSET data_count_width=8
-CSET disable_timing_violations=false
-CSET disable_timing_violations_axi=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_assert_value_axis=1022
-CSET empty_threshold_assert_value_rach=1022
-CSET empty_threshold_assert_value_rdch=1022
-CSET empty_threshold_assert_value_wach=1022
-CSET empty_threshold_assert_value_wdch=1022
-CSET empty_threshold_assert_value_wrch=1022
-CSET empty_threshold_negate_value=5
-CSET enable_aruser=false
-CSET enable_awuser=false
-CSET enable_buser=false
-CSET enable_common_overflow=false
-CSET enable_common_underflow=false
-CSET enable_data_counts_axis=false
-CSET enable_data_counts_rach=false
-CSET enable_data_counts_rdch=false
-CSET enable_data_counts_wach=false
-CSET enable_data_counts_wdch=false
-CSET enable_data_counts_wrch=false
-CSET enable_ecc=false
-CSET enable_ecc_axis=false
-CSET enable_ecc_rach=false
-CSET enable_ecc_rdch=false
-CSET enable_ecc_wach=false
-CSET enable_ecc_wdch=false
-CSET enable_ecc_wrch=false
-CSET enable_handshake_flag_options_axis=false
-CSET enable_handshake_flag_options_rach=false
-CSET enable_handshake_flag_options_rdch=false
-CSET enable_handshake_flag_options_wach=false
-CSET enable_handshake_flag_options_wdch=false
-CSET enable_handshake_flag_options_wrch=false
-CSET enable_read_channel=false
-CSET enable_read_pointer_increment_by2=false
-CSET enable_reset_synchronization=true
-CSET enable_ruser=false
-CSET enable_tdata=false
-CSET enable_tdest=false
-CSET enable_tid=false
-CSET enable_tkeep=false
-CSET enable_tlast=false
-CSET enable_tready=true
-CSET enable_tstrobe=false
-CSET enable_tuser=false
-CSET enable_write_channel=false
-CSET enable_wuser=false
-CSET fifo_application_type_axis=Data_FIFO
-CSET fifo_application_type_rach=Data_FIFO
-CSET fifo_application_type_rdch=Data_FIFO
-CSET fifo_application_type_wach=Data_FIFO
-CSET fifo_application_type_wdch=Data_FIFO
-CSET fifo_application_type_wrch=Data_FIFO
-CSET fifo_implementation=Common_Clock_Block_RAM
-CSET fifo_implementation_axis=Common_Clock_Block_RAM
-CSET fifo_implementation_rach=Common_Clock_Block_RAM
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wach=Common_Clock_Block_RAM
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM
-CSET full_flags_reset_value=0
-CSET full_threshold_assert_value=127
-CSET full_threshold_assert_value_axis=1023
-CSET full_threshold_assert_value_rach=1023
-CSET full_threshold_assert_value_rdch=1023
-CSET full_threshold_assert_value_wach=1023
-CSET full_threshold_assert_value_wdch=1023
-CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=126
-CSET id_width=4
-CSET inject_dbit_error=false
-CSET inject_dbit_error_axis=false
-CSET inject_dbit_error_rach=false
-CSET inject_dbit_error_rdch=false
-CSET inject_dbit_error_wach=false
-CSET inject_dbit_error_wdch=false
-CSET inject_dbit_error_wrch=false
-CSET inject_sbit_error=false
-CSET inject_sbit_error_axis=false
-CSET inject_sbit_error_rach=false
-CSET inject_sbit_error_rdch=false
-CSET inject_sbit_error_wach=false
-CSET inject_sbit_error_wdch=false
-CSET inject_sbit_error_wrch=false
-CSET input_data_width=8
-CSET input_depth=128
-CSET input_depth_axis=1024
-CSET input_depth_rach=16
-CSET input_depth_rdch=1024
-CSET input_depth_wach=16
-CSET input_depth_wdch=1024
-CSET input_depth_wrch=16
-CSET interface_type=Native
-CSET output_data_width=8
-CSET output_depth=128
-CSET overflow_flag=false
-CSET overflow_flag_axi=false
-CSET overflow_sense=Active_High
-CSET overflow_sense_axi=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_axis=Empty
-CSET programmable_empty_type_rach=Empty
-CSET programmable_empty_type_rdch=Empty
-CSET programmable_empty_type_wach=Empty
-CSET programmable_empty_type_wdch=Empty
-CSET programmable_empty_type_wrch=Empty
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET programmable_full_type_axis=Full
-CSET programmable_full_type_rach=Full
-CSET programmable_full_type_rdch=Full
-CSET programmable_full_type_wach=Full
-CSET programmable_full_type_wdch=Full
-CSET programmable_full_type_wrch=Full
-CSET rach_type=FIFO
-CSET rdch_type=FIFO
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=8
-CSET register_slice_mode_axis=Fully_Registered
-CSET register_slice_mode_rach=Fully_Registered
-CSET register_slice_mode_rdch=Fully_Registered
-CSET register_slice_mode_wach=Fully_Registered
-CSET register_slice_mode_wdch=Fully_Registered
-CSET register_slice_mode_wrch=Fully_Registered
-CSET reset_pin=false
-CSET reset_type=Asynchronous_Reset
-CSET ruser_width=1
-CSET tdata_width=64
-CSET tdest_width=4
-CSET tid_width=8
-CSET tkeep_width=4
-CSET tstrb_width=4
-CSET tuser_width=4
-CSET underflow_flag=false
-CSET underflow_flag_axi=false
-CSET underflow_sense=Active_High
-CSET underflow_sense_axi=Active_High
-CSET use_clock_enable=false
-CSET use_dout_reset=false
-CSET use_embedded_registers=false
-CSET use_extra_logic=true
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET wach_type=FIFO
-CSET wdch_type=FIFO
-CSET wrch_type=FIFO
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=8
-CSET wuser_width=1
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2011-02-03T22:23:32.000Z
-# END Extra information
-GENERATE
-# CRC: c4027d18
View
27 hdl/common/verilog/fifo_gen/xilinx.mk
@@ -1,27 +0,0 @@
-#
-# Copyright (C) 2009-2012 Chris McClelland
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU Lesser General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU Lesser General Public License for more details.
-#
-# You should have received a copy of the GNU Lesser General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-EXTRAS := fifo.ngc $(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo.v
-HDLS += $(COMMON)/$(HDL)/fifo_gen/fifo_wrapper_xilinx.v $(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo.v
-
-fifo.ngc: $(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo.ngc
- cp -p $< $@
-
-$(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo.v $(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo.ngc: $(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo_gen.batch
- cd $(COMMON)/$(HDL)/fifo_gen/$(PLATFORM) && coregen -b fifo_gen.batch
-
-fifoclean: FORCE
- cd $(COMMON)/$(HDL)/fifo_gen && for i in $$(find . -maxdepth 1 -mindepth 1 -type d); do mv $$i/fifo_gen.batch .; rm -rf $$i; mkdir $$i; mv fifo_gen.batch $$i; done
View
214 hdl/common/verilog/fifo_gen/xylo-l/fifo_gen.batch
@@ -1,214 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 13.1
-# Date: Thu May 3 23:21:50 2012
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-NEWPROJECT .
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc3s500e
-SET devicefamily = spartan3e
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = pq208
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -4
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.1
-# END Select
-# BEGIN Parameters
-CSET add_ngc_constraint_axi=false
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET aruser_width=1
-CSET awuser_width=1
-CSET axi_address_width=32
-CSET axi_data_width=64
-CSET axi_type=AXI4_Stream
-CSET axis_type=FIFO
-CSET buser_width=1
-CSET clock_enable_type=Slave_Interface_Clock_Enable
-CSET clock_type_axi=Common_Clock
-CSET component_name=fifo
-CSET data_count=true
-CSET data_count_width=8
-CSET disable_timing_violations=false
-CSET disable_timing_violations_axi=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_assert_value_axis=1022
-CSET empty_threshold_assert_value_rach=1022
-CSET empty_threshold_assert_value_rdch=1022
-CSET empty_threshold_assert_value_wach=1022
-CSET empty_threshold_assert_value_wdch=1022
-CSET empty_threshold_assert_value_wrch=1022
-CSET empty_threshold_negate_value=5
-CSET enable_aruser=false
-CSET enable_awuser=false
-CSET enable_buser=false
-CSET enable_common_overflow=false
-CSET enable_common_underflow=false
-CSET enable_data_counts_axis=false
-CSET enable_data_counts_rach=false
-CSET enable_data_counts_rdch=false
-CSET enable_data_counts_wach=false
-CSET enable_data_counts_wdch=false
-CSET enable_data_counts_wrch=false
-CSET enable_ecc=false
-CSET enable_ecc_axis=false
-CSET enable_ecc_rach=false
-CSET enable_ecc_rdch=false
-CSET enable_ecc_wach=false
-CSET enable_ecc_wdch=false
-CSET enable_ecc_wrch=false
-CSET enable_handshake_flag_options_axis=false
-CSET enable_handshake_flag_options_rach=false
-CSET enable_handshake_flag_options_rdch=false
-CSET enable_handshake_flag_options_wach=false
-CSET enable_handshake_flag_options_wdch=false
-CSET enable_handshake_flag_options_wrch=false
-CSET enable_read_channel=false
-CSET enable_read_pointer_increment_by2=false
-CSET enable_reset_synchronization=true
-CSET enable_ruser=false
-CSET enable_tdata=false
-CSET enable_tdest=false
-CSET enable_tid=false
-CSET enable_tkeep=false
-CSET enable_tlast=false
-CSET enable_tready=true
-CSET enable_tstrobe=false
-CSET enable_tuser=false
-CSET enable_write_channel=false
-CSET enable_wuser=false
-CSET fifo_application_type_axis=Data_FIFO
-CSET fifo_application_type_rach=Data_FIFO
-CSET fifo_application_type_rdch=Data_FIFO
-CSET fifo_application_type_wach=Data_FIFO
-CSET fifo_application_type_wdch=Data_FIFO
-CSET fifo_application_type_wrch=Data_FIFO
-CSET fifo_implementation=Common_Clock_Block_RAM
-CSET fifo_implementation_axis=Common_Clock_Block_RAM
-CSET fifo_implementation_rach=Common_Clock_Block_RAM
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wach=Common_Clock_Block_RAM
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM
-CSET full_flags_reset_value=0
-CSET full_threshold_assert_value=127
-CSET full_threshold_assert_value_axis=1023
-CSET full_threshold_assert_value_rach=1023
-CSET full_threshold_assert_value_rdch=1023
-CSET full_threshold_assert_value_wach=1023
-CSET full_threshold_assert_value_wdch=1023
-CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=126
-CSET id_width=4
-CSET inject_dbit_error=false
-CSET inject_dbit_error_axis=false
-CSET inject_dbit_error_rach=false
-CSET inject_dbit_error_rdch=false
-CSET inject_dbit_error_wach=false
-CSET inject_dbit_error_wdch=false
-CSET inject_dbit_error_wrch=false
-CSET inject_sbit_error=false
-CSET inject_sbit_error_axis=false
-CSET inject_sbit_error_rach=false
-CSET inject_sbit_error_rdch=false
-CSET inject_sbit_error_wach=false
-CSET inject_sbit_error_wdch=false
-CSET inject_sbit_error_wrch=false
-CSET input_data_width=8
-CSET input_depth=128
-CSET input_depth_axis=1024
-CSET input_depth_rach=16
-CSET input_depth_rdch=1024
-CSET input_depth_wach=16
-CSET input_depth_wdch=1024
-CSET input_depth_wrch=16
-CSET interface_type=Native
-CSET output_data_width=8
-CSET output_depth=128
-CSET overflow_flag=false
-CSET overflow_flag_axi=false
-CSET overflow_sense=Active_High
-CSET overflow_sense_axi=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_axis=Empty
-CSET programmable_empty_type_rach=Empty
-CSET programmable_empty_type_rdch=Empty
-CSET programmable_empty_type_wach=Empty
-CSET programmable_empty_type_wdch=Empty
-CSET programmable_empty_type_wrch=Empty
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET programmable_full_type_axis=Full
-CSET programmable_full_type_rach=Full
-CSET programmable_full_type_rdch=Full
-CSET programmable_full_type_wach=Full
-CSET programmable_full_type_wdch=Full
-CSET programmable_full_type_wrch=Full
-CSET rach_type=FIFO
-CSET rdch_type=FIFO
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=8
-CSET register_slice_mode_axis=Fully_Registered
-CSET register_slice_mode_rach=Fully_Registered
-CSET register_slice_mode_rdch=Fully_Registered
-CSET register_slice_mode_wach=Fully_Registered
-CSET register_slice_mode_wdch=Fully_Registered
-CSET register_slice_mode_wrch=Fully_Registered
-CSET reset_pin=false
-CSET reset_type=Asynchronous_Reset
-CSET ruser_width=1
-CSET tdata_width=64
-CSET tdest_width=4
-CSET tid_width=8
-CSET tkeep_width=4
-CSET tstrb_width=4
-CSET tuser_width=4
-CSET underflow_flag=false
-CSET underflow_flag_axi=false
-CSET underflow_sense=Active_High
-CSET underflow_sense_axi=Active_High
-CSET use_clock_enable=false
-CSET use_dout_reset=false
-CSET use_embedded_registers=false
-CSET use_extra_logic=true
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET wach_type=FIFO
-CSET wdch_type=FIFO
-CSET wrch_type=FIFO
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=8
-CSET wuser_width=1
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2011-02-03T22:23:32.000Z
-# END Extra information
-GENERATE
-# CRC: c4027d18
View
46 hdl/common/verilog/seven_seg/Makefile
@@ -1,46 +0,0 @@
-#
-# Copyright (C) 2012 Chris McClelland
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-MODULE := seven_seg
-HDLS := \
- ${MODULE}.v
-
-all: synthesis
-
-synthesis: ${HDLS}
- mkdir -p synthesis
- for i in ${HDLS}; do if [ "$${i##*.}" = "vhdl" ]; then echo "vhdl work \"$$i\""; elif [ "$${i##*.}" = "v" ]; then echo "verilog work \"$$i\""; fi; done > synthesis/$(MODULE).prj
- echo "set -tmpdir \"xst/projnav.tmp\"" > synthesis/platform.xst
- echo "set -xsthdpdir \"xst\"" >> synthesis/platform.xst
- echo "run" >> synthesis/platform.xst
- echo "-ifn ${MODULE}.prj" >> synthesis/platform.xst
- echo "-ifmt mixed" >> synthesis/platform.xst
- echo "-ofn ${MODULE}" >> synthesis/platform.xst
- echo "-ofmt NGC" >> synthesis/platform.xst
- echo "-p xc3s200-4-ft256" >> synthesis/platform.xst
- echo "-top ${MODULE}" >> synthesis/platform.xst
- echo "-opt_mode Speed" >> synthesis/platform.xst
- echo "-opt_level 1" >> synthesis/platform.xst
- cp ${HDLS} synthesis/
- mkdir -p synthesis/xst/projnav.tmp
- cd synthesis && xst -intstyle ise -ifn platform.xst -ofn ${MODULE}.syr
- grep WARNINGS synthesis/* | grep -Eq "XST_NUMBER_OF_WARNINGS\" value=\"0\""
- touch $@
-
-clean: FORCE
- rm -rf synthesis
-
-FORCE:
View
5 hdl/common/verilog/seven_seg/README
@@ -1,5 +0,0 @@
---------------------- VERILOG SEVEN-SEGMENT DISPLAY MODULE ---------------------
-
-Verilog seven-segment display driver. Accepts a 16-bit number for display in hex
-on four multiplexed 7-seg digits, and a four-bit number for display in binary on
-the four decimal points.
View
90 hdl/common/verilog/seven_seg/seven_seg.v
@@ -1,90 +0,0 @@
-//
-// Copyright (C) 2009-2012 Chris McClelland
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU Lesser General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU Lesser General Public License for more details.
-//
-// You should have received a copy of the GNU Lesser General Public License
-// along with this program. If not, see <http://www.gnu.org/licenses/>.
-//
-module
- seven_seg#(
- parameter
- // This can be overridden to change the refresh rate. The anode pattern will change at a
- // frequency given by F(clk_in) / (2**COUNTER_WIDTH). So for a 50MHz clk_in and
- // COUNTER_WIDTH=18, the anode pattern changes at ~191Hz, which means each digit gets
- // refreshed at ~48Hz.
- COUNTER_WIDTH = 18
- )(
- input wire clk_in,
- input wire[15:0] data_in,
- input wire[3:0] dots_in,
- output wire[7:0] segs_out,
- output wire[3:0] anodes_out
- );
-
- reg[COUNTER_WIDTH-1:0] count = 0;
- wire[COUNTER_WIDTH-1:0] count_next;
- wire[1:0] anodeSelect;
- wire[3:0] nibble;
- wire[6:0] segs;
- wire dot;
-
- // Infer counter register
- always @(posedge clk_in)
- count <= count_next;
-
- // Increment counter and derive anode select from top two bits
- assign count_next = count + 1'b1;
- assign anodeSelect = count[COUNTER_WIDTH-1:COUNTER_WIDTH-2];
-
- // Drive anodes
- assign anodes_out =
- (anodeSelect == 2'b00) ? 4'b0111 :
- (anodeSelect == 2'b01) ? 4'b1011 :
- (anodeSelect == 2'b10) ? 4'b1101 :
- 4'b1110;
-
- // Select the appropriate bit from dots_in
- assign dot =
- (anodeSelect == 2'b00) ? ~(dots_in[3]) :
- (anodeSelect == 2'b01) ? ~(dots_in[2]) :
- (anodeSelect == 2'b10) ? ~(dots_in[1]) :
- ~(dots_in[0]);
-
- // Choose a nibble to display
- assign nibble =
- (anodeSelect == 2'b00) ? data_in[15:12] :
- (anodeSelect == 2'b01) ? data_in[11:8] :
- (anodeSelect == 2'b10) ? data_in[7:4] :
- data_in[3:0];
-
- // Decode chosen nibble
- assign segs =
- (nibble == 4'b0000) ? 7'b1000000 :
- (nibble == 4'b0001) ? 7'b1111001 :
- (nibble == 4'b0010) ? 7'b0100100 :
- (nibble == 4'b0011) ? 7'b0110000 :
- (nibble == 4'b0100) ? 7'b0011001 :
- (nibble == 4'b0101) ? 7'b0010010 :
- (nibble == 4'b0110) ? 7'b0000010 :
- (nibble == 4'b0111) ? 7'b1111000 :
- (nibble == 4'b1000) ? 7'b0000000 :
- (nibble == 4'b1001) ? 7'b0010000 :
- (nibble == 4'b1010) ? 7'b0001000 :
- (nibble == 4'b1011) ? 7'b0000011 :
- (nibble == 4'b1100) ? 7'b1000110 :
- (nibble == 4'b1101) ? 7'b0100001 :
- (nibble == 4'b1110) ? 7'b0000110 :
- 7'b0001110;
-
- // Drive segs_out
- assign segs_out = {dot, segs};
-endmodule
View
46 hdl/common/verilog/timer/Makefile
@@ -1,46 +0,0 @@
-#
-# Copyright (C) 2012 Chris McClelland
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-MODULE := timer
-HDLS := \
- ${MODULE}.v
-
-all: synthesis
-
-synthesis: ${HDLS}
- mkdir -p synthesis
- for i in ${HDLS}; do if [ "$${i##*.}" = "vhdl" ]; then echo "vhdl work \"$$i\""; elif [ "$${i##*.}" = "v" ]; then echo "verilog work \"$$i\""; fi; done > synthesis/$(MODULE).prj
- echo "set -tmpdir \"xst/projnav.tmp\"" > synthesis/platform.xst
- echo "set -xsthdpdir \"xst\"" >> synthesis/platform.xst
- echo "run" >> synthesis/platform.xst
- echo "-ifn ${MODULE}.prj" >> synthesis/platform.xst
- echo "-ifmt mixed" >> synthesis/platform.xst
- echo "-ofn ${MODULE}" >> synthesis/platform.xst
- echo "-ofmt NGC" >> synthesis/platform.xst
- echo "-p xc3s200-4-ft256" >> synthesis/platform.xst
- echo "-top ${MODULE}" >> synthesis/platform.xst
- echo "-opt_mode Speed" >> synthesis/platform.xst
- echo "-opt_level 1" >> synthesis/platform.xst
- cp ${HDLS} synthesis/
- mkdir -p synthesis/xst/projnav.tmp
- cd synthesis && xst -intstyle ise -ifn platform.xst -ofn ${MODULE}.syr
- grep WARNINGS synthesis/* | grep -Eq "XST_NUMBER_OF_WARNINGS\" value=\"0\""
- touch $@
-
-clean: FORCE
- rm -rf synthesis
-
-FORCE:
View
16 hdl/common/verilog/timer/README
@@ -1,16 +0,0 @@
------------------------------ VERILOG TIMER MODULE -----------------------------
-
-Verilog timer unit. Accepts a clock and a ceiling value. It just counts up and
-asserts tick_out when it wraps. The ceiling value specifies (roughly speaking)
-the number of bits to use in the counter.
-
-The actual formula is that tick_out is high for one cycle, then low for a
-number of cycles given by 2^(COUNTER_WIDTH - ceiling_in). You should make sure
-COUNTER_WIDTH > 2^CEILING_WIDTH.
-
-COUNTER_WIDTH=4:
- CEILING_WIDTH=2:
- ceiling_in=0: tick_out high for one cycle, low for 16 cycles
- ceiling_in=1: tick_out high for one cycle, low for 8 cycles
- ceiling_in=2: tick_out high for one cycle, low for 4 cycles
- ceiling_in=3: tick_out high for one cycle, low for 2 cycles
View
58 hdl/common/verilog/timer/timer.v
@@ -1,58 +0,0 @@
-//
-// Copyright (C) 2009-2012 Chris McClelland
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU Lesser General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU Lesser General Public License for more details.
-//
-// You should have received a copy of the GNU Lesser General Public License
-// along with this program. If not, see <http://www.gnu.org/licenses/>.
-//
-module
- timer#(
- parameter
- // This gives the number of bits to be counted when ceiling_in is zero
- COUNTER_WIDTH = 25,
- // This gives the number of bits in the ceiling value
- CEILING_WIDTH = 4
- )(
- input wire clk_in,
- input wire[CEILING_WIDTH-1:0] ceiling_in,
- output reg tick_out
- );
-
- localparam TOP_BIT = 2**CEILING_WIDTH - 1;
- function[TOP_BIT:0] reverse(input[COUNTER_WIDTH:0] fwd);
- integer i;
- for ( i = 0; i <= TOP_BIT; i = i + 1 )
- reverse[i] = fwd[COUNTER_WIDTH-i];
- endfunction
- reg[COUNTER_WIDTH:0] count_next, count = 0;
- wire[TOP_BIT:0] revCount;
-
- // Infer registers
- always @(posedge clk_in)
- count <= count_next;
-
- assign revCount = reverse(count);
-
- always @*
- begin
- if ( revCount[ceiling_in] == 1'b0 )
- begin
- count_next = count + 1'b1;
- tick_out = 1'b0;
- end
- else
- begin
- count_next = 0;
- tick_out = 1'b1;
- end
- end
-endmodule
View
4 hdl/common/vhdl/fifo_gen/README
@@ -1,4 +0,0 @@
---------------------------- VHDL COREGEN FIFO MODULE ---------------------------
-
-A COREgen project which generates a FIFO for use by the ex_fifo examples. There
-is also a wrapper which follows the more usual {data,valid,ready} convention.
View
27 hdl/common/vhdl/fifo_gen/altera.mk
@@ -1,27 +0,0 @@
-#
-# Copyright (C) 2009-2012 Chris McClelland
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU Lesser General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU Lesser General Public License for more details.
-#
-# You should have received a copy of the GNU Lesser General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-EXTRAS := $(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo.vhdl
-HDLS += $(COMMON)/$(HDL)/fifo_gen/fifo_wrapper_altera.vhdl $(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo.vhdl
-
-$(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo.vhdl: $(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo.vhd
- cp -p $< $@
-
-$(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo.vhd $(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo.ngc: $(COMMON)/$(HDL)/fifo_gen/$(PLATFORM)/fifo_gen.batch
- cd $(COMMON)/$(HDL)/fifo_gen/$(PLATFORM) && qmegawiz -silent module=scfifo -f:fifo_gen.batch fifo.vhd
-
-fifoclean: FORCE
- cd $(COMMON)/$(HDL)/fifo_gen && for i in $$(find . -maxdepth 1 -mindepth 1 -type d); do mv $$i/fifo_gen.batch .; rm -rf $$i; mkdir $$i; mv fifo_gen.batch $$i; done
View
214 hdl/common/vhdl/fifo_gen/atlys/fifo_gen.batch
@@ -1,214 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 13.1
-# Date: Thu May 3 23:21:50 2012
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-NEWPROJECT .
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6slx45
-SET devicefamily = spartan6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = csg324
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.1
-# END Select
-# BEGIN Parameters
-CSET add_ngc_constraint_axi=false
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET aruser_width=1
-CSET awuser_width=1
-CSET axi_address_width=32
-CSET axi_data_width=64
-CSET axi_type=AXI4_Stream
-CSET axis_type=FIFO
-CSET buser_width=1
-CSET clock_enable_type=Slave_Interface_Clock_Enable
-CSET clock_type_axi=Common_Clock
-CSET component_name=fifo
-CSET data_count=true
-CSET data_count_width=8
-CSET disable_timing_violations=false
-CSET disable_timing_violations_axi=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_assert_value_axis=1022
-CSET empty_threshold_assert_value_rach=1022
-CSET empty_threshold_assert_value_rdch=1022
-CSET empty_threshold_assert_value_wach=1022
-CSET empty_threshold_assert_value_wdch=1022
-CSET empty_threshold_assert_value_wrch=1022
-CSET empty_threshold_negate_value=5
-CSET enable_aruser=false
-CSET enable_awuser=false
-CSET enable_buser=false
-CSET enable_common_overflow=false
-CSET enable_common_underflow=false
-CSET enable_data_counts_axis=false
-CSET enable_data_counts_rach=false
-CSET enable_data_counts_rdch=false
-CSET enable_data_counts_wach=false
-CSET enable_data_counts_wdch=false
-CSET enable_data_counts_wrch=false
-CSET enable_ecc=false
-CSET enable_ecc_axis=false
-CSET enable_ecc_rach=false
-CSET enable_ecc_rdch=false
-CSET enable_ecc_wach=false
-CSET enable_ecc_wdch=false
-CSET enable_ecc_wrch=false
-CSET enable_handshake_flag_options_axis=false
-CSET enable_handshake_flag_options_rach=false
-CSET enable_handshake_flag_options_rdch=false
-CSET enable_handshake_flag_options_wach=false
-CSET enable_handshake_flag_options_wdch=false
-CSET enable_handshake_flag_options_wrch=false
-CSET enable_read_channel=false
-CSET enable_read_pointer_increment_by2=false
-CSET enable_reset_synchronization=true
-CSET enable_ruser=false
-CSET enable_tdata=false
-CS