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Renaming SVF files in examples, etc

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1 parent 85f720b commit 599727e1002ac6127bb5ac3ffe5d67e439d69010 makestuff committed May 5, 2012
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@@ -21,66 +21,66 @@ board.
Linux x86_64 (Release):
gcc -m64 -O3 -Wall -Wextra -Wundef -pedantic-errors -std=c99 -Wstrict-prototypes -Wno-missing-field-initializers -I../.. -I../../../../common -Wl,--relax,--gc-sections,-rpath,\$ORIGIN,-rpath-link,../../linux.x86_64/rel -o ../../linux.x86_64/rel/fpgalink *.c -L../../linux.x86_64/rel -lfpgalink
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- sudo ../../linux.x86_64/rel/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ sudo ../../linux.x86_64/rel/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
Linux x86_64 (Debug):
gcc -m64 -g -Wall -Wextra -Wundef -pedantic-errors -std=c99 -Wstrict-prototypes -Wno-missing-field-initializers -I../.. -I../../../../common -Wl,--relax,--gc-sections,-rpath,\$ORIGIN,-rpath-link,../../linux.x86_64/dbg -o ../../linux.x86_64/dbg/fpgalink *.c -L../../linux.x86_64/dbg -lfpgalink
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- sudo ../../linux.x86_64/dbg/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ sudo ../../linux.x86_64/dbg/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
Linux i686 (Release):
gcc -m32 -O3 -Wall -Wextra -Wundef -pedantic-errors -std=c99 -Wstrict-prototypes -Wno-missing-field-initializers -I../.. -I../../../../common -Wl,--relax,--gc-sections,-rpath,\$ORIGIN,-rpath-link,../../linux.i686/rel -o ../../linux.i686/rel/fpgalink *.c -L../../linux.i686/rel -lfpgalink
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- sudo ../../linux.i686/rel/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ sudo ../../linux.i686/rel/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
Linux i686 (Debug):
gcc -m32 -g -Wall -Wextra -Wundef -pedantic-errors -std=c99 -Wstrict-prototypes -Wno-missing-field-initializers -I../.. -I../../../../common -Wl,--relax,--gc-sections,-rpath,\$ORIGIN,-rpath-link,../../linux.i686/dbg -o ../../linux.i686/dbg/fpgalink *.c -L../../linux.i686/dbg -lfpgalink
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- sudo ../../linux.i686/dbg/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ sudo ../../linux.i686/dbg/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
Linux armel (Release):
gcc -O3 -Wall -Wextra -Wundef -pedantic-errors -std=c99 -Wstrict-prototypes -Wno-missing-field-initializers -I../.. -I../../../../common -Wl,--relax,--gc-sections,-rpath,\$ORIGIN,-rpath-link,../../linux.armel/rel -o ../../linux.armel/rel/fpgalink *.c -L../../linux.armel/rel -lfpgalink
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- sudo ../../linux.armel/rel/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ sudo ../../linux.armel/rel/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
Linux armel (Debug):
gcc -g -Wall -Wextra -Wundef -pedantic-errors -std=c99 -Wstrict-prototypes -Wno-missing-field-initializers -I../.. -I../../../../common -Wl,--relax,--gc-sections,-rpath,\$ORIGIN,-rpath-link,../../linux.armel/dbg -o ../../linux.armel/dbg/fpgalink *.c -L../../linux.armel/dbg -lfpgalink
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- sudo ../../linux.armel/dbg/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ sudo ../../linux.armel/dbg/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
Linux ppc (Release):
gcc -O3 -Wall -Wextra -Wundef -pedantic-errors -std=c99 -Wstrict-prototypes -Wno-missing-field-initializers -I../.. -I../../../../common -Wl,--relax,--gc-sections,-rpath,\$ORIGIN,-rpath-link,../../linux.ppc/rel -o ../../linux.ppc/rel/fpgalink *.c -L../../linux.ppc/rel -lfpgalink
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- sudo ../../linux.ppc/rel/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ sudo ../../linux.ppc/rel/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
Linux ppc (Debug):
gcc -g -Wall -Wextra -Wundef -pedantic-errors -std=c99 -Wstrict-prototypes -Wno-missing-field-initializers -I../.. -I../../../../common -Wl,--relax,--gc-sections,-rpath,\$ORIGIN,-rpath-link,../../linux.ppc/dbg -o ../../linux.ppc/dbg/fpgalink *.c -L../../linux.ppc/dbg -lfpgalink
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- sudo ../../linux.ppc/dbg/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ sudo ../../linux.ppc/dbg/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
MacOSX (Release):
gcc -O3 -Wall -Wextra -Wundef -pedantic-errors -std=c99 -Wstrict-prototypes -Wno-missing-field-initializers -I../.. -I../../../../common -Wl,-rpath,@loader_path/ -o ../../darwin/rel/fpgalink *.c -L../../darwin/rel -lfpgalink
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- ../../darwin/rel/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ ../../darwin/rel/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
MacOSX (Debug):
gcc -gstabs+ -Wall -Wextra -Wundef -pedantic-errors -std=c99 -Wstrict-prototypes -Wno-missing-field-initializers -I../.. -I../../../../common -Wl,-rpath,@loader_path/ -o ../../darwin/dbg/fpgalink *.c -L../../darwin/dbg -lfpgalink
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- ../../darwin/dbg/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ ../../darwin/dbg/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
Windows (Release):
(assuming running from http://bit.ly/k0ydbN)
cl -O2 -Oi -DWIN32 -D_CRT_SECURE_NO_WARNINGS -EHsc -W4 -nologo -errorReport:prompt -I../.. -I../../../../common -DNDEBUG -D_CONSOLE -FD -MD -Gy -GL -Zi -Fe../../win32/rel/fpgalink.exe *.c ../../win32/rel/libfpgalink.lib kernel32.lib user32.lib
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- ../../win32/rel/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ ../../win32/rel/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
Windows (Debug):
(assuming running from http://bit.ly/k0ydbN)
cl -Od -DWIN32 -D_CRT_SECURE_NO_WARNINGS -EHsc -W4 -nologo -errorReport:prompt -I../.. -I../../../../common -D_DEBUG -D_CONSOLE -Gm -RTC1 -MDd -ZI -Fe../../win32/dbg/fpgalink.exe *.c ../../win32/dbg/libfpgalink.lib kernel32.lib user32.lib
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- ../../win32/dbg/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ ../../win32/dbg/fpgalink -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
This connects to the device at 1443:0005 (hopefully a 1200K Digilent Nexys2), loads the onboard FX2
-chip with a new firmware, loads the nexys2-1200.csvf design into the board's FPGA, and then does
-some register reads and writes. The changes to the board are lost on the next power cycle, so it's
-safe to try.
+chip with a new firmware, loads the ex_cksum_nexys2-1200_vhdl.csvf design into the board's FPGA,
+and then does some register reads and writes. The changes to the board are lost on the next power
+cycle, so it's safe to try.
@@ -1,14 +1,15 @@
CALLING FPGALINK FROM EXCEL/VBA
This example sheet connects to the device at 1443:0005 (hopefully a 1200K Digilent Nexys2), loads
-the onboard FX2 chip with a new firmware, loads the nexys2-1200.xsvf design into the board's FPGA,
-and then does some register reads and writes. The changes to the board are lost on the next power
-cycle, so it's safe to try.
+the onboard FX2 chip with a new firmware, loads the ex_cksum_nexys2-1200_vhdl.csvf design into the
+board's FPGA, and then does some register reads and writes. The changes to the board are lost on
+the next power cycle, so it's safe to try.
You may need to install the Visual C++ 2010 redistributable package:
http://www.microsoft.com/download/en/details.aspx?id=5555
The C functions in the FPGALink DLL are wrapped in VBA functions in the FPGALink module.
For Atlys and Nexys3, uncheck "Power on PD7" and enter "1443:0007" instead of "1443:0005" for
-"Initial VID/PID" and "Renum VID/PID", and choose the appropriate XSVF file for your board.
+"Initial VID/PID" and "Renum VID/PID", and choose the appropriate SVF, XSVF or CSVF file for your
+board.
@@ -17,7 +17,7 @@ board.
-s scan the JTAG chain
-v <VID:PID> renumerated vendor and product ID of the FPGALink device
-i <VID:PID> initial vendor and product ID of the FPGALink device
- -x <xsvfFile> XSVF or CSVF file to play into the JTAG chain
+ -x <xsvfFile> SVF, XSVF or CSVF file to play into the JTAG chain
-f <dataFile> binary data to write to register 0
There are separate bindings for different Python versions:
@@ -33,31 +33,31 @@ NONINTERACTIVE EXECUTION
Linux x86_64:
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- sudo LD_LIBRARY_PATH=../../linux.x86_64/rel ./fpgalink2.py -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ sudo LD_LIBRARY_PATH=../../linux.x86_64/rel ./fpgalink2.py -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
Linux i686:
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- sudo LD_LIBRARY_PATH=../../linux.i686/rel ./fpgalink2.py -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ sudo LD_LIBRARY_PATH=../../linux.i686/rel ./fpgalink2.py -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
Linux armel:
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- sudo LD_LIBRARY_PATH=../../linux.armel/rel ./fpgalink2.py -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ sudo LD_LIBRARY_PATH=../../linux.armel/rel ./fpgalink2.py -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
NOTE: With Python 2.6 you will need to install the argparse module, thus:
wget -qO- 'http://argparse.googlecode.com/files/argparse-1.2.1.tar.gz' | tar zxf -
sudo cp argparse-1.2.1/argparse.py /usr/lib/pymodules/python2.6/
Linux ppc:
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- sudo LD_LIBRARY_PATH=../../linux.ppc/rel ./fpgalink2.py -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ sudo LD_LIBRARY_PATH=../../linux.ppc/rel ./fpgalink2.py -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
NOTE: With Python 2.5 & 2.6 you will need to install the argparse module, thus:
wget -qO- 'http://argparse.googlecode.com/files/argparse-1.2.1.tar.gz' | tar zxf -
sudo cp argparse-1.2.1/argparse.py /usr/lib/python2.5/site-packages/ (or .../python2.6/...)
MacOSX:
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- DYLD_LIBRARY_PATH=../../darwin/rel ./fpgalink2.py -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ DYLD_LIBRARY_PATH=../../darwin/rel ./fpgalink2.py -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
NOTE: On Snow Leopard you will need to install the argparse module (not required for Lion), thus:
curl -sL 'http://argparse.googlecode.com/files/argparse-1.2.1.tar.gz' | tar zxf -
@@ -66,10 +66,10 @@ MacOSX:
Windows (assuming you're running from http://bit.ly/k0ydbN):
dd of=/var/tmp/foo.dat if=/dev/urandom bs=65536 count=160
- PATH=../../win32/rel:$PATH /c/Python27/python fpgalink2.py -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/nexys2-1200.csvf -f /var/tmp/foo.dat
+ PATH=../../win32/rel:$PATH /c/Python27/python fpgalink2.py -p -s -v 1443:0005 -i 1443:0005 -x ../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -f /var/tmp/foo.dat
This connects to the device at 1443:0005 (hopefully a 1200K Digilent Nexys2), loads the onboard FX2
-chip with a new firmware, loads the nexys2-1200.csvf design into the board's FPGA, and then does
+chip with a new firmware, loads the ex_cksum_nexys2-1200_vhdl.csvf design into the board's FPGA, and then does
some register reads and writes. The changes to the board are lost on the next power cycle, so it's
safe to try.
@@ -85,7 +85,7 @@ You can also use it in interactive mode (Linux x86_64):
>>> flLoadStandardFirmware("1443:0005", "1443:0005") # 1443:0007 for Nexys3 & Atlys
>>> handle = flOpen("1443:0005")
>>> flPortAccess(handle, 0x0080, 0x0080) # Skip this for Nexys3 & Atlys
- >>> flPlayXSVF(handle, "../../gen_csvf/nexys2-1200.csvf") # Or atlys.csvf/nexys3.csvf
+ >>> flPlayXSVF(handle, "../../gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf") # Or other SVF, XSVF or CSVF
>>> flWriteRegister(handle, 1000, 0x00, 0x10)
>>> flClose(handle)
>>>
@@ -34,7 +34,7 @@ handle = flOpen("04B4:8613")
flAppendWriteRegisterCommand(handle, 0x00, 0x10)
flAppendWriteRegisterCommand(handle, 0x00, 0x10)
flAppendWriteRegisterCommand(handle, 0x00, 0x10)
-flFlashStandardFirmware(handle, "04B4:8613", "${JTAG_PORT}", 512, "../../gen_csvf/s3board.csvf")
+flFlashStandardFirmware(handle, "04B4:8613", "${JTAG_PORT}", 512, "../../gen_csvf/ex_cksum_s3board_vhdl.csvf")
flClose(handle)
quit()
EOF
@@ -294,7 +294,7 @@ def flFlashStandardFirmware(handle, newVidPid, jtagPort, eepromSize, xsvfFile =
parser.add_argument('-v', action="store", nargs=1, required=True, metavar="<VID:PID>", help="renumerated vendor and product ID of the FPGALink device")
parser.add_argument('-i', action="store", nargs=1, metavar="<VID:PID>", help="initial vendor and product ID of the (FX2LP-based) FPGALink device")
parser.add_argument('-j', action="store", nargs=1, metavar="<jtagPort>", help="JTAG port specification for the (FX2LP-based) FPGALink device")
- parser.add_argument('-x', action="store", nargs=1, metavar="<xsvfFile>", help="XSVF or CSVF file to play into the JTAG chain")
+ parser.add_argument('-x', action="store", nargs=1, metavar="<xsvfFile>", help="SVF, XSVF or CSVF file to play into the JTAG chain")
parser.add_argument('-f', action="store", nargs=1, metavar="<dataFile>", help="binary data to write to register 0")
argList = parser.parse_args()
handle = FLHandle()
View
@@ -5,11 +5,11 @@ if [ $# != 1 ]; then
exit 1
fi
-export X2C=$(pwd)
+export HDL=$(pwd)
+export X2C=${HDL}/../$1
echo HDL build starting at $(date)...
-export HDL=$(dirname $0)
rm -rf ../gen_xsvf ../gen_csvf
mkdir ../gen_xsvf ../gen_csvf
for p in atlys lx9 nexys2-1200 nexys2-500 nexys3 s3board xylo-l; do
View
@@ -146,7 +146,7 @@ Interact with an FPGALink device.
So assuming you're using a Digilent Nexys2 connected to an ARM Linux machine:
-chris@armel$ sudo linux.armel/rel/flcli -i 1443:0005 -v 1443:0005 -x gen_csvf/nexys2-1200.csvf -p -s
+chris@armel$ sudo linux.armel/rel/flcli -i 1443:0005 -v 1443:0005 -x gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf -p -s
Attempting to open connection to FPGALink device 1443:0005...
Loading firmware into 1443:0005...
Awaiting renumeration............
@@ -155,7 +155,7 @@ Connecting USB power to FPGA...
The FPGALink device at 1443:0005 scanned its JTAG chain, yielding:
0x21C2E093
0xF5046093
-Playing "gen_csvf/nexys2-1200.csvf" into the JTAG chain on FPGALink device 1443:0005...
+Playing "gen_csvf/ex_cksum_nexys2-1200_vhdl.csvf" into the JTAG chain on FPGALink device 1443:0005...
chris@armel$
You can then connect to the device with a simple command-line interface:
@@ -199,11 +199,11 @@ TEST(FL_playXsvf) {
CHECK_EQUAL(FL_UNSUPPORTED_CMD_ERR, fStatus);
// Verify that the AVR (having nothing on its JTAG lines) gives FL_JTAG_ERR because the XSVF's IDCODE check fails
- fStatus = flPlayXSVF(avrHandle, "../gen_xsvf/s3board.xsvf", NULL);
+ fStatus = flPlayXSVF(avrHandle, "../gen_xsvf/ex_cksum_s3board_vhdl.xsvf", NULL);
CHECK_EQUAL(FL_JTAG_ERR, fStatus);
- // Verify that the FX2 (having an s3board on its JTAG lines) gives FL_JTAG_ERR because nexys2-1200.xsvf's IDCODE check fails
- fStatus = flPlayXSVF(fx2Handle, "../gen_xsvf/nexys2-1200.xsvf", NULL);
+ // Verify that the FX2 (having an s3board on its JTAG lines) gives FL_JTAG_ERR because the XSVF's IDCODE check fails
+ fStatus = flPlayXSVF(fx2Handle, "../gen_xsvf/ex_cksum_nexys2-1200_vhdl.xsvf", NULL);
CHECK_EQUAL(FL_JTAG_ERR, fStatus);
}
@@ -74,9 +74,32 @@ static void testRoundTrip(const char *xsvfFile, uint32 expectedMaxBufSize) {
}
TEST(FPGALink_testRoundTrip) {
- testRoundTrip("../gen_xsvf/s3board.xsvf", 5U);
- testRoundTrip("../gen_xsvf/nexys2-500.xsvf", 5U);
- testRoundTrip("../gen_xsvf/nexys2-1200.xsvf", 5U);
- testRoundTrip("../gen_xsvf/atlys.xsvf", 4U);
- testRoundTrip("../gen_xsvf/nexys3.xsvf", 4U);
+ testRoundTrip("../gen_xsvf/ex_cksum_atlys_verilog.xsvf", 4U);
+ testRoundTrip("../gen_xsvf/ex_cksum_atlys_vhdl.xsvf", 4U);
+ testRoundTrip("../gen_xsvf/ex_cksum_lx9_verilog.xsvf", 5U);
+ testRoundTrip("../gen_xsvf/ex_cksum_lx9_vhdl.xsvf", 5U);
+ testRoundTrip("../gen_xsvf/ex_cksum_nexys2-1200_verilog.xsvf", 5U);
+ testRoundTrip("../gen_xsvf/ex_cksum_nexys2-1200_vhdl.xsvf", 5U);
+ testRoundTrip("../gen_xsvf/ex_cksum_nexys2-500_verilog.xsvf", 5U);
+ testRoundTrip("../gen_xsvf/ex_cksum_nexys2-500_vhdl.xsvf", 5U);
+ testRoundTrip("../gen_xsvf/ex_cksum_nexys3_verilog.xsvf", 4U);
+ testRoundTrip("../gen_xsvf/ex_cksum_nexys3_vhdl.xsvf", 4U);
+ testRoundTrip("../gen_xsvf/ex_cksum_s3board_verilog.xsvf", 5U);
+ testRoundTrip("../gen_xsvf/ex_cksum_s3board_vhdl.xsvf", 5U);
+ testRoundTrip("../gen_xsvf/ex_cksum_xylo-l_verilog.xsvf", 4U);
+ testRoundTrip("../gen_xsvf/ex_cksum_xylo-l_vhdl.xsvf", 4U);
+ testRoundTrip("../gen_xsvf/ex_fifo_atlys_verilog.xsvf", 4U);
+ testRoundTrip("../gen_xsvf/ex_fifo_atlys_vhdl.xsvf", 4U);
+ testRoundTrip("../gen_xsvf/ex_fifo_lx9_verilog.xsvf", 5U);
+ testRoundTrip("../gen_xsvf/ex_fifo_lx9_vhdl.xsvf", 5U);
+ testRoundTrip("../gen_xsvf/ex_fifo_nexys2-1200_verilog.xsvf", 5U);
+ testRoundTrip("../gen_xsvf/ex_fifo_nexys2-1200_vhdl.xsvf", 5U);
+ testRoundTrip("../gen_xsvf/ex_fifo_nexys2-500_verilog.xsvf", 5U);
+ testRoundTrip("../gen_xsvf/ex_fifo_nexys2-500_vhdl.xsvf", 5U);
+ testRoundTrip("../gen_xsvf/ex_fifo_nexys3_verilog.xsvf", 4U);
+ testRoundTrip("../gen_xsvf/ex_fifo_nexys3_vhdl.xsvf", 4U);
+ testRoundTrip("../gen_xsvf/ex_fifo_s3board_verilog.xsvf", 5U);
+ testRoundTrip("../gen_xsvf/ex_fifo_s3board_vhdl.xsvf", 5U);
+ testRoundTrip("../gen_xsvf/ex_fifo_xylo-l_verilog.xsvf", 4U);
+ testRoundTrip("../gen_xsvf/ex_fifo_xylo-l_vhdl.xsvf", 4U);
}

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