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Removed auto-generated files from git

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1 parent e6c3952 commit f628291db2f4e0304e9debeba678556f23ac5ca4 makestuff committed Mar 15, 2013
@@ -1,38 +0,0 @@
-// Infer registers
-always @(posedge clk_in)
-begin
- if ( reset_in == 1'b1 )
- count <= 8'h00;
- else
- count <= count_next;
-end
-
-// Wire up write FIFO to channel 0 writes:
-// flags(2) driven by writeFifoOutputValid
-// writeFifoOutputReady driven by consumer_timer
-// LEDs driven by writeFifoOutputData
-assign writeFifoInputData =
- h2fData_in;
-assign writeFifoInputValid =
- (h2fValid_in == 1'b1 && chanAddr_in == 7'b0000000) ? 1'b1 : 1'b0;
-assign h2fReady_out =
- (writeFifoInputReady == 1'b0 && chanAddr_in == 7'b0000000) ? 1'b0 : 1'b1;
-
-// Wire up read FIFO to channel 0 reads:
-// readFifoInputValid driven by producer_timer
-// flags(0) driven by readFifoInputReady
-assign count_next =
- (readFifoInputValid == 1'b1) ? count + 1'b1 : count;
-assign readFifoInputData =
- count;
-assign f2hValid_out =
- (readFifoOutputValid == 1'b0 && chanAddr_in == 7'b0000000) ? 1'b0 : 1'b1;
-assign readFifoOutputReady =
- (f2hReady_in == 1'b1 && chanAddr_in == 7'b0000000) ? 1'b1 : 1'b0;
-
-// Select values to return for each channel when the host is reading
-assign f2hData_out =
- (chanAddr_in == 7'b0000000) ? readFifoOutputData : // get from read FIFO
- (chanAddr_in == 7'b0000001) ? fifoCount[15:8] : // get depth of write FIFO
- (chanAddr_in == 7'b0000010) ? fifoCount[7:0] : // get depth of write FIFO
- 8'h00;
@@ -1,38 +0,0 @@
-// Infer registers
-always @(posedge clk_in)
-begin
- if ( reset_in == 1'b1 )
- begin
- reg0 <= 8'h00;
- checksum <= 16'h0000;
- end
- else
- begin
- reg0 <= reg0_next;
- checksum <= checksum_next;
- end
-end
-
-// Drive register inputs for each channel when the host is writing
-assign reg0_next =
- (chanAddr_in == 7'b0000000 && h2fValid_in == 1'b1) ? h2fData_in :
- reg0;
-assign checksum_next =
- (chanAddr_in == 7'b0000000 && h2fValid_in == 1'b1) ?
- checksum + h2fData_in :
- (chanAddr_in == 7'b0000001 && h2fValid_in == 1'b1) ?
- {h2fData_in, checksum[7:0]} :
- (chanAddr_in == 7'b0000010 && h2fValid_in == 1'b1) ?
- {checksum[15:8], h2fData_in} :
- checksum;
-
-// Select values to return for each channel when the host is reading
-assign f2hData_out =
- (chanAddr_in == 7'b0000000) ? sw_in :
- (chanAddr_in == 7'b0000001) ? checksum[15:8] :
- (chanAddr_in == 7'b0000010) ? checksum[7:0] :
- 8'h00;
-
-// Assert that there's always data for reading, and always room for writing
-assign f2hValid_out = 1'b1;
-assign h2fReady_out = 1'b1;
@@ -1,46 +0,0 @@
--- Infer registers
-process(clk_in)
-begin
- if ( rising_edge(clk_in) ) then
- if ( reset_in = '1' ) then
- count <= (others => '0');
- else
- count <= count_next;
- end if;
- end if;
-end process;
-
--- Wire up write FIFO to channel 0 writes:
--- flags(2) driven by writeFifoOutputValid
--- writeFifoOutputReady driven by consumer_timer
--- LEDs driven by writeFifoOutputData
-writeFifoInputData <=
- h2fData_in;
-writeFifoInputValid <=
- '1' when h2fValid_in = '1' and chanAddr_in = "0000000"
- else '0';
-h2fReady_out <=
- '0' when writeFifoInputReady = '0' and chanAddr_in = "0000000"
- else '1';
-
--- Wire up read FIFO to channel 0 reads:
--- readFifoInputValid driven by producer_timer
--- flags(0) driven by readFifoInputReady
-count_next <=
- std_logic_vector(unsigned(count) + 1) when readFifoInputValid = '1'
- else count;
-readFifoInputData <=
- count;
-f2hValid_out <=
- '0' when readFifoOutputValid = '0' and chanAddr_in = "0000000"
- else '1';
-readFifoOutputReady <=
- '1' when f2hReady_in = '1' and chanAddr_in = "0000000"
- else '0';
-
--- Select values to return for each channel when the host is reading
-with chanAddr_in select f2hData_out <=
- readFifoOutputData when "0000000", -- get from read FIFO
- fifoCount(15 downto 8) when "0000001", -- get depth of write FIFO
- fifoCount(7 downto 0) when "0000010", -- get depth of read FIFO
- x"00" when others;
@@ -1,37 +0,0 @@
--- Infer registers
-process(clk_in)
-begin
- if ( rising_edge(clk_in) ) then
- if ( reset_in = '1' ) then
- reg0 <= (others => '0');
- checksum <= (others => '0');
- else
- reg0 <= reg0_next;
- checksum <= checksum_next;
- end if;
- end if;
-end process;
-
--- Drive register inputs for each channel when the host is writing
-reg0_next <=
- h2fData_in when chanAddr_in = "0000000" and h2fValid_in = '1'
- else reg0;
-checksum_next <=
- std_logic_vector(unsigned(checksum) + unsigned(h2fData_in))
- when chanAddr_in = "0000000" and h2fValid_in = '1'
- else h2fData_in & checksum(7 downto 0)
- when chanAddr_in = "0000001" and h2fValid_in = '1'
- else checksum(15 downto 8) & h2fData_in
- when chanAddr_in = "0000010" and h2fValid_in = '1'
- else checksum;
-
--- Select values to return for each channel when the host is reading
-with chanAddr_in select f2hData_out <=
- sw_in when "0000000",
- checksum(15 downto 8) when "0000001",
- checksum(7 downto 0) when "0000010",
- x"00" when others;
-
--- Assert that there's always data for reading, and always room for writing
-f2hValid_out <= '1';
-h2fReady_out <= '1';

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