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// license:BSD-3-Clause
// copyright-holders:Phil Stroffolino, hap, R. Belmont
/**
* This driver describes Namco's System22 and Super System 22 hardware.
*
* driver provided with thanks to:
* - hap
* - pstroffo@yahoo.com (Phil Stroffolino)
* - R. Belmont
* - trackmaster@gmx.net (Bjorn Sunder)
* - team vivanonno
*
* Input
* - input ports require manual calibration through built-in diagnostics (or canned EEPROM)
*
* Output Devices
* - Prop Cycle fan (outputs noted at the right MCU port)
* - lamps/LEDs on some cabinets
* - time crisis has force feedback for the guns
*
* Link
* - SCI (link) feature is not yet hooked up
*
* CPU Emulation issues
* - slave DSP is not yet used in-game
*
* Notes:
* The "dipswitch" settings are ignored in many games - this isn't a bug. For example, Prop Cycle software
* explicitly clears the chunk of work RAM used to cache the 8 bit dipswitch value immediately after
* populating it. This is apparently done to hide secret debug routines from release versions of games.
*
* Self Test Info:
* Prop Cycle DSP tests:
* MD ROM-PROGRAM (not-yet-working)
* MD-DOWNLOAD - confirms that main CPU can upload custom code to master DSP
* MD-EXTERNAL-RAM - tests private RAM used by master DSP
* C-RAM CHECK BY MD - tests communications RAM, shared by master DSP and main CPU
* PDP LOOP TEST - exercises multi-command DMA transfer
* PDP BLOCK MOVE - exercises DMA block transfer
* POINT RAM - RAM test for "Point RAM" (not directly accessible by any CPU)
* CUSTOM IC STATUS - currently hacked to always report "good"
* SD ROM-PRG - confirms that master DSP can upload custom code to run on slave DSP
* SD EXTERNAL-RAM - tests private RAM used by slave DSP
* DATA FLOW TEST 1 (not-yet-working)
* DATA FLOW TEST 2 (not-yet-working)
* POINT ROM TEST - checksums the "Point ROMs"
*
* Ridge Racer (Japan) tests:
* TEST 1a: MD-EXTERNAL-RAM
* TEST 1b: C-RAM CHECK BY MD
* TEST 2: (not-yet-working)
* TEST 3: SD EXTERNAL-RAM
* TEST 4: DATA FLOW TEST 1 (not-yet-working)
* TEST 5: DATA FLOW TEST 2 (not-yet-working)
* TEST 6: POINT RAM
*
* IO MCU:
* - generates sound/music
* - provides input port management (copying to shared RAM)
* - coinage handling in most games
* - manages external physical devices (i.e. lamps, fans, force feedback)
* - C74 is sound MCU, Mitsubishi M37702 MCU with mask ROM
* - some external subroutines for C74 are also embedded
*
* Master DSP:
* - S22 has two TI320C25 DSP (printed as C71)
* - the master DSP provides display list parsing
*
* Slave DSP:
* - serves as a calculation engine for lighting
*
* Communications RAM
* - seen as 32 bit memory by main 68k CPU
* - seen as 16 bit memory by master DSP (addr 0x8000..0xffff); upper/lower word is selectable
* - not addressable by slave DSP
*
* Point ROMs
* - encodes 3d model data
* - not directly addressable by any CPU
*
* Point RAM
* - same address space as Point ROMs
* - not directly addressable by any CPU
*
* Link Feature:
* - some (typically racing) games may be linked together
* - serial controller is C139 SCI (same as System21).
*
* "Super" System22
* - different memory map
* - different CPU controller register layout
* - sound CPU uses external ROM (i.e. pr1data.8k) instead of internal BIOS (C74)
* - additional 2d sprite layer
* - Point RAM starts at 0xf80000 rather than 0xf00000
* - "PDP" device, for automated block memory transfers (dsp ram, point ram)
*
**********************************************************************************************************
* SYSTEM22 Known Custom Chips
*
* CPU PCB:
*
* C71 TI TMS320C25 DSP
* C71 WEYW40116 (TMS320C25 Main/Sub DSP)
* C71 D72260FN 980 FE-5CA891W
*
* M5M5178AP-25 (CPU 16R, 17R, 19R, 20R) DSP Work RAM (8K x 8bit x 2 x 2)
*
* C74 Mitsubishi M37702 MCU
* C74 159 408600 (OLD SUB)
* C74 159 543100 (NEW SUB)
* C74 159 414600 (OLD I/O)
* C74 159 437600 (NEW I/O)
*
* C195 (Shared SRAM Controller)
* C196 CPP x 6
* C199 (CPU 18K) x 1
* C317 IDC (CPU 15E) x 1 (S21B)
* C337 PFP x 1
* C342 x 1 (S21B)
* C352 (32ch PCM)
* C353 x 1
*
*
* VIDEO PCB:
*
* C304 - 4 chips on SS22 Video PCB
* C305 (Palette)
* C335
* 9C, 10C
* 12D, 12E
* 14C
* C300
* 18B, 18C, 20B, 20C, 22B, 22C
* Cxxx
* 34R, 35R
*
* TI TBP28L22N (256 x 8bit PROM)
* VIDEO 2D, 3D, 4D (RGB Gamma LUT ROM)
*
* RR1.GAM (for Ridge Racer 1/2, Rave Racer)
**********************************************************************************************************
*
*Namco Super System 22 Hardware Overview (last updated 21st
*December 2012 at 7:15pm)
*---------------------------------------
*
*This document covers all the known Namco Super System 22 games, including....
*Air Combat 22 (C) Namco, 1995
*Alpine Racer 1 (C) Namco, 1994
*Alpine Racer 2 (C) Namco, 1996
*Alpine Surfer (C) Namco, 1996
*Aqua Jet (C) Namco, 1996
*Armadillo Racing (C) Namco, 1996 (an undumped prototype/test or early version exists using a different ROM PCB)
*Cyber Cycles (C) Namco, 1995
*Dirt Dash (C) Namco, 1995
*Prop Cycle (C) Namco, 1996
*Time Crisis (C) Namco, 1995
*Tokyo Wars (C) Namco, 1996
*
*The Namco Super System 22 System comprises 4 PCB's plugged into a motherboard. The motherboard contains only
*some slots and connectors. The 4 PCB's are housed in a metal box with a large fan on the side. The fan mostly cools
*the video board as these are known to run hot and commonly fail, especially now the system is many years old.
*
*CPU PCB - There are four known revisions of this PCB. Three of them have an extra connector for an
* auxiliary PCB. One of the others doesn't have that connector but is are otherwise identical.
* All PCBs can be swapped to any game and it will work. However, ALL required IC's must be swapped.
* This includes Program ROM PCB, socketed Keycus IC, socketed DATA ROM and socketed WAVE ROM(s).
* On most games the EEPROM will re-init itself on bootup. On the others, the EEPROM can re-init itself
* to defaults by holding down SERVICE + TEST on power-up. All games are swappable to ANY CPU PCB and will
* run ok (all dumped games have been swapped/tested and work fine)
*DSP PCB - There is only 1 revision of this PCB. All games use the exact same PCB. The DSP PCB can be swapped to
* any other game and works fine (all dumped games tested). Note that some games use different parts of the
* DSP PCB and some do more thorough tests on bootup so an old DSP PCB that works fine in one game may come
* up as faulty in a different SS22 game.
*MROM PCB - These PCB's have many SOP44 ROMs on them and are identical for each game, but the contents of the ROMs
* and the number of ROMs vary per game. (a few of the dumped games have had their surface mounted ROMs
* swapped to other PCBs and worked fine)
*FLASH PCB - Flash ROM board used only for a prototype or early version of Armadillo Racing and contains many TSOP56
* 16M FlashROMs
*VIDEO PCB - There are three known revisions of this PCB. They're mostly identical apart from some component shuffling
* and in the earlier versions (A & B), an Altera FPGA chip is used instead of a Namco custom chip.
* All revisions of the Video PCBs are swappable and fully compatible with any SS22 game. The Altera FPGA runs
* very hot and almost always fails even if heatsinked! Revision C is the most reliable.
*MOTHER PCB- There are probably 3 revisions of this PCB, but only the original revision and (C) are documented here.
* The differences are very minor, just the amount of connectors on the PCB. The Mother PCB is swappable to
* any game as long as the required connectors for that game are present on the PCB. (all dumped games tested
* and worked fine using any MOTHER PCB)
*
*Each game has a 2 or 3 digit letter code assigned to it. Then a number 1 or 2, Then a Rev. A/B/C/D which denotes the
*software revision.
*The 1 denotes a Japanese version. 2 denotes a World version. So far there are no other numbers used other than 1 or 2.
*For World versions, usually only the main program uses a '2', the rest of the ROM labels use the Japanese region code '1'.
*There is one exception so far. The World version of Alpine Racer 2, which uses a World version DATA ROM, and also one
*of the WAVE ROMs is a World version, but one Japanese WAVE ROM is also used.
*See the CPU PCB, Program ROM Daughterboard and MROM PCB texts below for more details on ROM usage.
*
*CPU PCB
*-------
*1st Revision
*SYSTEM SUPER22 CPU PCB 8646960102 (8646970102)
*
*2nd Revision
*SYSTEM SUPER22 CPU(B) PCB 8646962600 (8646972600)
*
*3rd Revision
*SYSTEM SUPER22 CPU(B) PCB 8646962600 (8646972601) <-- very minor?
*
*4th Revision
*SYSTEM SUPER22 CPU(B) PCB 8646962601 (8646972601) <-- very minor?
*|--------------------------------------------------------------|
*| J6 JC410 3771 |
*| N341256(x4) DSW(4)|
*| |-------| |--|
*| |MC68EC | | |
*| |020FG25| | |
*| *1 |-------| | |
*| DSW(8) SS22C2 |------| | |
*| | C383 | | |
*| CAT28C64 KEYCUS SS22C1 | | | |
*| |------| | |
*| |-------| | |
*| N341256 | | |------| | |
*| *3 N341256 | C405 | | 139 | |--|
*| | | CY7C182 | | |
*| *2 |-------| |------| |
*| |--|
*| 40.000MHz 137 | |
*| | |
*| DATA.8K JP1 49.152MHz | |
*| |------| |-------| 4558 | |
*| | C352 | JP2 |M37710 | | |
*| | | |S4BFP | | |
*| |------| |-------| | |
*|LED(x8) | |
*| J11 SS22C4 MB87078 | |
*| WAVEA.2L 4558 |--|
*| JP3 |
*| WAVEB.1L LC78815M LC78815M |
*|--------------------------------------------------------------|
*(logic chips omitted from the PCB layout)
*
*Notes:
* J6 : Custom Namco connector for plug-in program ROM PCB
* J11 : Custom Namco connector for optional plug-in WAVE ROM PCB (holds some SOP44 MASKROMs)
* JC410 : Custom Namco connector for Optional plug-in Auxiliary PCB (e.g. Gun Control PCB used in Time Crisis
* etc)
* The connector is populated only on the 2nd revision CPU (B) PCB 8646962600 (8646972600)
* and 3rd Revision CPU (B) PCB 8646962600 (8646972601)
* JP1 : Jumper for configuration of M37710 (tied to pins 26 & 27 of M37710). Set to 1-2
* JP2 : Jumper for configuration of DATA ROM. Set to 1-2 (labelled '4M'), alt. setting 2-3 (labelled '1M/2M')
* JP3 : Jumper for configuration of WAVE ROM. Set to 2-3 (labelled '42P32M'), alt. setting 1-2
* (labelled 'OTHER'). 'OTHER' is used when the WAVE ROMs are 16MBit. If the WAVE ROMs are 32MBit
* (i.e. JP3 = 2-3), they're programmed in BYTE mode.
* M37710 : Mitsubishi M37710 CPU. Used on SS22 as the sound CPU. Does not have internal ROM (QFP80)
* MB87078 : Fujitsu MB87078 electronic volume control IC (SOIC24)
* 4558 : Op Amp (SOIC8)
* LC78815M : Sanyo LC78815M 2-channel 16-bit D/A converter (x2, SOIC20)
* 3771 : Fujitsu MB3771 master reset IC (SOIC8)
* DSW(4) : 4 position DIP Switch (1,2,3 are ON, 4 is OFF)
* DSW(8) : 8 position DIP Switch (All OFF)
* N341256 : NKK N341256 32k x8 SRAM (x6, SOJ28)
* CY7C182 : Cypress 8k x9 SRAM (SOJ28)
* MC68EC020FG25: Main CPU, Motorola 68EC020FG25 (QFP100), running at 24.576MHz. Clock source is Namco
* custom clock divider 137. 68EC020 clock = Master Clock of 49.152MHz / 2
* C383 : Namco custom C383 (QFP100)
* 139 : Namco custom 139 Serial Controller Interface IC (QFP64). NOTE! On some PCB's this chip
* has been replaced by a custom C422 chip, though the PCB number is the same. Which means probably
* the function of this chip matches 139
* 137 : Namco custom clock divider IC (DIP28)
* C405 : Namco custom C405 (QFP176)
* C352 : Namco custom C352 PCM sound chip (QFP100), clock is 24.576MHz (49.152/2), from pin 6 of C137
* SS22C1 : PALCE 22V10H (PLCC28, labelled 'SS22C1')
* SS22C2 : PALCE 22V10H (PLCC28, labelled 'SS22C2')
* SS22C4 : PALCE 22V10H (PLCC28, labelled 'SS22C4')
* CAT28C64 : Catalyst Semiconductor Inc. CAT28C64 8k x8 EEPROM (DIP28)
* LEDS : 8 LEDs of various colors flash (in various pretty patterns) when the CPU PCB is active.
* KEYCUS : Namco custom (DIP32)
* Air Combat 22 = none
* Alpine Racer 1 = C391
* Alpine Racer 2 = C434
* Alpine Surfer = C425
* Aqua Jet = C429
* Armadillo Racing = C433
* Cyber Cycles = C389
* Dirt Dash = C418
* Prop Cycle = C428
* Time Crisis = C419
* Tokyo Wars = C424
*
* *1 : Unpopulated position for PAL16V8 (PLCC20)
* *2 : Unpopulated position for Fujitsu MB86601 (QFP100)
* *3 : Unpopulated position for 32MHz OSC
* DATA.8K : ST Microelectronics M27C4096 256k x16 EPROM (DIP40, labelled with the gamecode + 'DATA')
* Game EPROM label
* -------------------------------
* Air Combat 22 'ACS1 DATA'
* Alpine Racer 1 'AR1 DATA B'
* Alpine Racer 2 'ARS2 DATA'
* Alpine Surfer 'AF1 DATA'
* Aqua Jet 'AJ1 DATA'
* Armadillo Racing 'AM1 DATA'
* Cyber Cycles 'CB1 DATA B'
* Dirt Dash 'DT1 DATA A'
* Prop Cycle 'PR1 DATA'
* Time Crisis 'TS1 DATA'
* Tokyo Wars 'TW1 DATA'
*
* WAVEA.2L \
* WAVEB.1L / : 16M/32M WAVE MASKROMs. If 32MBit DIP42, they're programmed in BYTE mode (DIP42/SOP44)
* Game Wave A Wave B Type
* ----------------------------------------------------------------------------
* Air Combat 22 'ACS1 WAVE0', 'ACS1 WAVE1' , both SOP44 32M MASKROMs
* Alpine Racer 1 'AR1 WAVEA' , , DIP42 16M MASKROM
* Alpine Racer 2 'ARS1 WAVEA', 'ARS2 WAVE B', both DIP42 32M MASKROMs
* Alpine Surfer 'AF1 WAVEA' , , DIP42 32M MASKROM
* Aqua Jet 'AJ1 WAVEA' , 'AJ1 WAVEB' , both DIP42 32M MASKROMs
* Armadillo Racing 'AM1 WAVEA' , 'AM1 WAVEB' , both DIP42 32M MASKROMs. Prototype version uses TSOP56, mounted on a DIP48 adapter board
* Cyber Cycles 'CB1 WAVEA' , 'CB1 WAVEB' , WAVE A DIP42 32M MASKROM, WAVE B DIP42 16M MASKROM
* Dirt Dash 'DT1 WAVEA' , 'DT1 WAVEB' , both DIP42 32M MASKROMs
* Prop Cycle 'PR1 WAVE A', 'PR1 WAVE B' , both DIP42 32M MASKROM
* Time Crisis 'TS1 WAVE A', 'TS1 WAVE B' , WAVE A DIP42 32M MASKROM, WAVE B DIP42 16M MASKROM
* Tokyo Wars 'TW1 WAVE A', , DIP42 32M MASKROM
*
*
*PROGRAM ROM Daughterboard PCB
*-----------------------------
*This PCB holds the main program ROMs. There is a small sticker on each PCB stating the game code and software revision.
*The actual ROMs are not marked with any codes except the manufacturer's part number.
*There are 4 known types of program daughterboards used on SS22 games (so far). The most common is the first type.
*The PCB is very small (approx 2" x 3") containing one custom connector and some FlashROMs, and a PAL (in some cases).
*The ones that contain a PAL are approx 3" x 3".
*
*Type 1
*SYSTEM SUPER22 MPM(F) PCB 8646961600 (8646971600)
*|-------------------------|
*| |
*| |
*| ROM1 ROM2 ROM3 ROM4 |
*| |
*| |
*| |-------------------| |
*| |-------------------| |
*|-------------------------|
*Notes:
* ROMx: Intel E28F008SA 8MBit FlashROM (x4, TSOP40)
*
* This PCB is used on:
* Game Software revision
* -------------------------------
* Air Combat 22 'ACS1 Ver.B'
* Alpine Racer 'AR2 Ver.C'
* Alpine Racer 'AR2 Ver.D'
* Aqua Jet 'AJ2 Ver.B'
* Armadillo Racing 'AM1 Ver.A'
* Cyber Cycles 'CB2 Ver.C'
* Prop Cycle 'PR2 Ver.A'
* Time Crisis 'TS2 Ver.B'
* Tokyo Wars 'TW2 Ver.A'
*
*Type 2
*SYSTEM SUPER22 MPM(F16) PCB 8646962500 (8646972500)
*|-------------------------|
*| |
*| |
*| ROM1 ROM2 |
*| |
*| |
*| |
*| |-------------------| |
*| |-------------------| |
*|-------------------------|
*Notes:
* ROMx: Intel E28F016SA 16MBit FlashROMs (x2, TSOP56)
*
* This PCB is used on:
* Game Software revision
* -------------------------------
* Time Crisis 'TS2 Ver.A'
* Dirt Dash 'DT2 Ver.A'
*
*Type 3
*SYSTEM SUPER22 MPM(F16X4) PCB 8646962901 (8646972901)
*|-------------------------|
*|SS22P1B |
*| |
*| IC4_LM IC5_UU |
*| |
*| |
*| IC2_LL IC3_UM |
*| |
*| |
*| |-------------------| |
*| |-------------------| |
*|-------------------------|
*Notes:
* ICx* : Intel E28F016SA 16MBit FlashROMs (x4, TSOP56)
* SS22P1B: PALCE16V8H (PLCC20, labelled 'SS22P1B')
*
* This PCB is used on:
* Game Software revision
* -------------------------------
* Alpine Racer 2 'ARS2 Ver.B'
*
*Type 4
*SYSTEM SUPER22 MPM(F16X4F) PCB 8646963500 (8646973500)
*SYSTEM SUPER22 MPM(F16X4F) PCB 8646963501 (8646973501) <-- very minor?
*|-------------------------|
*|SS22P1B |
*| |
*| |
*| IC2_LL IC4_UM |
*| |
*| IC3_LM IC5_UU |
*| |
*| |
*| |-------------------| |
*| |-------------------| |
*|-------------------------|
*Notes:
* ICx : Fujitsu 29F016 16MBit FlashROMs (x4, TSOP48)
* SS22P1B: PALCE16V8H (PLCC20, labelled 'SS22P1B')
* There is a small mod on this PAL as follows....
* - Pin 8 is lifted and the pad on the PCB at pin 8
* is tied to pin 16 of the PAL (no other pins are lifted)
* - The lifted pin 8 is tied to the MPM PCB connector on pin 1
* That pin traces to pin 6 (OUTPUT Y) of a 74F08 at 15F on the CPU board
* Pins 4 (INPUT A) & 5 (INPUT B) of the 74F08 at 15F trace to Namco custom
* IC C383 pins 53 (A INPUT) & 52 (B INPUT)
*
* This PCB is used on:
* Game Software revision
* --------------------------------
* Alpine Surfer 'AF2 Ver.A' note: with PAL modification and using 8646963500 PCB
* Alpine Racer 2 'ARS2 Ver.A' note: without PAL modification and using 8646963501 PCB
*
*
*Auxillary PCB (connector JC410 on the CPU PCB is used only for Time Crisis)
*-------------
*V159 GUN POINT PCB 244790102 (2447970102)
*|---------------------------------|
*| |
*| 25.175MHz |
*| |
*| |
*| |
*| |
*| |
*| |
*| J2|
*| |
*| |
*| |
*| |
*| |
*| |
*| J1 |
*|---------------------------------|
*Notes:
* There isn't much on this PCB other than 2 connectors and an oscillator plus a large amount of logic chips.
* J1 : Connector joining Gun PCB to a connector on the metal box (which joins to the gun interface PCB in the
* cab which supplies 24V for the solenoid in the guns)
* J2 : Connector joining to the CPU PCB (to JC410)
*
*
*DSP PCB
*-------
*SYSTEM SUPER22 DSP PCB 8646960302 (8646970302)
* |--------------------------------------------------------------|
* | N341256 |-------| SS22D1 N341256 |-------| |
* | N341256 | | N341256 | | |
* | |---------| | C71 | | C405 | |--|
*|--|| | | | | | | |
*| || C396 | |-------| |-------| | |
*| || | | |
*|J || | N341256 |-------| | |
*|D ||---------| N341256 | | | |
*|3 | |-------| N341256 | C405 | | |
*| | | | | | | |
*| | | C71 | |---------| |-------| | |
*|--| | | | | |------| | |
* | |-------| | 342 | | C379 | |--|
* | |------| | | | | |
* | | C199 | | | |------| N341256 |
* | | | |---------| N341256 |--|
* | |------| | |
* | |-----| SS22D5 SS22D4B 40MHz |---------| | |
* | |C353 | | | | |
* | |-----| | C300 | | |
* |LED(x8) SS22D2 SS22D3 | | | |
* | |-----| | | | |
* | | 402 | |---------| |---------| | |
* | |-----| | | | |
* | | C403 | KM681000 KM681000 KM681000 | |
* | |-----| | | |--|
* | | 402 | | | KM681000 KM681000 KM681000 |
* | |-----| |---------| |
* |--------------------------------------------------------------|
*(logic chips omitted from the PCB layout)
*
*Notes:
* JD3 : Custom Namco connector joining this PCB to the MROM PCB with a special flat cable known as a
* 'DHD harness'
* N341256 : NKK N341256 32k x8 SRAM (x9, SOJ28)
* KM681000 : Samsung Electronics KM681000 128k x8 SRAM (x6, SOP32)
* 342 : Namco custom 342 (QFP160)
* 402 : Namco custom 402 (x2, TQFP144)
* C71 : Namco custom C71, actually a Texas Instruments 320C25 DSP (x2, PLCC68)
* C199 : Namco custom C199 (QFP100)
* C300 : Namco custom C300 (QFP160)
* C353 : Namco custom C353 (QFP120)
* C379 : Namco custom C379 (QFP64)
* C396 : Namco custom C396 (QFP160)
* C403 : Namco custom C403 (QFP136)
* C405 : Namco custom C396 (x2, QFP176)
* SS22D1 : PALCE 20V8H (PLCC28, labelled 'SS22D1')
* SS22D2 : PALCE 16V8H (PLCC20, labelled 'SS22D2')
* SS22D3 : PALCE 16V8H (PLCC20, labelled 'SS22D3')
* SS22D4B : PALCE 16V8H (PLCC20, labelled 'SS22D4B')
* SS22D5 : PALCE 16V8H (PLCC20, labelled 'SS22D5')
* LEDS : 8 red LEDs flash (in various pretty patterns) when the DSP PCB is active.
*
*
*ROM PCB (type 1)
*-------
*SYSTEM SUPER22 MROM PCB 8646960400 (8646970400)
* |--------------------------------------------------------------|
* | SS22M3 TC551001(x3) |
* | JP13 CG7.19D CG5.19B |
* | PTR-L0.18K PTR-M0.18J PTR-U0.18F |
*|--| CG6.18D CG4.18B |
*| | PTR-L1.16K PTR-M1.16J PTR-U1.16F CG6.18A|
*| | CG5.16D CG3.16B |
*|J | PTR-L2.15K PTR-M2.15J PTR-U2.15F CG7.15A|
*|R | CG4.14D CG2.14B |
*|4 | PTR-L3.14K PTR-M3.14J PTR-U3.14F JP1 |
*| | SCG0.12L SCG0.12F JP4 CG3.13D CG1.13B JP2 |
*| | JP5 JP3 |
*|--| SCG7.10J JP6 CG2.12D CG0.12B |
* | SCG1.10L SCG1.10F SS22M1 |
* | CG1.10D SS22M2 |
* | |
* | SCG2.8L JP10 SCG2.8F CG0.8D |--|
*|--| JP11 | |
*| | JP12 | |
*| | SCG3.7L SCG3.7F SS22M2 CCR-L.7B | |
*|J | | |
*|R | CCR-H.5B | |
*|3 | SCG4.5L SCG4.5F | |
*| | JP7 | |
*| | JP8 | |
*|--| SCG5.3L JP9 SCG5.3F CCR-L.3D | |
* | |--|
* | SCG7.1J CCR-H.1D |
* | SCG6.1L SCG6.1F |
* |--------------------------------------------------------------|
*(logic chips omitted from the PCB layout)
*
*Notes:
* Namco SS22 MROM PCBs have 2 identical sets of CG*, SCG* and CCR-L/CCR-H ROMs on the PCB.
* The Japanese region code '1' is appended to all game codes on all MROMs.
*
* JR3, JR4 : Custom Namco connector joining this PCB to the VIDEO & DSP PCBs with a special flat cable known
* as a 'DHD harness'
* SS22M1 : PALCE 16V8H (PLCC20, labelled 'SS22M1')
* SS22M2 : PALCE 20V8H (x2, PLCC28, labelled 'SS22M2')
* SS22M3 : PALCE 16V8H (PLCC20, labelled 'SS22M3')
* TC551001 : Toshiba TC551001 128k x8 SRAM (SOP32)
* JP1, JP2, JP3: Jumpers to configure CG* ROMs. Hardwired to '16M' on the PCB. Alt. setting '32M'
* JP4, JP5, JP6: Jumpers to configure CG* ROMs. Hardwired to '16M' on the PCB. Alt. setting '32M'
* JP7, JP8, JP9: Jumpers to configure SCG* ROMs. Hardwired to '16M' on the PCB. Alt. setting '32M'
* JP10, JP11, JP12: Jumpers to configure SCG* ROMs. Hardwired to '16M' on the PCB. Alt. setting '32M'
* JP13 : Jumper to configure PTR* ROMs. Hardwired to '4M' on the PCB. Alt. setting '8M'
*
*Game ROMs populated
*---------------------------------------------------------
*Air Combat 22 ACS1CCRH.5B, ACS1CCRH.1D 4M SOP32
* ACS1CCRL.7B, ACS1CCRL.3D 16M SOP44
* ACS1CG0.12B, ACS1CG0.8D "
* ACS1CG1.13B, ACS1CG1.10D "
* ACS1CG2.14B, ACS1CG2.12D "
* ACS1CG3.16B, ACS1CG3.13D "
* ACS1CG4.18B, ACS1CG4.14D "
* ACS1CG5.19B, ACS1CG5.16D "
* ACS1CG6.18A, ACS1CG6.18D "
* ACS1CG7.15A, ACS1CG7.19D "
* ACS1SCG0.12F,ACS1SCG0.12L "
* ACS1SCG1.10F,ACS1SCG1.10L "
* ACS1PTRU0.18F 4M SOP32
* ACS1PTRU1.16F "
* ACS1PTRU2.15F "
* ACS1PTRU3.14F "
* ACS1PTRM0.18J "
* ACS1PTRM1.16J "
* ACS1PTRM2.15J "
* ACS1PTRM3.14J "
* ACS1PTRL0.18K "
* ACS1PTRL1.16K "
* ACS1PTRL2.15K "
* ACS1PTRL3.14K "
*
*Alpine Racer 1 AR1CCRH.5B, AR1CCRH.1D 4M SOP32
* AR1CCRL.7B, AR1CCRL.3D 16M SOP44
* AR1CG0.12B, AR1CG0.8D "
* AR1CG1.13B, AR1CG1.10D "
* AR1CG2.14B, AR1CG2.12D "
* AR1CG3.16B, AR1CG3.13D "
* AR1CG4.18B, AR1CG4.14D "
* AR1CG5.19B, AR1CG5.16D "
* AR1CG6.18A, AR1CG6.18D "
* AR1CG7.15A, AR1CG7.19D "
* AR1SCG0.12F,AR1SCG0.12L "
* AR1SCG1.10F,AR1SCG1.10L "
* AR1PTRU0.18F 4M SOP32
* AR1PTRU1.16F "
* AR1PTRU2.15F "
* AR1PTRU3.14F "
* AR1PTRM0.18J "
* AR1PTRM1.16J "
* AR1PTRM2.15J "
* AR1PTRM3.14J "
* AR1PTRL0.18K "
* AR1PTRL1.16K "
* AR1PTRL2.15K "
* AR1PTRL3.14K "
*
*Alpine Racer 2 ARS1CCRH.5B, ARS1CCRH.1D 4M SOP32
* ARS1CCRL.7B, ARS1CCRL.3D 16M SOP44
* ARS1CG0.12B, ARS1CG0.8D "
* ARS1CG1.13B, ARS1CG1.10D "
* ARS1CG2.14B, ARS1CG2.12D "
* ARS1CG3.16B, ARS1CG3.13D "
* ARS1CG4.18B, ARS1CG4.14D "
* ARS1CG5.19B, ARS1CG5.16D "
* ARS1SCG0.12F,ARS1SCG0.12L "
* ARS1PTRU0.18F 4M SOP32
* ARS1PTRU1.16F "
* ARS1PTRU2.15F "
* ARS1PTRU3.14F "
* ARS1PTRM0.18J "
* ARS1PTRM1.16J "
* ARS1PTRM2.15J "
* ARS1PTRM3.14J "
* ARS1PTRL0.18K "
* ARS1PTRL1.16K "
* ARS1PTRL2.15K "
* ARS1PTRL3.14K "
*
*Alpine Surfer AF1CCRH.5B, AF1CCRH.1D 4M SOP32
* AF1CCRL.7B, AF1CCRL.3D 16M SOP44
* AF1CG0.12B, AF1CG0.8D "
* AF1CG1.13B, AF1CG1.10D "
* AF1CG2.14B, AF1CG2.12D "
* AF1CG3.16B, AF1CG3.13D "
* AF1CG4.18B, AF1CG4.14D "
* AF1SCG0B.12F,AF1SCG0B.12L "
* AF1PTRU0.18F 4M SOP32
* AF1PTRU1.16F "
* AF1PTRM0.18J "
* AF1PTRM1.16J "
* AF1PTRL0.18K "
* AF1PTRL1.16K "
*
*Aqua Jet AJ1CCRH.5B, AJ1CCRH.1D 4M SOP32
* AJ1CCRL.7B, AJ1CCRL.3D 16M SOP44
* AJ1CG0.12B, AJ1CG0.8D "
* AJ1CG1.13B, AJ1CG1.10D "
* AJ1CG2.14B, AJ1CG2.12D "
* AJ1CG3.16B, AJ1CG3.13D "
* AJ1CG4.18B, AJ1CG4.14D "
* AJ1CG5.19B, AJ1CG5.16D "
* AJ1CG6.18A, AJ1CG6.18D "
* AJ1CG7.15A, AJ1CG7.19D "
* AJ1SCG0.12F,AJ1SCG0.12L "
* AJ1SCG1.10F,AJ1SCG1.10L "
* AJ1SCG2.8F, AJ1SCG2.8L "
* AJ1PTRU0.18F 4M SOP32
* AJ1PTRU1.16F "
* AJ1PTRU2.15F "
* AJ1PTRU3.14F "
* AJ1PTRM0.18J "
* AJ1PTRM1.16J "
* AJ1PTRM2.15J "
* AJ1PTRM3.14J "
* AJ1PTRL0.18K "
* AJ1PTRL1.16K "
* AJ1PTRL2.15K "
* AJ1PTRL3.14K "
*
*Armadillo Racing AM1CCRH.5B, AM1CCRH.1D 4M SOP32
* AM1CCRL.7B, AM1CCRL.3D 16M SOP44
* AM1CG0.12B, AM1CG0.8D "
* AM1CG1.13B, AM1CG1.10D "
* AM1CG2.14B, AM1CG2.12D "
* AM1CG3.16B, AM1CG3.13D "
* AM1CG4.18B, AM1CG4.14D "
* AM1CG5.19B, AM1CG5.16D "
* AM1CG6.18A, AM1CG6.18D "
* AM1CG7.15A, AM1CG7.19D "
* AM1SCG0.12F,AM1SCG0.12L "
* AM1SCG1.10F,AM1SCG1.10L "
* AM1PTRU0.18F 4M SOP32
* AM1PTRU1.16F "
* AM1PTRU2.15F "
* AM1PTRU3.14F "
* AM1PTRM0.18J "
* AM1PTRM1.16J "
* AM1PTRM2.15J "
* AM1PTRM3.14J "
* AM1PTRL0.18K "
* AM1PTRL1.16K "
* AM1PTRL2.15K "
* AM1PTRL3.14K "
*
*Cyber Cycles CB1CCRH.5B, CB1CCRH.1D 4M SOP32
* CB1CCRL.7B, CB1CCRL.3D 16M SOP44
* CB1CG0.12B, CB1CG0.8D "
* CB1CG1.13B, CB1CG1.10D "
* CB1CG2.14B, CB1CG2.12D "
* CB1CG3.16B, CB1CG3.13D "
* CB1CG4.18B, CB1CG4.14D "
* CB1CG5.19B, CB1CG5.16D "
* CB1CG6.18A, CB1CG6.18D "
* CB1SCG0.12F,CB1SCG0.12L "
* CB1SCG1.10F,CB1SCG1.10L "
* CB1PTRU0.18F 4M SOP32
* CB1PTRU1.16F "
* CB1PTRU2.15F "
* CB1PTRU3.14F "
* CB1PTRM0.18J "
* CB1PTRM1.16J "
* CB1PTRM2.15J "
* CB1PTRM3.14J "
* CB1PTRL0.18K "
* CB1PTRL1.16K "
* CB1PTRL2.15K "
* CB1PTRL3.14K "
*
*Dirt Dash DT1CCRH.5B, DT1CCRH.1D 4M SOP32
* DT1CCRL.7B, DT1CCRL.3D 16M SOP44
* DT1CG0.12B, DT1CG0.8D "
* DT1CG1.13B, DT1CG1.10D "
* DT1CG2.14B, DT1CG2.12D "
* DT1CG3.16B, DT1CG3.13D "
* DT1CG4.18B, DT1CG4.14D "
* DT1CG5.19B, DT1CG5.16D "
* DT1CG6.18A, DT1CG6.18D "
* DT1CG7.15A, DT1CG7.19D "
* DT1SCG0.12F,DT1SCG0.12L "
* DT1SCG1.10F,DT1SCG1.10L "
* DT1PTRU0.18F 4M SOP32
* DT1PTRU1.16F "
* DT1PTRU2.15F "
* DT1PTRU3.14F "
* DT1PTRM0.18J "
* DT1PTRM1.16J "
* DT1PTRM2.15J "
* DT1PTRM3.14J "
* DT1PTRL0.18K "
* DT1PTRL1.16K "
* DT1PTRL2.15K "
* DT1PTRL3.14K "
*
*Prop Cycle PR1CCRH.5B, PR1CCRH.1D 4M SOP32
* PR1CCRL.7B, PR1CCRL.3D 16M SOP44
* PR1CG0.12B, PR1CG0.8D "
* PR1CG1.13B, PR1CG1.10D "
* PR1CG2.14B, PR1CG2.12D "
* PR1CG3.16B, PR1CG3.13D "
* PR1CG4.18B, PR1CG4.14D "
* PR1CG5.19B, PR1CG5.16D "
* PR1CG6.18A, PR1CG6.18D "
* PR1CG7.15A, PR1CG7.19D "
* PR1SCG0.12F,PR1SCG0.12L "
* PR1SCG1.10F,PR1SCG1.10L "
* PR1PTRU0.18F 4M SOP32
* PR1PTRU1.16F "
* PR1PTRU2.15F "
* PR1PTRM0.18J "
* PR1PTRM1.16J "
* PR1PTRM2.15J "
* PR1PTRL0.18K "
* PR1PTRL1.16K "
* PR1PTRL2.15K "
*
*Time Crisis TS1CCRH.5B, TS1CCRH.1D 4M SOP32
* TS1CCRL.7B, TS1CCRL.3D 16M SOP44
* TS1CG0.12B, TS1CG0.8D "
* TS1CG1.13B, TS1CG1.10D "
* TS1CG2.14B, TS1CG2.12D "
* TS1CG3.16B, TS1CG3.13D "
* TS1CG4.18B, TS1CG4.14D "
* TS1CG5.19B, TS1CG5.16D "
* TS1CG6.18A, TS1CG6.18D "
* TS1CG7.15A, TS1CG7.19D "
* TS1SCG0.12F,TS1SCG0.12L "
* TS1SCG1.10F,TS1SCG1.10L "
* TS1SCG2.8F, TS1SCG2.8L "
* TS1SCG3.7F, TS1SCG3.7L "
* TS1SCG4.5F, TS1SCG4.5L "
* TS1SCG5.3F, TS1SCG5.3L "
* TS1PTRU0.18F 4M SOP32
* TS1PTRU1.16F "
* TS1PTRU2.15F "
* TS1PTRM0.18J "
* TS1PTRM1.16J "
* TS1PTRM2.15J "
* TS1PTRL0.18K "
* TS1PTRL1.16K "
* TS1PTRL2.15K "
*
*Tokyo Wars TW1CCRH.5B, TW1CCRH.1D 4M SOP32
* TW1CCRL.7B, TW1CCRL.3D 16M SOP44
* TW1CG0.12B, TW1CG0.8D "
* TW1CG1.13B, TW1CG1.10D "
* TW1CG2.14B, TW1CG2.12D "
* TW1CG3.16B, TW1CG3.13D "
* TW1CG4.18B, TW1CG4.14D "
* TW1CG5.19B, TW1CG5.16D "
* TW1CG6.18A, TW1CG6.18D "
* TW1CG7.15A, TW1CG7.19D "
* TW1SCG0.12F,TW1SCG0.12L "
* TW1SCG1.10F,TW1SCG1.10L "
* TW1SCG2.8F, TW1SCG2.8L "
* TW1SCG3.7F, TW1SCG3.7L "
* TW1PTRU0.18F 4M SOP32
* TW1PTRU1.16F "
* TW1PTRU2.15F "
* TW1PTRU3.14F "
* TW1PTRM0.18J "
* TW1PTRM1.16J "
* TW1PTRM2.15J "
* TW1PTRM3.14J "
* TW1PTRL0.18K "
* TW1PTRL1.16K "
* TW1PTRL2.15K "
* TW1PTRL3.14K "
*
*
*ROM PCB (type 2)
*-------
*SS22DS FLASH PCB 8650961300 (8650971300)
* |--------------------------------------------------------------|
* | F13M F13L F12J F12E |------| |
* | |ALTERA| |
* | F12M F12L |EPMXXXX |
*|--| F11J F11E |------| |
*| | HM628128 F11L |
*| | HM628128 DSF4 |
*|J | HM628128 F9L F9J F9E |
*|R | |
*|4 | DSF5A |
*| | F8J F8E |
*| | |
*|--| SS22DSF3 |
* | F7L F7M F7J F7E |
* | |
* | |
* | F6J F6E SS22DSF3|--|
*|--| | |
*| | | |
*| | F5L F5M F5J F5E | |
*|J | | |
*|R | | |
*|3 | F4J F4E | |
*| | | |
*| | F3L F3M | |
*|--| | |
* | SS22DSF2 F2J F2E |--|
* | |
* | SS22DSF2 F1L F1M F1J F1E |
* |--------------------------------------------------------------|
*(logic chips omitted from the PCB layout)
*
*Notes:
* Namco SS22 FLASH PCBs have 2 identical sets of CG*, SCG* and CCR-L/CCR-H ROMs on the PCB.
*
* JR3, JR4 : Custom Namco connector joining this PCB to the VIDEO & DSP PCBs with a special flat cable known
* as a 'DHD harness'
* EPMXXXX : Altera EPM??? (PLCC84, unknown chip model, possibly EPM7064, sticker on top of it blocking ID markings)
* DSF5A : PALCE 16V8H (PLCC20, labelled 'DSF5A')
* DSF4 : PALCE 16V8H (PLCC20, labelled 'DSF4')
* SS22DSF3 : EPM7032 (x2, PLCC44, labelled 'SS22DSF3')
* SS22DSF2 : EPM7032 (x2, PLCC44, labelled 'SS22DSF2')
* HM628128 : Hitachi HM628128 128k x8 SRAM (TSOP32)
*
*Game ROMs populated (All Intel E28F016SA TSOP56 16M FlashROMs)
*-----------------------------------------------------------------
*Armadillo Racing F1E, F1J, F2E, F2J - CCRL/CCRH
*ROMs (prototype or
*early test version)F4E, F4J, F5E, F5J, F6E, F6J, \
* F7E, F7J, F8E, F8J, F9E, F9J, \ CGx ROMs
* F11E, F11J, F12E, F12J /
*
* F1L, F1M, F3L, F3M, F5L, F5M, \
* F7L, F7M / SCGx ROMs
*
* F9L, F11L, F12L, F13L, \
* F12M, F13M / PTR ROMs
*
*
*VIDEO PCB
*---------
*1st Revision
*SYSTEM SUPER22 VIDEO 8646960204 (8646970204)
*
*2nd Revision
*SYSTEM SUPER22 VIDEO(B) 8646961200 (8646971200)
*
*3rd Revision (PCB layout shown below)
*SYSTEM SUPER22 VIDEO(C) 8646962700 (8646972700)
* |--------------------------------------------------------------|
* | |
* | HM534251BJ-8(x22) |
* | |-----| |--|
* | |---------| |---------| |---------| |---------| |C401 | | |
* | | | | | | | | | |-----| | |
* | | 304 | | 304 | | 304 | | 304 | | |
* | | | | | | | | | |-----| | |
* | | | | | | | | | |C400 | | |
* | |---------| |---------| |---------| |---------| |-----| | |
* | N341256 |-----| |-----| |-----| |-----| | |
* | N341256 |C407 | |C401 | |C401 | |C401 | |---------| | |
* | |-----| |-----| |-----| |-----| | | | |
* | |---------| | C399 | |--|
* | | | |-----| |-----| |-----| | | |
* | | C387 | |C400 | |C400 | |C400 | | | |
* | | | |-----| |-----| |-----| |---------| |--|
*|--| | | |-----| N341256 | |
*| | |---------| |C406 | |-----| N341256 | |
*| | |-----| |-----| |C381 | | |
*|J | |C381 | |---------| |-----| | |
*|V | |-----| N341256 | | LC321664| |
*|3 | 51.2MHz N341256 | C404 | |---------| | |
*| | |---------| |---------| | | | | | |
*| | | | | | | | | C361 | | |
*|--| | C374 | | C395 | |---------| | | | |
* | | | | | N341256 | | |--|
* | | | | | N341256 |---------| |
* | |---------| |---------| N341256 CXD1178Q |
* |--------------------------------------------------------------|
*(logic chips omitted from the PCB layout)
*
*Notes:
* JV3 : Custom Namco connector joining this PCB to the MROM PCB with a special flat cable known
* as a 'DHD harness'
* N341256 : NKK N341256 32k x8 SRAM (x9, SOJ28)
* HM534251BJ-8 : Hitachi HM534251BJ-8 256k x4 FASTPAGE DRAM (x22, SOJ28)
* LC321664 : Sanyo LC321664 64k x16 DRAM (SOJ40)
* CXD1178Q : Sony CXD1178Q 8-bit RGB 3-channel D/A converter (QFP48)
* 304 : Namco custom 304 (x4, QFP120)
* C361 : Namco custom C361 (QFP120)
* C374 : Namco custom C374 (QFP160)
* C381 : Namco custom C381 (x2, QFP144)
* C387 : Namco custom C387 (QFP160)
* C395 : Namco custom C395 (QFP168)
* C399 : Namco custom C399 (QFP160)
* C400 : Namco custom C400 (x4, QFP100)
* - x3 on 1st Revision
* C401 : Namco custom C401 (x4, QFP64)
* - x5 on 1st Revision
* C404 : Namco custom C404 (QFP208)
* C406 : Namco custom C406 (TQFP120)
* C407 : Namco custom C407 (QFP64) NOTE! On Revision A & B, this position is populated by an
* Altera EPM7064 PLCC84 FPGA labelled 'SS22V1B'
* The Altera chip runs very hot and fails quite often.
* Even if a heatsink is added to the chip it still fails.
* The failure of this chip is the primary cause of
* video faults on Namco Super System 22 PCBs.
* (Second reason for video faults is generally attributed
* to failure of RAM on this PCB and/or the DSP PCB)
*
*
*Motherboard PCB
*---------------
*1st Revision
*SYSTEM SUPER22 MOTHER PCB 8646960602 (8646970602)
*
*2nd Revision
*SYSTEM SUPER22 MOTHER(B) PCB (number not known)
*
*3rd Revision
*SYSTEM SUPER22 MOTHER(C) PCB 8646960602 (8646970602)
*|------------------------------------------------------------------|
*| J1 J2 J4 J6 J8 |
*| J10 J5 IC2 J7 |
*| J3 IC3 IC1 J9 |
*| |
*| JC2 |---------------------| |---------------------|JC1 |
*| |---------------------| |---------------------| |
*| |
*| JD2 |---------------------| |---------------------|JD1 |
*| |---------------------| |---------------------| |
*| |
*| |---------------------|JR1 |
*| |---------------------| |
*| |
*| JV2 |---------------------| |---------------------|JV1 |
*| |---------------------| |---------------------| |
*|------------------------------------------------------------------|
*Notes:
* IC1 : LB1233 (DIP8)
* IC2, IC3: LB1235 (DIP8)
*
* JC1, JC2: Connectors to plug in CPU PCB
* JD1, JD2: Connectors to plug in DSP PCB
* JR1 : Connector to plug in MROM PCB
* JV1, JV2: Connectors to plug in VIDEO PCB
*
* J1 : 9 pin power input socket Pin Use
* -----------
* 1 +5V
* 2 +5V
* 3 +5V
* 4 NC
* 5 Ground
* 6 Ground
* 7 Ground
* 8 NC
* 9 +12V
*
* J2 : 9 pin link connector Pin Use
* --------------
* 1 Ring In+
* 2 Ring In-
* 3 Ring Out2+
* 4 Ground
* 5 /RXD+ (NC)
* 6 /RXD- (NC)
* 7 /TXD (NC)
* 8 GND (NC)
* 9 +5V (NC)
*
* J3 : 9 pin socket Pin Use
* -------------------
* 1 Service Credit
* 2 Test
* 3 NC
* 4 +12V
* 5 Counter
* 6 NC
* 7 Ground
* 8 Coin Sw
* 9 NC
*
* J4 : 8 pin connector Pin Use
* -------------------------------------
* 1 Start
* 2 Left Select
* 3 Right Select
* 4 Safety Free Controls (Ski's etc)
* 5 Safety Lock Controls (Ski's etc)
* 6 NC
* 7 Ground
* 8 Ground
*
* J5 : 15 pin socket Pin Use
* ---------------
* 1 Relay1
* 2 Relay1
* 3 Mute
* 4 Mid Light
* 5 Left Light
* 6 Right Light
* 7 NC
* 8 NC
* 9 NC
* 10 NC
* 11 NC
* 12 NC
* 13 +12V
* 14 +5V
* 15 NC
*
* J6 : 12 pin audio output connector Pin Use
* ----------
* 1 SPKL+
* 2 SPKL-
* 3 SPKR+
* 4 SPKR-
* 5 NC
* 6 NC
* 7 NC
* 8 NC
* 9 NC
* 10 NC
* 11 NC
* 12 NC
*
* J7 : 12 pin analog controls socket Pin Use
* ---------------------------
* 1 +5V
* 2 5K Ohm Potentiometer 1 (Side Swing on Alpine Racer, Alpine Surfer etc)
* 3 5K Ohm Potentiometer 2 (Tilt on Alpine Racer, Alpine Surfer etc)
* 4 GND (Other games may use more/different pots or no pots)
* 5 NC
* 6 NC
* 7 NC
* 8 NC
* 9 NC
* 10 NC
* 11 NC
* 12 NC
*
* J8 : 10 pin connector (not used?)
*
* J9 : 6 pin video output socket Pin Use
* ---------
* 1 Red
* 2 Green
* 3 Blue
* 4 Composite Sync (VSync 15kHz interlaced)
* 5 Ground
* 6 NC
*
* J10: 16 pin flat cable connector (only populated on Mother(C) PCB, use not known)
*
*
*AMP PCB
*-------
*SYSTEM SUPER22 AMP(4) PCB 8647960100 (8647970100) (sticker 'AMP(2) PCB 8647961100')
*|-----------------------------------|
*|J1 J2 LA4705 J3 *1 *2 J5|
*| |
*|-----------------------------------|
*Notes:
* LA4705: 2-channel 15W Power Amp
* J1 : 3 pin power input socket Pin Use
* -----------
* 1 +12V
* 2 Ground
* 3 NC
*
* J2 : 4 pin dual speaker output socket Pin Use
* ---------
* 1 SP1+
* 2 SP1-
* 3 SP2+
* 4 SP2-
*
* J3 : 8 pin sound data input connector from Mother PCB J6 Pin Use
* ----------
* 1 SPKL+
* 2 SPKL-
* 3 SPKR+
* 4 SPKR-
* 5 NC
* 6 NC
* 7 NC
* 8 NC
*
* *1 : Unpopulated position for a 2nd LA4705 Power Amp
* *2 : J4 - Unpopulated position for another 4 pin dual speaker output socket
* J5 : 2 pin connector used for sound mute Pin Use
* -----------
* 1 Mute
* 2 Ground
*/
#include "emu.h"
#include "includes/namcos22.h"
#include "cpu/m68000/m68000.h"
#include "cpu/tms32025/tms32025.h"
#include "machine/namcomcu.h"
#include "sound/c352.h"
#include "speaker.h"
#define SS22_MASTER_CLOCK (XTAL(49'152'000)) /* info from Guru */
#define PIXEL_CLOCK (SS22_MASTER_CLOCK/2)
// VSync - 59.9042 Hz
// HSync - 15.7248 kHz (may be inaccurate)
#define HTOTAL (800)
#define HBEND (0)
#define HBSTART (640)
#define VTOTAL (512)
#define VBEND (0)
#define VBSTART (480)
#define MCU_SPEEDUP 1 /* mcu idle skipping */
/*********************************************************************************************/
// Main CPU
/* SCI, prelim! */
READ32_MEMBER(namcos22_state::namcos22_sci_r)
{
switch (offset)
{
case 0x0/4:
return 0x0004 << 16;
default:
return 0;
}
}
#if 0
WRITE32_MEMBER(namcos22_state::namcos22_sci_w)
{
COMBINE_DATA(&m_sci_regs[offset]);
/*
20020000 2 R/W RX Status
0x01 : Frame Error
0x02 : Frame Received
0x04 : ?
20020002 2 R/W Status/Control Flags
0x01 :
0x02 : RX flag? (cleared every vsync)
0x04 : RX flag? (cleared every vsync)
0x08 :
20020004 2 W FIFO Control Register
0x01 : sync bit enable?
0x02 : TX FIFO sync bit (bit-8)
20020006 2 W TX Control Register
0x01 : TX start/stop
0x02 : ?
0x10 : ?
20020008 2 W -
2002000a 2 W TX Frame Size
2002000c 2 R/W RX FIFO Pointer (0x0000 - 0x0fff)
2002000e 2 W TX FIFO Pointer (0x0000 - 0x1fff)
*/
}
#endif
/* system controller (super system22)
0x00: vblank irq level
0x01: hblank irq level
0x02: sci irq level
0x03: unk irq level (unused?)
0x04: vblank irq ack
0x05: hblank irq ack
0x06: sci irq ack
0x07: unk irq ack
0x08: unknown
0x09: 0x62 or 0x61
0x0a: 0x62
0x0b: 0x57
0x0c: 0x40
0x0d: 0x12
0x0e: 0x52 or 0x50
0x0f: 0x72 or 0x71
0x10: 0xe0
0x11: 0x2c
0x12: 0x50
0x13: 0xff
0x14: watchdog
0x15: ?
0x16: subcpu enable
0x17: 0x0f
0x18: ?
0x19: ?
0x1a: ?
0x1b: 0x01
0x1c: dsp control
*/
WRITE8_MEMBER(namcos22_state::namcos22s_system_controller_w)
{
switch (offset)
{
// irq level / enable irqs
case 0x00: // vblank
case 0x01: // hblank
case 0x02: // SCI
case 0x03: // unknown
{
int line = 1 << offset;
int oldlevel = m_syscontrol[offset] & 7;
int newlevel = data & 7;
if (m_irq_state & line && oldlevel != newlevel)
{
m_maincpu->set_input_line(oldlevel, CLEAR_LINE);
if (newlevel)
m_maincpu->set_input_line(newlevel, ASSERT_LINE);
else
m_irq_state &= ~line;
}
break;
}
// acknowledge irqs
case 0x04: // vblank
case 0x05: // hblank
case 0x06: // SCI
case 0x07: // unknown
{
int line = 1 << (offset-4);
m_irq_state &= ~line;
m_maincpu->set_input_line(m_syscontrol[offset-4] & 7, CLEAR_LINE);
break;
}
// watchdog
case 0x14:
break;
// reset mcu
case 0x16:
m_mcu->set_input_line(INPUT_LINE_RESET, data ? CLEAR_LINE : ASSERT_LINE);
break;
// dsp control
case 0x1c:
if (data != m_syscontrol[0x1c])
{
if (data == 0)
{
/* disable DSPs */
m_master->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
m_slave->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
enable_slave_simulation(false);
m_dsp_irq_enabled = false;
}
else if (data == 1)
{
/* enable dsp and rendering subsystem */
m_master->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
enable_slave_simulation(true);
m_dsp_irq_enabled = true;
}
else if (data == 0xff)
{
/* used to upload game-specific code to master/slave dsps */
m_master->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
m_dsp_irq_enabled = false;
}
}
break;
// other regs: unknown
default:
break;
}
m_syscontrol[offset] = data;
}
/*
000064: 0000 8C9A (1)
000068: 0000 8CA2 (2)
00006C: 0000 8CAA (3)
000070: 0000 8CB2 (4)
00008bd8: sys[0x01] := 0x01 // scanline
00008be0: sys[0x02] := 0x02 // sci
00008be8: sys[0x03] := 0x03 // unk
00008bf0: sys[0x00] := 0x04 // vblank
00008bf8: sys[0x08] := 0xff // ?
*/
INTERRUPT_GEN_MEMBER(namcos22_state::namcos22s_interrupt)
{
if (m_syscontrol[0x00] & 7)
{
// vblank irq
m_irq_state |= (1 << 0x00);
device.execute().set_input_line(m_syscontrol[0x00] & 7, ASSERT_LINE);
}
}
/* system controller (system22)
0x00: IRQ (unknown)
0x01: ?
0x02: SCI IRQ level
0x03: IRQ (unknown)
0x04: VSYNC IRQ level
0x05: IRQ (unknown) acknowledge
0x06: ?
0x07: SCI IRQ acknowledge
0x08: IRQ (unknown) acknowledge
0x09: VSYNC IRQ acknowledge
0x0a: ?
0x0b: ?
0x0c: ?
0x0d: ?
0x0e: ?
0x0f: ?
0x10: ?
0x11: ?
0x12: ?
0x13: ?
0x14: ?
0x15: ? (cyc1)
0x16: Watchdog timer reset
0x17: ?
0x18: 0 or 1 -> mcu reset?
0x19: ?
0x1a: 0 or 1 or 0xff -> DSP control
0x1b: ?
*/
WRITE8_MEMBER(namcos22_state::namcos22_system_controller_w)
{
switch (offset)
{
// irq level / enable irqs
case 0x00: // unknown
case 0x01: // ?
case 0x02: // SCI
case 0x03: // unknown
case 0x04: // vblank
{
int line = 1 << offset;
int oldlevel = m_syscontrol[offset] & 7;
int newlevel = data & 7;
if (m_irq_state & line && oldlevel != newlevel)
{
m_maincpu->set_input_line(oldlevel, CLEAR_LINE);
if (newlevel)
m_maincpu->set_input_line(newlevel, ASSERT_LINE);
else
m_irq_state &= ~line;
}
break;
}
// acknowledge irqs
case 0x05: // unknown
case 0x06: // ?
case 0x07: // SCI
case 0x08: // unknown
case 0x09: // vblank
{
int line = 1 << (offset-5);
m_irq_state &= ~line;
m_maincpu->set_input_line(m_syscontrol[offset-5] & 7, CLEAR_LINE);
break;
}
// watchdog
case 0x16:
break;
// reset mcu
case 0x18:
m_mcu->set_input_line(INPUT_LINE_RESET, data ? CLEAR_LINE : ASSERT_LINE);
break;
// dsp control
case 0x1a:
if (data != m_syscontrol[0x1a])
{
if (data == 0)
{
/* disable DSPs */
m_master->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
m_slave->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
enable_slave_simulation(false);
m_dsp_irq_enabled = false;
}
else if (data == 1)
{
/* enable dsp and rendering subsystem */
m_master->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
enable_slave_simulation(true);
m_dsp_irq_enabled = true;
}
else if (data == 0xff)
{
/* used to upload game-specific code to master/slave dsps */
m_master->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
m_dsp_irq_enabled = false;
}
}
break;
// other regs: unknown
default:
break;
}
m_syscontrol[offset] = data;
}
/* namcos22_interrupt
Ridge Racer:
1:0a0b6
2:09fe8 (rte)
3:09fe8 (rte)
4:09f9a (vblank)
5:14dee (SCI)
6:09fe8 (rte)
7:09fe8 (rte)
Ridge Racer 2:
1:0d10c 40000005
2:0cfa2 (rte)
3:0cfa2 (rte)
4:0cfa2 (rte)
5:0cef0
6:1bbcc
7:0cfa2 (rte)
Ace Driver:
9f8 (rte)
9fa (rte)
9fc (rte)
9fe (rte)
a00
a46
a4c (rte)
Victory Lap:
a54 indir to 21c2 (hblank?)
a5a (rte)
a5c (rte)
a5e (rte)
a60 irq
abe indirect to 27f1e (SCI)
ac4 (rte)
Cyber Commando:
move.b #$36, $40000002.l
move.b # $0, $40000003.l
move.b #$35, $40000004.l
move.b #$34, $40000004.l
*/
INTERRUPT_GEN_MEMBER(namcos22_state::namcos22_interrupt)
{
switch (m_gametype)
{
case NAMCOS22_RIDGE_RACER:
case NAMCOS22_RIDGE_RACER2:
case NAMCOS22_RAVE_RACER:
case NAMCOS22_ACE_DRIVER:
case NAMCOS22_VICTORY_LAP:
handle_driving_io();
break;
case NAMCOS22_CYBER_COMMANDO:
handle_cybrcomm_io();
break;
default:
break;
}
if (m_syscontrol[0x04] & 7)
{
// vblank irq
m_irq_state |= (1 << 0x04);
device.execute().set_input_line(m_syscontrol[0x04] & 7, ASSERT_LINE);
}
}
READ8_MEMBER(namcos22_state::namcos22_system_controller_r)
{
return m_syscontrol[offset];
}
READ32_MEMBER(namcos22_state::namcos22_dspram_r)
{
return m_polygonram[offset] | 0xff000000; // only d0-23 are connected
}
WRITE32_MEMBER(namcos22_state::namcos22_dspram_w)
{
if (ACCESSING_BITS_16_23)
{
// only d0-23 are connected
mem_mask |= 0xff000000;
data = signed24(data); // !
}
COMBINE_DATA(&m_polygonram[offset]);
}
READ16_MEMBER(namcos22_state::namcos22_keycus_r)
{
// Like other Namco hardware, this chip is used for protection as well as
// reading random values in some games for example in timecris to determine
// where certain enemies will emerge.
// It works in combination with keycus_w, but not yet understood how.
// printf("Hit keycus offs %x mask %x PC=%x\n", offset, mem_mask, m_maincpu->pc());
// protection (not used for all games)
// note: some games will XOR this register against a magic value, but that doesn't mean
// that the magic value is the keycus id. For example dirtdash XORs against $2c79, but its
// keycus id is $01a2 evident from a simple compare.
switch (m_gametype)
{
case NAMCOS22_RIDGE_RACER2:
if (offset == 0) return 0x0172;
break;
case NAMCOS22_ACE_DRIVER:
if (offset == 3) return 0x0173;
break;
case NAMCOS22_CYBER_COMMANDO:
if (offset == 1) return 0x0185;
break;
case NAMCOS22_ALPINE_RACER:
if (offset == 1) return 0x0187;
break;
case NAMCOS22_CYBER_CYCLES:
if (offset == 0xf) return 0x0387;
break;
case NAMCOS22_VICTORY_LAP:
if (offset == 2) return 0x0188;
break;
case NAMCOS22_DIRT_DASH:
if (offset == 0) return 0x01a2;
break;
case NAMCOS22_ALPINE_SURFER:
if (offset == 1) return 0x01a9;
break;
case NAMCOS22_TOKYO_WARS:
if (offset == 4) return 0x01a8;
break;
default:
break;
}
// pick a random number, but don't pick the same twice in a row
uint16_t old_rng = m_keycus_rng;
do
{
m_keycus_rng = machine().rand() & 0xffff;
} while(m_keycus_rng == old_rng);
return m_keycus_rng;
}
WRITE16_MEMBER(namcos22_state::namcos22_keycus_w)
{
// for obfuscating keycus and/or random seed?
}
/**
* Some port values are read serially one bit at a time via word reads at
* 0x50000008 and 0x5000000a
*
* Writes to 0x50000008 and 0x5000000a reset the state of the input buffer.
*
* Note that only the values read at 0x50000008 seem to be used in-game.
*
* Some of these values are redundant with respects to the work-RAM supplied input port
* values supplied by the IO CPU. For example, the position of the stick shift is digital,
* and may be read through this mechanism or through shared IO RAM at 0x60004030.
*
* Other values seem to be digital versions of analog ports, for example "the gas pedal is
* pressed" as a boolean flag. IO RAM supplies it as an analog value.
*/
READ16_MEMBER(namcos22_state::namcos22_portbit_r)
{
uint16_t ret = m_portbits[offset] & 1;
m_portbits[offset] = m_portbits[offset] >> 1 | 0x8000;
return ret;
}
WRITE16_MEMBER(namcos22_state::namcos22_portbit_w)
{
m_portbits[offset] = ((offset == 0) ? m_p1 : m_p2).read_safe(0xffff);
}
READ16_MEMBER(namcos22_state::namcos22_dipswitch_r)
{
return ioport("DSW0")->read();
}
WRITE16_MEMBER(namcos22_state::namcos22_cpuleds_w)
{
// 8 leds on cpu board, 0=on 1=off
// on system 22: two rows of 4 red leds
// on super system 22: GYRGYRGY green/yellow/red
for (int i = 0; i < 8; i++)
m_cpuled[i] = (~data << i & 0x80) ? 0 : 1;
}
WRITE32_MEMBER(namcos22_state::namcos22s_chipselect_w)
{
// assume that this register is for chip enable/disable
// it's written many times during boot-up, and most games don't touch it afterwards (last value usually 0038 or 0838)
// 8000: spot related (set in dirtdash night driving)
// 4000: spot related (set in dirtdash and testmode)
// 0800: fade related?
// other bits: no clue
if (ACCESSING_BITS_16_23)
m_chipselect = data >> 16;
// 8-bit access? (see alpinerd)
else if (ACCESSING_BITS_24_31)
m_chipselect = data >> 24;
}
// System 22
void namcos22_state::namcos22_am(address_map &map)
{
/**
* Program ROM (2M bytes)
* Mounted position: LLB: CPU 4D, LMB: CPU 2D, UMB: CPU 8D, UUB: CPU 6D
* Known ROM chip type: TI TMS27C040-10, ST M27C4001-10, M27C4001-12Z
*/
map(0x00000000, 0x001fffff).rom();
/**
* Main RAM (128K bytes)
* Mounted position: CPU 3D, 5D, 7D, 9D
* Known DRAM chip type: TC55328P-25, N3441256P-15
*/
map(0x10000000, 0x1001ffff).ram().mirror(0x08000000);
/**
* KEYCUS
* Mounted position: CPU 13R
* Known chip type:
* C370 (Ridge Racer, Ridge Racer 2)
* C388 (Rave Racer)
* C389? (Cyber Cycles)
* C392? (Ace Driver Victory Lap)
*/
map(0x20000000, 0x2000000f).rw(FUNC(namcos22_state::namcos22_keycus_r), FUNC(namcos22_state::namcos22_keycus_w));
/**
* C139 SCI Buffer
* Mounted position: CPU 4N
* Known chip type: M5M5179AP-25 (8k x 9bit SRAM)
*
* Note: Boot time check: 20010000 - 20011fff / bits=0x000001ff
*
* 20010000 - 20011fff TX Buffer
* 20012000 - 20013fff RX FIFO Buffer (also used for TX Buffer)
*/
map(0x20010000, 0x20013fff).ram();
/**
* C139 SCI Register
* Mounted position: CPU 4R
*
* 20020000 2 R/W RX Status
* 0x01 : Frame Error
* 0x02 : Frame Received
* 0x04 : ?
*
* 20020002 2 R/W Status/Control Flags
* 0x01 :
* 0x02 : RX flag? (cleared every vsync)
* 0x04 : RX flag? (cleared every vsync)
* 0x08 :
*
* 20020004 2 W FIFO Control Register
* 0x01 : sync bit enable?
* 0x02 : TX FIFO sync bit (bit-8)
*
* 20020006 2 W TX Control Register
* 0x01 : TX start/stop
* 0x02 : ?
* 0x10 : ?
*
* 20020008 2 W -
* 2002000a 2 W TX Frame Size
* 2002000c 2 R/W RX FIFO Pointer (0x0000 - 0x0fff)
* 2002000e 2 W TX FIFO Pointer (0x0000 - 0x1fff)
*/
map(0x20020000, 0x2002000f).r(FUNC(namcos22_state::namcos22_sci_r)).writeonly();
/**
* System Controller: Interrupt Control, Peripheral Control
*
*/
map(0x40000000, 0x4000001f).rw(FUNC(namcos22_state::namcos22_system_controller_r), FUNC(namcos22_state::namcos22_system_controller_w));
/**
* Unknown Device (optional for diagnostics?)
*
* zero means not-connected.
* may be related to device at 0x94000000
*/
map(0x48000000, 0x4800003f).nopr().nopw();
/**
* DIPSW
* 0x50000000 - DIPSW3
* 0x50000001 - DIPSW2
*/
map(0x50000000, 0x50000003).rw(FUNC(namcos22_state::namcos22_dipswitch_r), FUNC(namcos22_state::namcos22_cpuleds_w));
map(0x50000008, 0x5000000b).rw(FUNC(namcos22_state::namcos22_portbit_r), FUNC(namcos22_state::namcos22_portbit_w));
/**
* EEPROM
* Mounted position: CPU 9E
* Known chip type: HN58C65P-25 (8k x 8bit EEPROM)
*/
map(0x58000000, 0x58001fff).rw(m_eeprom, FUNC(eeprom_parallel_28xx_device::read), FUNC(eeprom_parallel_28xx_device::write));
/**
* C74 (Mitsubishi M37702 MCU) Shared RAM (0x60004000 - 0x6000bfff)
* Mounted position: CPU 11L, 12L
* Known chip type: TC55328P-25, N341256P-15
*
* DATA ROM for C74 (SEQ data and external code):
* Known chip type: NEC D27C4096D-12
* Notes: C74(CPU PCB) sends/receives I/O data from C74(I/O PCB) by SIO.
*
* 0x60004020 b4 = 1 : ???
* 0x60004022.w Volume(R)
* 0x60004024.w Volume(L)
* 0x60004026.w Volume(R) (maybe rear channels, not put on real PCB)
* 0x60004028.w Volume(L) (maybe rear channels, not put on real PCB)
* 0x60004030 b0 : system type 0
* 0x60004030 b1 = 0 : COIN2
* 0x60004030 b2 = 0 : TEST SW
* 0x60004030 b3 = 0 : SERVICE SW
* 0x60004030 b4 = 0 : COIN1
* 0x60004030 b5 : system type 1
* (system type on RR2 (00:50inch, 01:two in one, 20:standard, 21:deluxe))
* 0x60004031 b0 = 0 : SWITCH1 (for manual transmission)
* 0x60004031 b1 = 0 : SWITCH2
* 0x60004031 b2 = 0 : SWITCH3
* 0x60004031 b3 = 0 : SWITCH4
* 0x60004031 b4 = 0 : CLUTCH
* 0x60004031 b6 = 0 : VIEW SW
* 0x60004032.w Handle A/D (=steering wheel, default of center value is different in each game)
* 0x60004034.w Gas A/D
* 0x60004036.w Brake A/D
* 0x60004038.w A/D3 (reserved)
* (some GOUT (general outputs for lamps, etc) is also mapped this area)
* 0x60004080 Data/Code for Sub-CPU
* 0x60004200 Data/Code for Sub-CPU
* 0x60005000 - 0x6000bfff Sound Work
* +0x0000 - 0x003f Song Request #00 to 31
* +0x0100 - 0x02ff Parameter RAM from Main MPU (for SEs)
* +0x0300 - 0x03ff? Song Title (put messages here from Sound CPU)
*/
map(0x60000000, 0x60003fff).nopw();
map(0x60004000, 0x6000bfff).ram().share("shareram");
/**
* C71 (TI TMS320C25 DSP) Shared RAM (0x70000000 - 0x70020000)
* Mounted position:
* C71: CPU 15R, 21R
* RAM: CPU 15K, 13E, 12E
* Known chip type: TC55328P-25, N341256P-15
* Notes: connected bits = 0x00ffffff (24bit)
*/
map(0x70000000, 0x7001ffff).rw(FUNC(namcos22_state::namcos22_dspram_r), FUNC(namcos22_state::namcos22_dspram_w)).share("polygonram");
/**
* LED on PCB(?)
*/
map(0x90000000, 0x90000003).ram();
/**
* Depth-cueing Look-up Table (fog density between near to far)
* Mounted position: VIDEO 8P
* Known chip type: TC55328P-25
*/
map(0x90010000, 0x90017fff).ram().share("czram");
/**
* C305 (Display Controller)
* Mounted position: VIDEO 7D (C305)
* Notes: Boot time check: 0x90020100 - 0x9002027f
*/
map(0x90020000, 0x90027fff).ram().share("video_mixer");
/**
* Mounted position: VIDEO 6B, 7B, 8B (near C305)
* Note: 0xff00-0xffff are for Tilemap (16 x 16)
*/
map(0x90028000, 0x9003ffff).ram().w(FUNC(namcos22_state::namcos22_paletteram_w)).share("paletteram");
/**
* unknown (option)
* Note: This device may be optional. This may relate to device at 0x40000000
*/
map(0x90040000, 0x9007ffff).ram(); /* diagnostic ROM? */
/**
* Tilemap PCG Memory
*/
map(0x90080000, 0x9009dfff).ram().w(FUNC(namcos22_state::namcos22_cgram_w)).share("cgram");
/**
* Tilemap Memory (64 x 64)
* Mounted position: VIDEO 2K
* Known chip type: HM511664 (64k x 16bit SRAM)
* Note: Self test: 90084000 - 9009ffff
*/
map(0x9009e000, 0x9009ffff).ram().w(FUNC(namcos22_state::namcos22_textram_w)).share("textram");
/**
* Tilemap Register
* Mounted position: unknown
*/
map(0x900a0000, 0x900a000f).rw(FUNC(namcos22_state::namcos22_tilemapattr_r), FUNC(namcos22_state::namcos22_tilemapattr_w)).share("tilemapattr");
}
// Super System 22
void namcos22_state::namcos22s_am(address_map &map)
{
map(0x000000, 0x3fffff).rom();
map(0x400000, 0x40001f).rw(FUNC(namcos22_state::namcos22_keycus_r), FUNC(namcos22_state::namcos22_keycus_w));
map(0x410000, 0x413fff).ram(); /* C139 SCI buffer */
map(0x420000, 0x42000f).r(FUNC(namcos22_state::namcos22_sci_r)).writeonly(); /* C139 SCI registers */
map(0x440000, 0x440003).rw(FUNC(namcos22_state::namcos22_dipswitch_r), FUNC(namcos22_state::namcos22_cpuleds_w));
map(0x450008, 0x45000b).rw(FUNC(namcos22_state::namcos22_portbit_r), FUNC(namcos22_state::namcos22_portbit_w));
map(0x460000, 0x463fff).rw(m_eeprom, FUNC(eeprom_parallel_28xx_device::read), FUNC(eeprom_parallel_28xx_device::write)).umask32(0xff00ff00);
map(0x700000, 0x70001f).rw(FUNC(namcos22_state::namcos22_system_controller_r), FUNC(namcos22_state::namcos22s_system_controller_w));
map(0x800000, 0x800003).w(FUNC(namcos22_state::namcos22s_chipselect_w));
map(0x810000, 0x81000f).ram().share("czattr");
map(0x810200, 0x8103ff).rw(FUNC(namcos22_state::namcos22s_czram_r), FUNC(namcos22_state::namcos22s_czram_w));
map(0x820000, 0x8202ff).nopw(); /* leftover of old (non-super) video mixer device */
map(0x824000, 0x8243ff).ram().share("video_mixer");
map(0x828000, 0x83ffff).ram().w(FUNC(namcos22_state::namcos22_paletteram_w)).share("paletteram");
map(0x860000, 0x860007).rw(FUNC(namcos22_state::namcos22s_spotram_r), FUNC(namcos22_state::namcos22s_spotram_w));
map(0x880000, 0x89dfff).ram().w(FUNC(namcos22_state::namcos22_cgram_w)).share("cgram");
map(0x89e000, 0x89ffff).ram().w(FUNC(namcos22_state::namcos22_textram_w)).share("textram");
map(0x8a0000, 0x8a000f).rw(FUNC(namcos22_state::namcos22_tilemapattr_r), FUNC(namcos22_state::namcos22_tilemapattr_w)).share("tilemapattr");
map(0x900000, 0x90ffff).ram().share("vics_data");
map(0x940000, 0x94007f).rw(FUNC(namcos22_state::namcos22s_vics_control_r), FUNC(namcos22_state::namcos22s_vics_control_w)).share("vics_control");
map(0x980000, 0x9affff).ram().share("spriteram"); /* C374 */
map(0xa04000, 0xa0bfff).ram().share("shareram"); /* COM RAM */
map(0xc00000, 0xc1ffff).rw(FUNC(namcos22_state::namcos22_dspram_r), FUNC(namcos22_state::namcos22_dspram_w)).share("polygonram");
map(0xe00000, 0xe3ffff).ram(); /* workram */
}
// Time Crisis gun
READ32_MEMBER(namcos22_state::namcos22_gun_r)
{
uint16_t xpos = ioport("LIGHTX")->read();
uint16_t ypos = ioport("LIGHTY")->read();
// ypos is not completely understood yet, there should be a difference between case 1 and 2
switch (offset)
{
case 0: /* 430000 */
return xpos << 16;
case 1: /* 430004 */
case 2: /* 430008 */
return ypos << 16;
default:
return 0;
}
}
void namcos22_state::timecris_am(address_map &map)
{
namcos22s_am(map);
map(0x430000, 0x43000f).r(FUNC(namcos22_state::namcos22_gun_r));
}
// Alpine Surfer protection
READ32_MEMBER(namcos22_state::alpinesa_prot_r)
{
return m_alpinesa_protection;
}
WRITE32_MEMBER(namcos22_state::alpinesa_prot_w)
{
switch (data)
{
case 0:
m_alpinesa_protection = 0;
break;
case 1:
m_alpinesa_protection = 1;
break;
case 3:
m_alpinesa_protection = 2;
break;
default:
break;
}
}
void namcos22_state::alpinesa_am(address_map &map)
{
namcos22s_am(map);
map(0x200000, 0x200003).r(FUNC(namcos22_state::alpinesa_prot_r));
map(0x300000, 0x300003).w(FUNC(namcos22_state::alpinesa_prot_w));
}
/*********************************************************************************************/
// DSPs
void namcos22_state::enable_slave_simulation(bool enable)
{
m_slave_simulation_active = enable;
}
void namcos22_state::slave_halt()
{
m_slave->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
enable_slave_simulation(false);
}
void namcos22_state::slave_enable()
{
// m_slave->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
enable_slave_simulation(true);
}
READ16_MEMBER(namcos22_state::namcos22_dspram16_r)
{
uint32_t value = m_polygonram[offset];
switch (m_dspram_bank)
{
case 0:
value &= 0xffff;
break;
case 1:
value >>= 16;
break;
case 2:
m_dspram16_latch = value >> 16;
value &= 0xffff;
break;
default:
break;
}
return (uint16_t)value;
}
WRITE16_MEMBER(namcos22_state::namcos22_dspram16_w)
{
uint32_t value = m_polygonram[offset];
uint16_t lo = value & 0xffff;
uint16_t hi = value >> 16;
switch (m_dspram_bank)
{
case 0:
COMBINE_DATA(&lo);
break;
case 1:
COMBINE_DATA(&hi);
break;
case 2:
COMBINE_DATA(&lo);
hi = m_dspram16_latch;
break;
default:
break;
}
m_polygonram[offset] = (hi << 16) | lo;
}
WRITE16_MEMBER(namcos22_state::namcos22_dspram16_bank_w)
{
COMBINE_DATA(&m_dspram_bank);
}
void namcos22_state::point_write(offs_t offs, uint32_t data)
{
offs &= 0x00ffffff; /* 24 bit addressing */
if (m_is_ss22)
{
if (offs >= 0xf80000 && offs < 0xfa0000)
m_pointram[offs - 0xf80000] = data & 0x00ffffff;
}
else
{
if (offs >= 0xf00000 && offs < 0xf20000)
m_pointram[offs - 0xf00000] = data & 0x00ffffff;
}
}
int32_t namcos22_state::point_read(int32_t addr)
{
if (addr < 0)
return -1;
// point rom
else if (addr < m_pointrom_size)
return m_pointrom[addr];
// point ram, only used in ram test?
int32_t result = 0;
if (m_is_ss22)
{
if (addr >= 0xf80000 && addr < 0xfa0000)
result = m_pointram[addr - 0xf80000];
else return -1;
}
else
{
if (addr >= 0xf00000 && addr < 0xf20000)
result = m_pointram[addr - 0xf00000];
else return -1;
}
// sign extend or crop
return signed24(result);
}
WRITE16_MEMBER(namcos22_state::point_address_w)
{
m_point_address <<= 16;
m_point_address |= data;
}
WRITE16_MEMBER(namcos22_state::point_loword_iw)
{
m_point_data |= data;
point_write(m_point_address++, m_point_data);
}
WRITE16_MEMBER(namcos22_state::point_hiword_w)
{
m_point_data = data << 16;
}
READ16_MEMBER(namcos22_state::point_loword_r)
{
return point_read(m_point_address & 0x00ffffff) & 0xffff;
}
READ16_MEMBER(namcos22_state::point_hiword_ir)
{
return point_read(m_point_address++ & 0x00ffffff) >> 16 & 0xffff;
}
READ16_MEMBER(namcos22_state::pdp_status_r)
{
return m_dsp_master_bioz;
}
uint32_t namcos22_state::pdp_polygonram_read(offs_t offs)
{
return m_polygonram[offs & 0x7fff];
}
void namcos22_state::pdp_polygonram_write(offs_t offs, uint32_t data)
{
m_polygonram[offs & 0x7fff] = data;
}
READ16_MEMBER(namcos22_state::pdp_begin_r)
{
/* this feature appears to be only used on Super System22 hardware */
if (m_is_ss22)
{
uint16_t offs = pdp_polygonram_read(0x7fff);
m_dsp_master_bioz = 1;
for (;;)
{
uint16_t start = offs;
uint16_t cmd = pdp_polygonram_read(offs++);
uint32_t srcAddr;
uint32_t dstAddr;
uint32_t numWords;
uint32_t data;
switch (cmd)
{
case 0xfff0:
/* NOP? used in 'PDP LOOP TEST' */
break;
case 0xfff5:
/* write to point ram */
dstAddr = pdp_polygonram_read(offs++); /* 32 bit PointRAM address */
data = pdp_polygonram_read(offs++); /* 24 bit data */
point_write(dstAddr, data);
break;
case 0xfff6:
/* read word from point ram */
srcAddr = pdp_polygonram_read(offs++); /* 32 bit PointRAM address */
dstAddr = pdp_polygonram_read(offs++); /* CommRAM address; receives 24 bit PointRAM data */
data = point_read(srcAddr & 0x00ffffff);
pdp_polygonram_write(dstAddr, data);
break;
case 0xfff7:
/* block move (CommRAM to CommRAM) */
srcAddr = pdp_polygonram_read(offs++);
dstAddr = pdp_polygonram_read(offs++);
numWords = pdp_polygonram_read(offs++);
while (numWords--)
{
data = pdp_polygonram_read(srcAddr++);
pdp_polygonram_write(dstAddr++, data);
}
break;
case 0xfffa:
/* read block from point ram */
srcAddr = pdp_polygonram_read(offs++); /* 32 bit PointRAM address */
dstAddr = pdp_polygonram_read(offs++); /* CommRAM address; receives data */
numWords = pdp_polygonram_read(offs++); /* block size */
while (numWords--)
{
data = point_read(srcAddr++ & 0x00ffffff);
pdp_polygonram_write(dstAddr++, data);
}
break;
case 0xfffb:
/* write block to point ram */
dstAddr = pdp_polygonram_read(offs++); /* 32 bit PointRAM address */
numWords = pdp_polygonram_read(offs++); /* block size */
while (numWords--)
{
data = pdp_polygonram_read(offs++); /* 24 bit source data */
point_write(dstAddr++, data);
}
break;
case 0xfffc:
/* point ram to point ram */
srcAddr = pdp_polygonram_read(offs++);
dstAddr = pdp_polygonram_read(offs++);
numWords = pdp_polygonram_read(offs++);
while (numWords--)
{
data = point_read(srcAddr++ & 0x00ffffff);
point_write(dstAddr++, data);
}
break;
case 0xfffd:
/* direct command to render device */
// len -> command (eg. BB0003) -> data
numWords = pdp_polygonram_read(offs++);
while (numWords--)
{
data = pdp_polygonram_read(offs++);
//namcos22_WriteDataToRenderDevice(data);
}
break;
case 0xfffe:
/* unknown */
data = pdp_polygonram_read(offs++); /* ??? (usually 0x400 or 0) */
break;
case 0xffff:
/* "goto" command */
offs = pdp_polygonram_read(offs);
if (offs == start)
{
/* most commands end with a "goto self" */
return 0;
}
break;
default:
logerror("unknown PDP cmd = 0x%04x!\n", cmd);
return 0;
}
}
}
return 0;
}
READ16_MEMBER(namcos22_state::slave_external_ram_r)
{
return m_pSlaveExternalRAM[offset];
}
WRITE16_MEMBER(namcos22_state::slave_external_ram_w)
{
COMBINE_DATA(&m_pSlaveExternalRAM[offset]);
}
READ16_MEMBER(namcos22_state::dsp_hold_signal_r)
{
/* STUB */
return 0;
}
WRITE16_MEMBER(namcos22_state::dsp_hold_ack_w)
{
/* STUB */
}
WRITE16_MEMBER(namcos22_state::dsp_xf_output_w)
{
/* STUB */
}
WRITE16_MEMBER(namcos22_state::dsp_unk2_w)
{
/**
* Used by Ridge Racer (Japan) to specify baseaddr
* for post-processed display-list output.
*
* Prop Cycle doesn't use this; instead it writes this
* addr to the uppermost word of CommRAM.
*/
}
READ16_MEMBER(namcos22_state::dsp_unk_port3_r)
{
m_dsp_master_bioz = 0;
m_dsp_upload_state = NAMCOS22_DSP_UPLOAD_READY;
return 0;
}
WRITE16_MEMBER(namcos22_state::upload_code_to_slave_dsp_w)
{
switch (m_dsp_upload_state)
{
case NAMCOS22_DSP_UPLOAD_READY:
logerror("UPLOAD_READY; cmd = 0x%x\n", data);
switch (data)
{
case 0x00:
slave_halt();
break;
case 0x01:
m_dsp_upload_state = NAMCOS22_DSP_UPLOAD_DEST;
break;
case 0x02:
/* custom IC poke */
break;
case 0x03:
slave_enable();
break;
case 0x04:
break;
case 0x10:
/* serial i/o related? */
slave_enable();
break;
default:
logerror("%08x: master port#7: 0x%04x\n", m_master->pcbase(), data);
break;
}
break;
case NAMCOS22_DSP_UPLOAD_DEST:
m_UploadDestIdx = data;
m_dsp_upload_state = NAMCOS22_DSP_UPLOAD_DATA;
break;
case NAMCOS22_DSP_UPLOAD_DATA:
m_pSlaveExternalRAM[m_UploadDestIdx & 0x1fff] = data;
m_UploadDestIdx++;
break;
default:
break;
}
}
READ16_MEMBER(namcos22_state::dsp_unk8_r)
{
/* bit 0x0001 is busy signal */
return 0x0000;
}
READ16_MEMBER(namcos22_state::custom_ic_status_r)
{
/* bit 0x0001 signals completion */
return 0x0063;
}
READ16_MEMBER(namcos22_state::dsp_upload_status_r)
{
/* bit 0x0001 is polled to confirm that code/data has been successfully uploaded to the slave dsp via port 0x7. */
return 0x0000;
}
READ16_MEMBER(namcos22_state::master_external_ram_r)
{
return m_pMasterExternalRAM[offset];
}
WRITE16_MEMBER(namcos22_state::master_external_ram_w)
{
COMBINE_DATA(&m_pMasterExternalRAM[offset]);
}
WRITE16_MEMBER(namcos22_state::slave_serial_io_w)
{
m_SerialDataSlaveToMasterNext = data;
logerror("slave_serial_io_w(%04x)\n", data);
}
READ16_MEMBER(namcos22_state::master_serial_io_r)
{
logerror("master_serial_io_r() == %04x\n", m_SerialDataSlaveToMasterCurrent);
return m_SerialDataSlaveToMasterCurrent;
}
TIMER_DEVICE_CALLBACK_MEMBER(namcos22_state::dsp_master_serial_irq)
{
int scanline = param;
if (m_dsp_irq_enabled)
{
m_SerialDataSlaveToMasterCurrent = m_SerialDataSlaveToMasterNext;
if (scanline == 480)
{
m_master->set_input_line(TMS32025_INT0, HOLD_LINE);
}
else if ((scanline % 2) == 0)
{
m_master->set_input_line(TMS32025_RINT, HOLD_LINE);
m_master->set_input_line(TMS32025_XINT, HOLD_LINE);
}
}
}
TIMER_DEVICE_CALLBACK_MEMBER(namcos22_state::dsp_slave_serial_irq)
{
int scanline = param;
if (m_dsp_irq_enabled)
{
if ((scanline % 2) == 0)
{
m_slave->set_input_line(TMS32025_RINT, HOLD_LINE);
m_slave->set_input_line(TMS32025_XINT, HOLD_LINE);
}
}
}
WRITE16_MEMBER(namcos22_state::dsp_unk_porta_w)
{
}
WRITE16_MEMBER(namcos22_state::dsp_led_w)
{
/* I believe this port controls diagnostic LEDs on the DSP PCB. */
}
/**
* master dsp usage pattern:
*
* 4059: out $10,PA$8
* 405A: in $09,PA$8; lac $09,0h; andk 0001h,0h; bnz $405A *
* 4060: out $11,PA$8
*
* 4061: out $10,PA$F
* 4062: nop; rpt *+; out *+,PA$C // send data to 'render device'
* 4065: out $11,PA$F
*
* 4066: out $10,PA$9
* 4067: nop
* 4068: out $11,PA$9
**************************************************************
* 0x03a2 // 0x0fff zcode lo
* 0x0001 // 0x000f zcode hi
* 0xbd00 // color
* 0x13a2 // flags
*
* 0x0100 0x009c // u,v
* 0x0072 0xf307 // sx,sy
* 0x602b 0x9f28 // i,zpos
*
* 0x00bf 0x0060 // u,v
* 0x0040 0xf3ec // sx,sy
* 0x602b 0xad48 // i,zpos
*
* 0x00fb 0x00ca // u,v
* 0x0075 0xf205 // sx,sy
* 0x602b 0x93e8 // i,zpos
*
* 0x00fb 0x00ca // u,v
* 0x0075 0xf205 // sx,sy
* 0x602b 0x93e8 // i,zpos
*/
WRITE16_MEMBER(namcos22_state::dsp_unk8_w)
{
m_RenderBufSize = 0;
}
WRITE16_MEMBER(namcos22_state::master_render_device_w)
{
if (m_RenderBufSize < NAMCOS22_MAX_RENDER_CMD_SEQ)
{
m_RenderBufData[m_RenderBufSize++] = data;
if (m_RenderBufSize == NAMCOS22_MAX_RENDER_CMD_SEQ)
{
draw_direct_poly(m_RenderBufData);
}
}
}
void namcos22_state::master_dsp_program(address_map &map)
{
map(0x0000, 0x0fff).rom(); /* internal ROM (4k words) */
map(0x4000, 0x7fff).rom().share("masterextram");
}
void namcos22_state::master_dsp_data(address_map &map)
{
map(0x1000, 0x3fff).ram();
map(0x4000, 0x7fff).r(FUNC(namcos22_state::master_external_ram_r)).w(FUNC(namcos22_state::master_external_ram_w));
map(0x8000, 0xffff).r(FUNC(namcos22_state::namcos22_dspram16_r)).w(FUNC(namcos22_state::namcos22_dspram16_w));
}
void namcos22_state::master_dsp_io(address_map &map)
{
map(0x0, 0x0).rw(FUNC(namcos22_state::point_loword_r), FUNC(namcos22_state::point_loword_iw));
map(0x1, 0x1).rw(FUNC(namcos22_state::point_hiword_ir), FUNC(namcos22_state::point_hiword_w));
map(0x2, 0x2).rw(FUNC(namcos22_state::pdp_begin_r), FUNC(namcos22_state::dsp_unk2_w));
map(0x3, 0x3).rw(FUNC(namcos22_state::dsp_unk_port3_r), FUNC(namcos22_state::point_address_w));
map(0x4, 0x4).nopw(); /* unknown */
map(0x7, 0x7).w(FUNC(namcos22_state::upload_code_to_slave_dsp_w));
map(0x8, 0x8).rw(FUNC(namcos22_state::dsp_unk8_r), FUNC(namcos22_state::dsp_unk8_w)); /* trigger irq? */
map(0x9, 0x9).r(FUNC(namcos22_state::custom_ic_status_r)).nopw(); /* trigger irq? */
map(0xa, 0xa).w(FUNC(namcos22_state::dsp_unk_porta_w));
map(0xb, 0xb).nopw(); /* RINT-related? */
map(0xc, 0xc).w(FUNC(namcos22_state::master_render_device_w));
map(0xd, 0xd).w(FUNC(namcos22_state::namcos22_dspram16_bank_w));
map(0xe, 0xe).w(FUNC(namcos22_state::dsp_led_w));
map(0xf, 0xf).r(FUNC(namcos22_state::dsp_upload_status_r)).nopw();
}
READ16_MEMBER(namcos22_state::dsp_bioz_r)
{
/* STUB */
return 1;
}
READ16_MEMBER(namcos22_state::dsp_slave_port3_r)
{
return 0x0010; /* ? */
}
READ16_MEMBER(namcos22_state::dsp_slave_port4_r)
{
return 0;
// return ReadDataFromSlaveBuf();
}
READ16_MEMBER(namcos22_state::dsp_slave_port5_r)
{
#if 0
int numWords = SlaveBufSize();
int mode = 2;
return (numWords<<4) | mode;
#endif
return 0;
}
READ16_MEMBER(namcos22_state::dsp_slave_port6_r)
{
/* bit 0x9 indicates whether device at port2 is ready to receive data */
/* bit 0xd indicates whether data is available from port4 */
return 0;
}
WRITE16_MEMBER(namcos22_state::dsp_slave_portc_w)
{
/* Unknown; used before transmitting a command sequence. */
}
READ16_MEMBER(namcos22_state::dsp_slave_port8_r)
{
/* This reports status of the device mapped at port 0xb. */
/* The slave dsp waits for bit 0x0001 to be zero before writing a new command sequence. */
return 0; /* status */
}
READ16_MEMBER(namcos22_state::dsp_slave_portb_r)
{
/* The slave DSP reads before transmitting a command sequence. */
return 0;
}
WRITE16_MEMBER(namcos22_state::dsp_slave_portb_w)
{
/* The slave dsp uses this to transmit a command sequence to an external device. */
}
void namcos22_state::slave_dsp_program(address_map &map)
{
map(0x0000, 0x0fff).rom(); /* internal ROM */
map(0x8000, 0x9fff).rom().share("slaveextram");
}
void namcos22_state::slave_dsp_data(address_map &map)
{
map(0x8000, 0x9fff).rw(FUNC(namcos22_state::slave_external_ram_r), FUNC(namcos22_state::slave_external_ram_w));
}
void namcos22_state::slave_dsp_io(address_map &map)
{
/* unknown signal */
map(0x3, 0x3).r(FUNC(namcos22_state::dsp_slave_port3_r));
map(0x4, 0x4).r(FUNC(namcos22_state::dsp_slave_port4_r));
map(0x5, 0x5).r(FUNC(namcos22_state::dsp_slave_port5_r));
map(0x6, 0x6).r(FUNC(namcos22_state::dsp_slave_port6_r)).nopw();
/* render device state */
map(0x8, 0x8).r(FUNC(namcos22_state::dsp_slave_port8_r)).nopw();
/* render device */
map(0xb, 0xb).rw(FUNC(namcos22_state::dsp_slave_portb_r), FUNC(namcos22_state::dsp_slave_portb_w));
map(0xc, 0xc).w(FUNC(namcos22_state::dsp_slave_portc_w));
}
/*********************************************************************************************/
/*
MCU memory map
--------------
000000-00027f: internal MCU registers and RAM
002000-002fff: C352 PCM chip
004000-00bfff: shared RAM with host CPU
00c000-00ffff: BIOS ROM (internal on System 22, external on Super)
200000-27ffff: data ROM
301000-301001: watchdog?
308000-308003: unknown (I/O?)
pin hookups
-----------
5 (IRQ0): C383 custom (probably vsync)
7 (IRQ2): 74F244 at 8c, pin 3
port assignments
----------------
port 4: "bankswitches" the controls read at port 5, probably other functions too
port 5: on read, digital controls (buttons, coins, start, service switch)
on write, various outputs (lamps, the fan in prop cycle, etc)
ADC : analog inputs
*/
// System 22 37702
READ16_MEMBER(namcos22_state::s22mcu_shared_r)
{
uint16_t *share16 = (uint16_t *)m_shareram.target();
return share16[BYTE_XOR_BE(offset)];
}
WRITE16_MEMBER(namcos22_state::s22mcu_shared_w)
{
uint16_t *share16 = (uint16_t *)m_shareram.target();
COMBINE_DATA(&share16[BYTE_XOR_BE(offset)]);
}
READ8_MEMBER(namcos22_state::mcu_port4_s22_r)
{
// for C74, 0x10 selects sound MCU role, 0x00 selects control-reading role
return 0x10;
}
READ8_MEMBER(namcos22_state::iomcu_port4_s22_r)
{
// for C74, 0x10 selects sound MCU role, 0x00 selects control-reading role
return 0x00;
}
void namcos22_state::mcu_s22_program(address_map &map)
{
map(0x002000, 0x002fff).rw("c352", FUNC(c352_device::read), FUNC(c352_device::write));
map(0x004000, 0x00bfff).rw(FUNC(namcos22_state::s22mcu_shared_r), FUNC(namcos22_state::s22mcu_shared_w));
map(0x080000, 0x0fffff).rom().region("mcu", 0);
map(0x200000, 0x27ffff).rom().region("mcu", 0);
map(0x280000, 0x2fffff).rom().region("mcu", 0);
map(0x301000, 0x301001).noprw(); // watchdog? LEDs?
map(0x308000, 0x308003).noprw(); // volume control IC?
}
void namcos22_state::iomcu_s22_program(address_map &map)
{
// is there any external memory or MMIO on this one?
}
void namcos22_state::mcu_s22_io(address_map &map)
{
map(M37710_PORT4, M37710_PORT4).r(FUNC(namcos22_state::mcu_port4_s22_r));
}
void namcos22_state::iomcu_s22_io(address_map &map)
{
map(M37710_PORT4, M37710_PORT4).r(FUNC(namcos22_state::iomcu_port4_s22_r));
map(0x00, 0xff).noprw();
}
// Super System 22 M37710
TIMER_DEVICE_CALLBACK_MEMBER(namcos22_state::mcu_irq)
{
int scanline = param;
/* TODO: real sources of these */
if (scanline == 480)
m_mcu->set_input_line(M37710_LINE_IRQ0, HOLD_LINE);
else if (scanline == 500)
m_mcu->set_input_line(M37710_LINE_ADC, HOLD_LINE);
else if (scanline == 0)
m_mcu->set_input_line(M37710_LINE_IRQ2, HOLD_LINE);
}
WRITE8_MEMBER(namcos22_state::mcu_port4_w)
{
m_p4 = data;
}
READ8_MEMBER(namcos22_state::mcu_port4_r)
{
return m_p4;
}
WRITE8_MEMBER(namcos22_state::mcu_port5_w)
{
;
}
READ8_MEMBER(namcos22_state::mcu_port5_r)
{
if (m_p4 & 8)
return m_mcup5a.read_safe(0xff);
else
return m_mcup5b.read_safe(0xff);
}
WRITE8_MEMBER(namcos22_state::mcu_port6_w)
{
;
}
READ8_MEMBER(namcos22_state::mcu_port6_r)
{
return 0;
}
WRITE8_MEMBER(namcos22_state::mcu_port7_w)
{
;
}
READ8_MEMBER(namcos22_state::mcu_port7_r)
{
return 0;
}
READ8_MEMBER(namcos22_state::namcos22s_mcu_adc_r)
{
uint16_t adc = m_adc_ports[offset >> 1 & 7].read_safe(0) << 2;
return (offset & 1) ? adc >> 8 : adc;
}
void namcos22_state::mcu_program(address_map &map)
{
map(0x002000, 0x002fff).rw("c352", FUNC(c352_device::read), FUNC(c352_device::write));
map(0x004000, 0x00bfff).rw(FUNC(namcos22_state::s22mcu_shared_r), FUNC(namcos22_state::s22mcu_shared_w));
map(0x00c000, 0x00ffff).rom().region("mcu", 0xc000);
map(0x080000, 0x0fffff).rom().region("mcu", 0);
map(0x200000, 0x27ffff).rom().region("mcu", 0);
map(0x280000, 0x2fffff).rom().region("mcu", 0);
map(0x301000, 0x301001).noprw(); // watchdog? LEDs?
map(0x308000, 0x308003).noprw(); // volume control IC?
}
void namcos22_state::mcu_io(address_map &map)
{
map(M37710_PORT4, M37710_PORT4).rw(FUNC(namcos22_state::mcu_port4_r), FUNC(namcos22_state::mcu_port4_w));
map(M37710_PORT5, M37710_PORT5).rw(FUNC(namcos22_state::mcu_port5_r), FUNC(namcos22_state::mcu_port5_w));
map(M37710_PORT6, M37710_PORT6).rw(FUNC(namcos22_state::mcu_port6_r), FUNC(namcos22_state::mcu_port6_w));
map(M37710_PORT7, M37710_PORT7).rw(FUNC(namcos22_state::mcu_port7_r), FUNC(namcos22_state::mcu_port7_w));
map(M37710_ADC0_L, M37710_ADC7_H).r(FUNC(namcos22_state::namcos22s_mcu_adc_r));
}
/*********************************************************************************************/
// custom input handling
/* TODO: REMOVE (THIS IS HANDLED BY "IOMCU") */
void namcos22_state::handle_coinage(int slots, int address_is_odd)
{
uint16_t *share16 = (uint16_t *)m_shareram.target();
uint32_t coin_state = ioport("INPUTS")->read() & 0x1200;
if (!(coin_state & 0x1000) && (m_old_coin_state & 0x1000))
{
m_credits1++;
}
if (!(coin_state & 0x0200) && (m_old_coin_state & 0x0200))
{
m_credits2++;
}
m_old_coin_state = coin_state;
share16[BYTE_XOR_LE(0x38/2)] = m_credits1 << (address_is_odd*8);
if (slots == 2)
{
share16[BYTE_XOR_LE(0x3e/2)] = m_credits2 << (address_is_odd*8);
}
}
/* TODO: REMOVE (THIS IS HANDLED BY "IOMCU") */
void namcos22_state::handle_driving_io()
{
if (m_syscontrol[0x18] != 0)
{
uint16_t flags = ioport("INPUTS")->read();
uint16_t coinram_address_is_odd = 0;
uint16_t gas = ioport("GAS")->read();
uint16_t brake = ioport("BRAKE")->read();
uint16_t steer = ioport("STEER")->read();
switch (m_gametype)
{
case NAMCOS22_RIDGE_RACER:
case NAMCOS22_RIDGE_RACER2:
gas <<= 3;
gas += 884;
brake <<= 3;
brake += 809;
steer <<= 4;
steer += 0x160;
break;
case NAMCOS22_RAVE_RACER:
gas <<= 3;
gas += 992;
brake <<= 3;
brake += 3008;
steer <<= 4;
steer += 32;
break;
case NAMCOS22_VICTORY_LAP:
coinram_address_is_odd = 1;
// (fall through)
case NAMCOS22_ACE_DRIVER:
gas <<= 3;
gas += 992;
brake <<= 3;
brake += 3008;
steer <<= 4;
steer += 2048;
break;
default:
gas <<= 3;
brake <<= 3;
steer <<= 4;
break;
}
handle_coinage(2, coinram_address_is_odd);
m_shareram[0x000/4] = 0x10 << 16; /* SUB CPU ready */
m_shareram[0x030/4] = (flags << 16) | steer;
m_shareram[0x034/4] = (gas << 16) | brake;
}
}
/* TODO: REMOVE (THIS IS HANDLED BY "IOMCU") */
void namcos22_state::handle_cybrcomm_io()
{
if (m_syscontrol[0x18] != 0)
{
uint16_t flags = ioport("INPUTS")->read();
uint16_t volume0 = ioport("STICKY1")->read() * 0x10;
uint16_t volume1 = ioport("STICKY2")->read() * 0x10;
uint16_t volume2 = ioport("STICKX1")->read() * 0x10;
uint16_t volume3 = ioport("STICKX2")->read() * 0x10;
m_shareram[0x030/4] = (flags << 16) | volume0;
m_shareram[0x034/4] = (volume1 << 16) | volume2;
m_shareram[0x038/4] = volume3 << 16;
handle_coinage(1, 0);
}
}
// Alpine skiing games
TIMER_DEVICE_CALLBACK_MEMBER(namcos22_state::alpine_steplock_callback)
{
m_motor_status = param;
}
WRITE8_MEMBER(namcos22_state::alpine_mcu_port5_w)
{
// bits 1+2 are steplock motor outputs
if ((data & 6) == 6)
{
if (m_motor_status == 2)
{
// free steps
m_motor_status = 0;
m_motor_timer->adjust(attotime::from_msec(500), 1);
}
}
else if (data & 4)
{
if (m_motor_status == 1)
{
// lock steps
m_motor_status = 0;
m_motor_timer->adjust(attotime::from_msec(500), 2);
}
}
}
void namcos22_state::alpine_io_map(address_map &map)
{
mcu_io(map);
map(M37710_PORT5, M37710_PORT5).w(FUNC(namcos22_state::alpine_mcu_port5_w));
}
// Prop Cycle
WRITE8_MEMBER(namcos22_state::propcycle_mcu_port5_w)
{
// prop cycle outputs:
// bit 1 = fan
// bit 2 = button light
output().set_value("fan0", data & 1);
m_led = BIT(data, 1);
}
void namcos22_state::propcycl_io_map(address_map &map)
{
mcu_io(map);
map(M37710_PORT5, M37710_PORT5).w(FUNC(namcos22_state::propcycle_mcu_port5_w));
}
TIMER_DEVICE_CALLBACK_MEMBER(namcos22_state::propcycl_pedal_interrupt)
{
m_mcu->pulse_input_line(M37710_LINE_TIMERA3TICK, m_mcu->minimum_quantum_time());
}
TIMER_DEVICE_CALLBACK_MEMBER(namcos22_state::propcycl_pedal_update)
{
// arbitrary timer for reading optical pedal
uint8_t i = ioport("PEDAL")->read();
if (i != 0)
{
// the pedal has a simple 1-bit "light interrupted" sensor. the faster you pedal,
// the faster it pulses. this is connected to the clock input for timer A3,
// and timer A3 is configured by the MCU program to cause an interrupt each time
// it's clocked. by counting the number of interrupts in a frame, we can determine
// how fast the user is pedaling.
// these values(in usec) may need tweaking:
const int base = 1000;
const int range = 10000;
attotime freq = attotime::from_usec(base + range * (1.0 / (double)i));
m_pc_pedal_interrupt->adjust(std::min(freq, m_pc_pedal_interrupt->time_left()), 0, freq);
}
else
{
// not moving
m_pc_pedal_interrupt->adjust(attotime::never, 0, attotime::never);
}
}
// Armadillo Racing
TIMER_CALLBACK_MEMBER(namcos22_state::adillor_trackball_interrupt)
{
m_mcu->pulse_input_line(param ? M37710_LINE_TIMERA2TICK : M37710_LINE_TIMERA3TICK, m_mcu->minimum_quantum_time());
}
TIMER_DEVICE_CALLBACK_MEMBER(namcos22_state::adillor_trackball_update)
{
// arbitrary timer for reading optical trackball
uint8_t ix = ioport("TRACKX")->read();
uint8_t iy = ioport("TRACKY")->read();
if (ix != 0x80 || iy < 0x80)
{
if (iy >= 0x80)
iy = 0x7f;
double x = (double)(ix - 0x80) / 127.0;
double y = (double)(0x80 - iy) / 127.0;
// normalize
double a = atan(x/y);
double p = sqrt(x*x + y*y);
double v = (fabs(a) < (M_PI / 4.0)) ? p*cos(a) : p*sin(a);
v = fabs(v);
// note that it is rotated by 45 degrees, so instead of axes like (+), they are like (x)
a += (M_PI / 4.0);
if (a < 0)
a = 0;
else if (a > (M_PI / 2.0))
a = M_PI / 2.0;
// tied to mcu A2/A3 timer (speed determines frequency)
// these values(in usec) may need tweaking:
const int base = 1000;
const int range = 5000;
double t[2];
t[0] = v*sin(a); // y -> A2
t[1] = v*cos(a); // x -> A3
for (int axis = 0; axis < 2; axis++)
{
if (t[axis] > (1.0 / (double)(range)))
{
attotime freq = attotime::from_usec((base + range) - ((double)(range) * t[axis]));
m_ar_tb_interrupt[axis]->adjust(std::min(freq, m_ar_tb_interrupt[axis]->remaining()), axis, freq);
}
else
{
// not moving
m_ar_tb_interrupt[axis]->adjust(attotime::never, axis, attotime::never);
}
}
}
else
{
// both axes not moving
for (int axis = 0; axis < 2; axis++)
{
m_ar_tb_interrupt[axis]->adjust(attotime::never, axis, attotime::never);
}
}
}
/*********************************************************************************************/
static INPUT_PORTS_START( ridgera )
PORT_START("INPUTS")
/* 1 3 5 When the cabinet is set to Deluxe, the stick shift is basically
|-|-| an 8-way joystick that locks into place.
2 4 6 Standard (default) setup uses a racing shifter like in Ace Driver. */
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_NAME("Shift Down")
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_NAME("Shift Up")
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_NAME("Shift Left") // not used in Standard Cabinet
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT) PORT_NAME("Shift Right") // not used in Standard Cabinet
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("Clutch Pedal") // not used in Standard Cabinet
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_CONFNAME( 0x0100, 0x0000, DEF_STR( Cabinet ) ) // @ JAMMA pins
PORT_CONFSETTING( 0x0000, DEF_STR( Standard ) )
PORT_CONFSETTING( 0x0100, "Deluxe" )
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_SERVICE3 ) // also service mode?
PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("DSW0")
PORT_SERVICE_DIPLOC( 0x0001, IP_ACTIVE_LOW, "SW2:1")
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW2:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW2:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW2:4" )
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW2:5" )
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW2:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW2:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW2:8" )
PORT_DIPUNKNOWN_DIPLOC( 0x0100, 0x0100, "SW3:1" )
PORT_DIPUNKNOWN_DIPLOC( 0x0200, 0x0200, "SW3:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0400, 0x0400, "SW3:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0800, 0x0800, "SW3:4" )
PORT_DIPUNKNOWN_DIPLOC( 0x1000, 0x1000, "SW3:5" )
PORT_DIPUNKNOWN_DIPLOC( 0x2000, 0x2000, "SW3:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x4000, 0x4000, "SW3:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x8000, 0x8000, "SW3:8" )
PORT_START("GAS")
PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Gas Pedal")
PORT_START("BRAKE")
PORT_BIT( 0xff, 0x00, IPT_PEDAL2 ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Brake Pedal")
PORT_START("STEER")
PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Steering Wheel")
INPUT_PORTS_END
static INPUT_PORTS_START( ridgeracf )
PORT_INCLUDE( ridgera )
PORT_MODIFY("INPUTS")
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("Ignition Key")
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_NAME("AT Switch")
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_NAME("MT Switch")
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_SERVICE2 )
PORT_SERVICE( 0x0400, IP_ACTIVE_LOW )
// DIP3-1 to DIP3-3 are for setting up the viewing angle (game used one board per screen?)
// Some of the other dipswitches are for debugging, like with Ridge Racer 2.
PORT_MODIFY("DSW0")
PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0000, "SW2:1" ) // always on?
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0000, "SW2:2" ) // always on?
PORT_DIPNAME( 0x8000, 0x8000, "Test Mode" ) PORT_DIPLOCATION("SW3:8")
PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
INPUT_PORTS_END
static INPUT_PORTS_START( ridgera2 )
PORT_INCLUDE( ridgera )
PORT_MODIFY("INPUTS")
PORT_CONFNAME( 0x2100, 0x2000, DEF_STR( Cabinet ) ) // @ JAMMA pins
PORT_CONFSETTING( 0x0000, "50 Inch" )
PORT_CONFSETTING( 0x0100, "Twin" )
PORT_CONFSETTING( 0x2000, DEF_STR( Standard ) )
PORT_CONFSETTING( 0x2100, "Deluxe" )
/* Some dipswitches seem to be for debug purposes, for example:
2-4 : background drawing related
2-5 : background drawing related
2-6 : debug link-up
2-8 : no game over when time runs out (cheat)
3-7 : debug polygons
*/
PORT_MODIFY("DSW0")
PORT_DIPNAME( 0x8000, 0x8000, "Test Mode" ) PORT_DIPLOCATION("SW3:8")
PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
INPUT_PORTS_END
static INPUT_PORTS_START( raveracw )
PORT_INCLUDE( ridgera )
PORT_MODIFY("INPUTS")
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("View Change")
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_UNKNOWN ) // no coin2
PORT_CONFNAME( 0x2100, 0x2000, DEF_STR( Cabinet ) ) // @ JAMMA pins
PORT_CONFSETTING( 0x0000, "50 Inch" )
PORT_CONFSETTING( 0x0100, "Twin" )
PORT_CONFSETTING( 0x2000, DEF_STR( Standard ) )
PORT_CONFSETTING( 0x2100, "Deluxe" )
INPUT_PORTS_END
static INPUT_PORTS_START( cybrcomm )
PORT_START("INPUTS")
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Gun Trigger") // placed on both sticks
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("Missile Button") // placed on both sticks
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("View Change")
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_SERVICE( 0x0400, IP_ACTIVE_LOW )
PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
/* Note(s)
The ranges here are based on the test mode which displays +-224
The eeprom is calibrated using these settings. If the SUBCPU handling changes then these might
end up needing to change again too
Default key arrangement is based on dual-joystick 'Tank' arrangement found in Assault and CyberSled
*/
PORT_START("STICKY1") /* VOLUME 0 */
PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_Y ) PORT_MINMAX(0x47,0xb7) /* range based on test mode */ PORT_CODE_DEC(KEYCODE_I) PORT_CODE_INC(KEYCODE_K) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2) /* right joystick: vertical */
PORT_START("STICKY2") /* VOLUME 0 */
PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_Y ) PORT_MINMAX(0x47,0xb7) /* range based on test mode */ PORT_CODE_DEC(KEYCODE_E) PORT_CODE_INC(KEYCODE_D) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1) /* left joystick: vertical */
PORT_START("STICKX1") /* VOLUME 0 */
PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_X ) PORT_MINMAX(0x47,0xb7) /* range based on test mode */ PORT_CODE_DEC(KEYCODE_J) PORT_CODE_INC(KEYCODE_L) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2) /* right joystick: horizontal */
PORT_START("STICKX2") /* VOLUME 0 */
PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_X ) PORT_MINMAX(0x47,0xb7) /* range based on test mode */ PORT_CODE_DEC(KEYCODE_S) PORT_CODE_INC(KEYCODE_F) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1) /* left joystick: horizontal */
PORT_START("DSW0")
PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW2:1" )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW2:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW2:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW2:4" )
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW2:5" )
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW2:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW2:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW2:8" )
PORT_DIPUNKNOWN_DIPLOC( 0x0100, 0x0100, "SW3:1" )
PORT_DIPUNKNOWN_DIPLOC( 0x0200, 0x0200, "SW3:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0400, 0x0400, "SW3:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0800, 0x0800, "SW3:4" )
PORT_DIPUNKNOWN_DIPLOC( 0x1000, 0x1000, "SW3:5" )
PORT_DIPUNKNOWN_DIPLOC( 0x2000, 0x2000, "SW3:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x4000, 0x4000, "SW3:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x8000, 0x8000, "SW3:8" )
INPUT_PORTS_END
static INPUT_PORTS_START( acedrvr )
PORT_START("INPUTS")
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_NAME("Shift Down")
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_NAME("Shift Up")
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("View Change")
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("Motion-Stop")
PORT_START("P1")
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) PORT_NAME("Dev Service Enter")
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2) PORT_NAME("Dev Service Up")
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2) PORT_NAME("Dev Service Down")
PORT_BIT( 0xff3e, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("DSW0")
PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW2:1" )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW2:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW2:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW2:4" )
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW2:5" )
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW2:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW2:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW2:8" )
PORT_DIPUNKNOWN_DIPLOC( 0x0100, 0x0100, "SW3:1" )
PORT_DIPUNKNOWN_DIPLOC( 0x0200, 0x0200, "SW3:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0400, 0x0400, "SW3:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0800, 0x0800, "SW3:4" )
PORT_DIPUNKNOWN_DIPLOC( 0x1000, 0x1000, "SW3:5" )
PORT_DIPUNKNOWN_DIPLOC( 0x2000, 0x2000, "SW3:6" )
PORT_DIPNAME( 0x4000, 0x4000, "Test Mode?" ) PORT_DIPLOCATION("SW3:7")
PORT_DIPSETTING( 0x4000, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_DIPNAME( 0x8000, 0x8000, "Test Mode?" ) PORT_DIPLOCATION("SW3:8")
PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_START("GAS")
PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Gas Pedal")
PORT_START("BRAKE")
PORT_BIT( 0xff, 0x00, IPT_PEDAL2 ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Brake Pedal")
PORT_START("STEER")
PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Steering Wheel")
INPUT_PORTS_END
static INPUT_PORTS_START( victlap )
PORT_INCLUDE( acedrvr )
PORT_MODIFY("P1")
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2) PORT_NAME("Dev Service Up")
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2) PORT_NAME("Dev Service Down")
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) PORT_NAME("Dev Service Enter")
PORT_BIT( 0xfe3f, IP_ACTIVE_LOW, IPT_UNKNOWN )
INPUT_PORTS_END
/*********************************************************************************************/
CUSTOM_INPUT_MEMBER(namcos22_state::alpine_motor_read)
{
return m_motor_status >> (uintptr_t)param & 1;
}
static INPUT_PORTS_START( alpiner )
PORT_START("DSW0")
PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW4:1" )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START("MCUP5A")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_SERVICE( 0x08, IP_ACTIVE_LOW )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 ) // Decision / View Change
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_16WAY // L Selection
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT) PORT_16WAY // R Selection
PORT_BIT( 0x80, IP_ACTIVE_HIGH,IPT_CUSTOM ) PORT_CUSTOM_MEMBER(DEVICE_SELF, namcos22_state,alpine_motor_read, (void *)0) // steps are free
PORT_START("MCUP5B")
PORT_BIT( 0x01, IP_ACTIVE_HIGH,IPT_CUSTOM ) PORT_CUSTOM_MEMBER(DEVICE_SELF, namcos22_state,alpine_motor_read, (void *)1) // steps are locked
PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("ADC.0")
PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_SENSITIVITY(100) PORT_KEYDELTA(4) PORT_NAME("Steps Swing")
PORT_START("ADC.1")
PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(4) PORT_NAME("Steps Edge")
INPUT_PORTS_END
static INPUT_PORTS_START( airco22 )
PORT_START("DSW0")
PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW4:1" )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START("MCUP5A")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_SERVICE( 0x08, IP_ACTIVE_LOW )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 ) /* Missile */
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 ) /* Gun */
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("MCUP5B")
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("ADC.0")
PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_MINMAX(0x40, 0xc0) PORT_SENSITIVITY(100) PORT_KEYDELTA(4)
PORT_START("ADC.1")
PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_MINMAX(0x40, 0xc0) PORT_SENSITIVITY(100) PORT_KEYDELTA(4)
PORT_START("ADC.2")
PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Z ) PORT_MINMAX(0x40, 0xc0) PORT_SENSITIVITY(100) PORT_KEYDELTA(4)
INPUT_PORTS_END
static INPUT_PORTS_START( cybrcycc )
PORT_START("DSW0")
PORT_DIPNAME( 0x0001, 0x0001, "Test Mode?" ) PORT_DIPLOCATION("SW4:1")
PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START("MCUP5A")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_SERVICE( 0x08, IP_ACTIVE_LOW )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 ) // also view-change function
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("MCUP5B")
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("ADC.0")
PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Steering Wheel")
PORT_START("ADC.1")
PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Gas Pedal")
PORT_START("ADC.2")
PORT_BIT( 0xff, 0x00, IPT_PEDAL2 ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Brake Pedal")
INPUT_PORTS_END
static INPUT_PORTS_START( dirtdash )
PORT_START("DSW0")
PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW4:1" )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START("MCUP5A")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_SERVICE( 0x08, IP_ACTIVE_LOW )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("View Change")
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_NAME("Shift Up")
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_NAME("Shift Down")
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("Motion-Stop")
PORT_START("MCUP5B")
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("ADC.0")
PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_SENSITIVITY(100) PORT_KEYDELTA(3) PORT_NAME("Steering Wheel")
PORT_START("ADC.1")
PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Gas Pedal")
PORT_START("ADC.2")
PORT_BIT( 0xff, 0x00, IPT_PEDAL2 ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Brake Pedal")
INPUT_PORTS_END
static INPUT_PORTS_START( tokyowar )
PORT_START("DSW0")
PORT_DIPNAME( 0x0001, 0x0001, "Test Mode?" ) PORT_DIPLOCATION("SW4:1")
PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START("MCUP5A")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_SERVICE( 0x08, IP_ACTIVE_LOW )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 ) // also view-change function
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_NAME("Right Trigger")
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("Left Trigger")
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("MCUP5B")
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("ADC.0")
PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Steering Wheel")
PORT_START("ADC.2")
PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Gas Pedal")
PORT_START("ADC.3")
PORT_BIT( 0xff, 0x00, IPT_PEDAL2 ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Brake Pedal")
INPUT_PORTS_END
static INPUT_PORTS_START( aquajet )
PORT_START("DSW0")
PORT_DIPNAME( 0x0001, 0x0001, "Test Mode?" ) PORT_DIPLOCATION("SW4:1")
PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START("MCUP5A")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_SERVICE( 0x08, IP_ACTIVE_LOW )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("MCUP5B")
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("ADC.0")
PORT_BIT( 0xff, 0x7f, IPT_PADDLE ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_REVERSE
PORT_START("ADC.1")
PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_MINMAX(0x00, 0x80) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_REVERSE
PORT_START("ADC.2")
PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_Y ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_REVERSE
INPUT_PORTS_END
static INPUT_PORTS_START( adillor )
PORT_START("DSW0")
PORT_DIPNAME( 0x0001, 0x0001, "Test Mode?" ) PORT_DIPLOCATION("SW4:1")
PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_START("P1")
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) PORT_NAME("Dev Service Enter")
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2) PORT_NAME("Dev Service Exit")
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2) PORT_NAME("Dev Service Left")
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2) PORT_NAME("Dev Service Right") // when in normal testmode, press this to enter the extra testmode
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2) PORT_NAME("Dev Service Up")
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2) PORT_NAME("Dev Service Down")
PORT_BIT( 0xffc0, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("MCUP5A")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_SERVICE( 0x08, IP_ACTIVE_LOW )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("MCUP5B")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
PORT_BIT( 0xfe, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("TRACKX")
PORT_BIT( 0xff, 0x80, IPT_AD_STICK_X ) PORT_MINMAX(0x01, 0xff) PORT_SENSITIVITY(100) PORT_KEYDELTA(20) PORT_NAME("Trackball X")
PORT_START("TRACKY")
PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_MINMAX(0x01, 0xff) PORT_SENSITIVITY(100) PORT_KEYDELTA(20) PORT_NAME("Trackball Y")
INPUT_PORTS_END
static INPUT_PORTS_START( propcycl )
PORT_START("DSW0")
PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW4:1" )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x0080,