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mips1: bc2/bc3 always work (nw)

BCzF/BCzT can be used (by reading input lines) when coprocessor 2 or 3 are enabled, even when there's no real coprocessor hardware.
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pmackinlay committed Mar 1, 2019
1 parent f7276e6 commit 85f865a782ef99e3d0da73d7a05a5eaad1f1fdb4
Showing with 64 additions and 2 deletions.
  1. +64 −2 src/devices/cpu/mips/mips1.cpp
@@ -955,13 +955,75 @@ void mips1core_device_base::handle_cop1(u32 const op)

void mips1core_device_base::handle_cop2(u32 const op)
{
if (!(SR & SR_COP2))
if (SR & SR_COP2)
{
switch (RSREG)
{
case 0x08: // BC2
switch (RTREG)
{
case 0x00: // BC2F
if (!m_in_brcond[2]())
{
m_branch_state = BRANCH;
m_branch_target = m_pc + 4 + (s32(SIMMVAL) << 2);
}
break;
case 0x01: // BC2T
if (m_in_brcond[2]())
{
m_branch_state = BRANCH;
m_branch_target = m_pc + 4 + (s32(SIMMVAL) << 2);
}
break;
default:
generate_exception(EXCEPTION_INVALIDOP);
break;
}
break;
default:
generate_exception(EXCEPTION_INVALIDOP);
break;
}
}
else
generate_exception(EXCEPTION_BADCOP2);
}

void mips1core_device_base::handle_cop3(u32 const op)
{
if (!(SR & SR_COP3))
if (SR & SR_COP3)
{
switch (RSREG)
{
case 0x08: // BC3
switch (RTREG)
{
case 0x00: // BC3F
if (!m_in_brcond[3]())
{
m_branch_state = BRANCH;
m_branch_target = m_pc + 4 + (s32(SIMMVAL) << 2);
}
break;
case 0x01: // BC3T
if (m_in_brcond[3]())
{
m_branch_state = BRANCH;
m_branch_target = m_pc + 4 + (s32(SIMMVAL) << 2);
}
break;
default:
generate_exception(EXCEPTION_INVALIDOP);
break;
}
break;
default:
generate_exception(EXCEPTION_INVALIDOP);
break;
}
}
else
generate_exception(EXCEPTION_BADCOP3);
}

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