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New working machine

-----------
Rebound [DICE team, Couriersud]
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couriersud committed Mar 10, 2019
1 parent 68c97d0 commit e80276bb23b25b7e2a6772e737cebbf57487326f
@@ -1198,6 +1198,8 @@ files {
MAME_DIR .. "src/mame/machine/nl_pongd.h",
MAME_DIR .. "src/mame/machine/nl_breakout.cpp",
MAME_DIR .. "src/mame/machine/nl_breakout.h",
MAME_DIR .. "src/mame/machine/nl_rebound.cpp",
MAME_DIR .. "src/mame/machine/nl_rebound.h",
MAME_DIR .. "src/mame/drivers/poolshrk.cpp",
MAME_DIR .. "src/mame/includes/poolshrk.h",
MAME_DIR .. "src/mame/audio/poolshrk.cpp",
@@ -128,6 +128,8 @@ files{
MAME_DIR .. "src/mame/machine/nl_pongd.h",
MAME_DIR .. "src/mame/machine/nl_breakout.cpp",
MAME_DIR .. "src/mame/machine/nl_breakout.h",
MAME_DIR .. "src/mame/machine/nl_rebound.cpp",
MAME_DIR .. "src/mame/machine/nl_rebound.h",
MAME_DIR .. "src/mame/machine/nl_hazelvid.cpp",
MAME_DIR .. "src/mame/machine/nl_hazelvid.h",

@@ -66,7 +66,7 @@ hpc_disassembler::hpc_disassembler(const char *const regs[])
{
}

u32 hpc_disassembler::opcode_alignment() const
util::u32 hpc_disassembler::opcode_alignment() const
{
return 1;
}
@@ -79,7 +79,7 @@ void hpc_disassembler::format_register(std::ostream &stream, u16 reg) const
if (name != nullptr)
{
stream << name;
if (BIT(reg, 0))
if (util::BIT(reg, 0))
stream << "+1";
return;
}
@@ -160,7 +160,7 @@ void hpc_disassembler::disassemble_unary_op(std::ostream &stream, const char *op

void hpc_disassembler::disassemble_bit_op(std::ostream &stream, const char *op, u8 bit, u16 offset, u16 src, bool indir, bool idx) const
{
if (src >= 0x00c0 && src < 0x01c0 && BIT(src, 0) && !indir && m_regs[(src - 0x00c0) >> 1] != nullptr)
if (src >= 0x00c0 && src < 0x01c0 && util::BIT(src, 0) && !indir && m_regs[(src - 0x00c0) >> 1] != nullptr)
{
src &= 0xfffe;
bit += 8;
@@ -178,7 +178,7 @@ void hpc_disassembler::disassemble_bit_op(std::ostream &stream, const char *op,
stream << "].b";
}

offs_t hpc_disassembler::disassemble(std::ostream &stream, offs_t pc, const hpc_disassembler::data_buffer &opcodes, const hpc_disassembler::data_buffer &params)
util::disasm_interface::offs_t hpc_disassembler::disassemble(std::ostream &stream, util::disasm_interface::offs_t pc, const hpc_disassembler::data_buffer &opcodes, const hpc_disassembler::data_buffer &params)
{
u8 opcode = opcodes.r8(pc);
u16 reg = REGISTER_A;
@@ -253,7 +253,7 @@ offs_t hpc_disassembler::disassemble(std::ostream &stream, offs_t pc, const hpc_
case 0xa0:
dmode = true;
indir = false;
if (BIT(opcode, 1))
if (util::BIT(opcode, 1))
imm = true;

src = opcodes.r8(pc + 1);
@@ -266,7 +266,7 @@ offs_t hpc_disassembler::disassemble(std::ostream &stream, offs_t pc, const hpc_
case 0xa4:
dmode = true;
indir = false;
if (BIT(opcode, 1))
if (util::BIT(opcode, 1))
imm = true;

src = (opcodes.r8(pc + 1) << 8) | opcodes.r8(pc + 2);
@@ -279,7 +279,7 @@ offs_t hpc_disassembler::disassemble(std::ostream &stream, offs_t pc, const hpc_
case 0xa1:
dmode = true;
indir = false;
if (BIT(opcode, 1))
if (util::BIT(opcode, 1))
imm = true;

src = opcodes.r8(pc + 1);
@@ -300,7 +300,7 @@ offs_t hpc_disassembler::disassemble(std::ostream &stream, offs_t pc, const hpc_
case 0xa5:
dmode = true;
indir = false;
if (BIT(opcode, 1))
if (util::BIT(opcode, 1))
imm = true;

src = (opcodes.r8(pc + 1) << 8) | opcodes.r8(pc + 2);
@@ -583,17 +583,17 @@ offs_t hpc_disassembler::disassemble(std::ostream &stream, offs_t pc, const hpc_
case 0xd4:
case 0xe4:
case 0xf4:
disassemble_op(stream, "ld", reg, src, imm, indir, idx, BIT(opcode, 5));
disassemble_op(stream, "ld", reg, src, imm, indir, idx, util::BIT(opcode, 5));
break;

case 0x89:
case 0xa9:
disassemble_unary_op(stream, "inc", reg, src, indir, idx, BIT(opcode, 5));
disassemble_unary_op(stream, "inc", reg, src, indir, idx, util::BIT(opcode, 5));
break;

case 0x8a:
case 0xaa:
disassemble_unary_op(stream, "decsz", reg, src, indir, idx, BIT(opcode, 5));
disassemble_unary_op(stream, "decsz", reg, src, indir, idx, util::BIT(opcode, 5));
bytes |= STEP_OVER | (1 << OVERINSTSHIFT);
break;

@@ -603,7 +603,7 @@ offs_t hpc_disassembler::disassemble(std::ostream &stream, offs_t pc, const hpc_
case 0xd6:
case 0xe6:
case 0xf6:
disassemble_op(stream, dmode ? "ld" : "st", reg, src, imm, indir, idx, BIT(opcode, 5));
disassemble_op(stream, dmode ? "ld" : "st", reg, src, imm, indir, idx, util::BIT(opcode, 5));
break;

case 0x8d:
@@ -619,7 +619,7 @@ offs_t hpc_disassembler::disassemble(std::ostream &stream, offs_t pc, const hpc_
case 0xd5:
case 0xe5:
case 0xf5:
disassemble_op(stream, "x", reg, src, imm, indir, idx, BIT(opcode, 5));
disassemble_op(stream, "x", reg, src, imm, indir, idx, util::BIT(opcode, 5));
break;

case 0x94: case 0x95:
@@ -631,35 +631,35 @@ offs_t hpc_disassembler::disassemble(std::ostream &stream, offs_t pc, const hpc_
break;

case 0x98: case 0xb8: case 0xd8: case 0xf8:
disassemble_op(stream, "add", reg, src, imm, indir, idx, BIT(opcode, 5));
disassemble_op(stream, "add", reg, src, imm, indir, idx, util::BIT(opcode, 5));
break;

case 0x99: case 0xb9: case 0xd9: case 0xf9:
disassemble_op(stream, "and", reg, src, imm, indir, idx, BIT(opcode, 5));
disassemble_op(stream, "and", reg, src, imm, indir, idx, util::BIT(opcode, 5));
break;

case 0x9a: case 0xba: case 0xda: case 0xfa:
disassemble_op(stream, "or", reg, src, imm, indir, idx, BIT(opcode, 5));
disassemble_op(stream, "or", reg, src, imm, indir, idx, util::BIT(opcode, 5));
break;

case 0x9b: case 0xbb: case 0xdb: case 0xfb:
disassemble_op(stream, "xor", reg, src, imm, indir, idx, BIT(opcode, 5));
disassemble_op(stream, "xor", reg, src, imm, indir, idx, util::BIT(opcode, 5));
break;

case 0x9c: case 0xbc: case 0xdc: case 0xfc:
disassemble_op(stream, "ifeq", reg, src, imm, indir, idx, BIT(opcode, 5));
disassemble_op(stream, "ifeq", reg, src, imm, indir, idx, util::BIT(opcode, 5));
break;

case 0x9d: case 0xbd: case 0xdd: case 0xfd:
disassemble_op(stream, "ifgt", reg, src, imm, indir, idx, BIT(opcode, 5));
disassemble_op(stream, "ifgt", reg, src, imm, indir, idx, util::BIT(opcode, 5));
break;

case 0x9e: case 0xbe: case 0xde: case 0xfe:
disassemble_op(stream, "mult", reg, src, imm, indir, idx, BIT(opcode, 5));
disassemble_op(stream, "mult", reg, src, imm, indir, idx, util::BIT(opcode, 5));
break;

case 0x9f: case 0xbf: case 0xdf: case 0xff:
disassemble_op(stream, "div", reg, src, imm, indir, idx, BIT(opcode, 5));
disassemble_op(stream, "div", reg, src, imm, indir, idx, util::BIT(opcode, 5));
break;

case 0xa7:
@@ -694,65 +694,65 @@ offs_t hpc_disassembler::disassemble(std::ostream &stream, offs_t pc, const hpc_
case 0xc0: case 0xc2:
case 0xe0: case 0xe2:
util::stream_format(stream, "%-8sA,[B%c].%c", "lds",
BIT(opcode, 1) ? '-' : '+',
BIT(opcode, 5) ? 'w' : 'b');
util::BIT(opcode, 1) ? '-' : '+',
util::BIT(opcode, 5) ? 'w' : 'b');
bytes |= STEP_OVER | (1 << OVERINSTSHIFT);
break;

case 0xd0: case 0xd2:
case 0xf0: case 0xf2:
util::stream_format(stream, "%-8sA,[X%c].%c", "ld",
BIT(opcode, 1) ? '-' : '+',
BIT(opcode, 5) ? 'w' : 'b');
util::BIT(opcode, 1) ? '-' : '+',
util::BIT(opcode, 5) ? 'w' : 'b');
break;

case 0xc1: case 0xc3:
case 0xe1: case 0xe3:
util::stream_format(stream, "%-8sA,[B%c].%c", "xs",
BIT(opcode, 1) ? '-' : '+',
BIT(opcode, 5) ? 'w' : 'b');
util::BIT(opcode, 1) ? '-' : '+',
util::BIT(opcode, 5) ? 'w' : 'b');
bytes |= STEP_OVER | (1 << OVERINSTSHIFT);
break;

case 0xd1: case 0xd3:
case 0xf1: case 0xf3:
util::stream_format(stream, "%-8sA,[X%c].%c", "x",
BIT(opcode, 1) ? '-' : '+',
BIT(opcode, 5) ? 'w' : 'b');
util::BIT(opcode, 1) ? '-' : '+',
util::BIT(opcode, 5) ? 'w' : 'b');
break;

case 0xc7: case 0xe7:
util::stream_format(stream, "%-8sA", BIT(opcode, 5) ? "shl" : "shr");
util::stream_format(stream, "%-8sA", util::BIT(opcode, 5) ? "shl" : "shr");
break;

case 0xd7: case 0xf7:
util::stream_format(stream, "%-8sA", BIT(opcode, 5) ? "rlc" : "rrc");
util::stream_format(stream, "%-8sA", util::BIT(opcode, 5) ? "rlc" : "rrc");
break;

case 0xc8: case 0xe8:
disassemble_op(stream, "adc", reg, src, imm, indir, idx, BIT(opcode, 5));
disassemble_op(stream, "adc", reg, src, imm, indir, idx, util::BIT(opcode, 5));
break;

case 0xc9: case 0xe9:
disassemble_op(stream, "dadc", reg, src, imm, indir, idx, BIT(opcode, 5));
disassemble_op(stream, "dadc", reg, src, imm, indir, idx, util::BIT(opcode, 5));
break;

case 0xca: case 0xea:
disassemble_op(stream, "dsubc", reg, src, imm, indir, idx, BIT(opcode, 5));
disassemble_op(stream, "dsubc", reg, src, imm, indir, idx, util::BIT(opcode, 5));
break;

case 0xcb: case 0xeb:
disassemble_op(stream, "subc", reg, src, imm, indir, idx, BIT(opcode, 5));
disassemble_op(stream, "subc", reg, src, imm, indir, idx, util::BIT(opcode, 5));
break;

case 0xcc: case 0xec:
stream << "jid";
if (BIT(opcode, 5))
if (util::BIT(opcode, 5))
stream << "w";
break;

case 0xcf: case 0xef:
disassemble_op(stream, "divd", reg, src, imm, indir, idx, BIT(opcode, 5));
disassemble_op(stream, "divd", reg, src, imm, indir, idx, util::BIT(opcode, 5));
break;

default:
@@ -271,7 +271,10 @@ NETDEV_ANALOG_CALLBACK_MEMBER(fixedfreq_device::update_composite_monochrome)
int colv = (int) ((data - m_sync_threshold) * m_gain * 255.0);
if (colv > 255)
colv = 255;
m_col = rgb_t(colv, colv, colv);
if (colv < 0)
m_col = rgb_t(255, 0, 0);
else
m_col = rgb_t(colv, colv, colv);
}

NETDEV_ANALOG_CALLBACK_MEMBER(fixedfreq_device::update_red)
@@ -45,6 +45,7 @@ class fixedfreq_device : public device_t, public device_video_interface
m_vsync = sync;
m_vbackporch = backporch;
}
void set_horz_scale(int hscale) { m_hscale = hscale; }

// pre-defined configurations
void set_mode_ntsc720() //ModeLine "720x480@30i" 13.5 720 736 799 858 480 486 492 525 interlace -hsync -vsync
@@ -147,7 +147,9 @@ namespace netlist
{
// FIXME: assumes GND is connected to 0V.

if (!m_RESET() && m_last_reset)
const auto reset = m_RESET();

if (!reset && m_last_reset)
{
m_ff = false;
}
@@ -163,7 +165,7 @@ namespace netlist
m_ff = false;
}

const bool out = (!m_RESET() ? false : m_ff);
const bool out = (!reset ? false : m_ff);

if (m_last_out && !out)
{
@@ -178,7 +180,7 @@ namespace netlist
m_OUT.push(m_R1.m_P());
m_RDIS.set_R(R_OFF);
}
m_last_reset = m_RESET();
m_last_reset = reset;
m_last_out = out;
}

@@ -12,6 +12,8 @@ static NETLIST_START(diode_models)
NET_MODEL("D _(IS=1e-15 N=1)")

NET_MODEL("1N914 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)")
// FIXME: 1N916 currently only a copy of 1N914!
NET_MODEL("1N916 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)")
NET_MODEL("1N4001 D(Is=14.11n N=1.984 Rs=33.89m Ikf=94.81 Xti=3 Eg=1.11 Cjo=25.89p M=.44 Vj=.3245 Fc=.5 Bv=75 Ibv=10u Tt=5.7u Iave=1 Vpk=50 mfg=GI type=silicon)")
NET_MODEL("1N4148 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)")
NET_MODEL("1S1588 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75)")
@@ -112,8 +112,8 @@ struct CapacitorDesc : public SeriesRCDesc
#define CHIP(n, t) TTL_ ## t ## _DIP(n)

#define OHM(x) x
#define K_OHM(x) RES_K(X)
#define M_OHM(x) RES_M(X)
#define K_OHM(x) RES_K(x)
#define M_OHM(x) RES_M(x)
#define U_FARAD(x) CAP_U(x)
#define N_FARAD(x) CAP_N(x)
#define P_FARAD(x) CAP_P(x)
@@ -132,9 +132,9 @@ struct CapacitorDesc : public SeriesRCDesc
NET_C(name.6, name ## _R.1) \
NET_C(name.6, name ## _C.1) \
NET_C(name ## _R.2, V5) \
NET_CSTR(# name "_C.2", "GND") \
NET_C(name ## _C.2, GND) \
NET_C(name.8, V5) \
NET_CSTR(# name ".1", "GND")
NET_C(name.1, GND)

#define CHIP_555_Astable(name, pdesc) \
NE555_DIP(name) \
@@ -147,9 +147,9 @@ struct CapacitorDesc : public SeriesRCDesc
NET_C(name.6, name ## _C.1) \
NET_C(name.2, name ## _C.1) \
NET_C(name ## _R1.2, V5) \
NET_CSTR(# name "_C.2", "GND") \
NET_C(name ## _C.2, GND) \
NET_C(name.8, V5) \
NET_CSTR(# name ".1", "GND")
NET_C(name.1, GND)

#define CHIP_9602_Mono(name, pdesc) \
CHIP(# name, 9602) \
@@ -179,13 +179,13 @@ struct CapacitorDesc : public SeriesRCDesc
#define CHIP_INPUT_ACTIVE_LOW(name) \
SWITCH2(name ## _SW) \
NET_C(name ## _SW.1, V5) \
NET_CSTR(# name "_SW.2", "GND") \
NET_C(name ## _SW.2, GND) \
ALIAS(name.1, name ## _SW.Q)

#define CHIP_INPUT_ACTIVE_HIGH(name) \
SWITCH2(name ## _SW) \
NET_C(name ## _SW.2, V5) \
NET_CSTR(# name "_SW.1", "GND") \
NET_C(name ## _SW.1, GND) \
ALIAS(name.1, name ## _SW.Q)

#define CHIP_LATCH(name) \

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