Add preliminary Sun4/25 support

[friedkiwi]

I've succesfully dumped the boot ROM of my SPARCstation ELC and added preliminary support for it to MAME based on the existing Sun4 work.

This patch manages to get the ELC emulation to get to the Open Firmware prompt, but booting any OS media (eg Solaris/SunOS/NetBSD) results in an illegal instruction error on the OF prompt.

The emulation passes the boot diagnostics:

m_cache_tag_shift 3
m_page_mask 000003ff
m_seg_entry_shift 0000000a
m_seg_entry_mask 0000003f
m_page_entry_mask 0000ffff
m_cache_mask 00003fff

EPROM Checksum Test
Power-Up State Test
Context Register Bit Test
Context Register Addressing Test
Segment Map RAM MATS Pattern Test, Context 00000000
Segment Map RAM MATS Pattern Test, Context 00000001
Segment Map RAM MATS Pattern Test, Context 00000002
Segment Map RAM MATS Pattern Test, Context 00000003
Segment Map RAM MATS Pattern Test, Context 00000004
Segment Map RAM MATS Pattern Test, Context 00000005
Segment Map RAM MATS Pattern Test, Context 00000006
Segment Map RAM MATS Pattern Test, Context 00000007
Page Map RAM MATS Pattern Test
Limit 0 Register Test
Counter Interrupt Level 10 Test
Limit 1 Register Test
Counter Interrupt Level 14 Test
Synchronous Error Reg Test
Synchronous Error Virtual Address Reg Test
Asynchronous Error Reg Test
Asynchronous Error Virtual Address Reg Test
Asynchronous Error Data Reg1 Test
Asynchronous Error Data Reg2 Test
System Enable Register Bit Test
Cache Data RAM MATS Pattern Test
Cache Tag RAM MATS Pattern Test
PTE Access Bit Test
PTE Modify Bit Test
PTE Write-Protect Bit Test
PTE Write-Invalid Bit Test
PTE Read-Invalid Bit Test
PTE Type 2 Space Bit Test
PTE Type 3 Space Bit Test
Synchronous Timeout Test
Asynchronous Timeout Test
**** 16 MegaBytes Found in Address Range 0x00000000 to 0x00ffffff ****
**** 16 MegaBytes Found in Address Range 0x01000000 to 0x01ffffff ****
**** 16 MegaBytes Found in Address Range 0x02000000 to 0x02ffffff ****
**** 16 MegaBytes Found in Address Range 0x03000000 to 0x03ffffff ****
DRAM Word MATS Pattern Test (0x00fe0000 - 0x01000000)
Parity/Memory Control Registers Bit Test
36-bit SIMM Parity Test
33-bit SIMM Parity Test
Interrupt Register Test
Software Interrupt Level 1 Test
Software Interrupt Level 4 Test
Software Interrupt Level 6 Test
NVRAM Access Test
TOD Clock Oscillator Running
TOD Registers Test
Cache Statistics Bit Update Test
Cache Doubleword-Alignment Read Miss Test
Cache TAG Comparator Read Miss Test
Cache Non-Cacheable Read Miss Test
Cache Read Miss Parity Test
Cache Doubleword-Alignment Read Hit Test
Cache Byte-Alignment Read Hit Test
Cache Read Hit Context Test
Cache Read Hit MMU Invalid Test
Cache Doubleword-Alignment Write Hit Test
Cache TAG Comparator Write Hit Test
Cache Write Hit Context Test
Cache Write Hit/Miss (Cacheable) Test
Cache Write Hit/Miss (Non-Cacheable) Test
Cache Write Miss Test
Software Context Flush Test
Software Segment Flush Test
Software Page Flush Test
Hardware Context Flush Test
Hardware Segment Flush Test
Hardware Page Flush Test
Unconditional Block Flush Test
FPU Misaligned Register Pair Test
FPU Single-Precision Test
Single-Precision FPU Exception (Invalid Result) Test
Single-Precision FPU Exception (Overflow) Test
Single-Precision FPU Exception (Underflow) Test
Single-Precision FPU Exception (Divide-by-0) Test
Single-Precision FPU Exception (Inexact Result) Test
Single-Precision FPU Exception and Timeout Test
Single-Precision FPU Exception and Data-Access Trap Test
Single-Precision FPU Exception and Misalignment Test
Single-Precision FPU Exception and Asynchronous Trap Test
FPU Double-Precision Test
Double-Precision FPU Exception (Invalid Result) Test
Double-Precision FPU Exception (Overflow) Test
Double-Precision FPU Exception (Underflow) Test
Double-Precision FPU Exception (Divide-by-0) Test
Double-Precision FPU Exception (Inexact Result) Test
Double-Precision FPU Exception and Timeout Test
Double-Precision FPU Exception and Data-Access Trap Test
Double-Precision FPU Exception and Misalignment Test
Double-Precision FPU Exception and Asynchronous Trap Test
Setting Segment Map
Setting RAM Parity Mode
 Mode set to 36-bit
Sizing Memory
Mapping ROM
Mapping RAM
Can't find keyboard table for keyboard layout code 21
Using USA keyboard table
Probing /sbus@1,f8000000 at 0,0  dma esp sd st le
Probing /sbus@1,f8000000 at 1,0  Nothing there
Probing /sbus@1,f8000000 at 2,0  Nothing there
Probing /sbus@1,f8000000 at 3,0  bwtwo

[Robbbert]

Is the change to infoxml supposed to be there?

[friedkiwi]

Is the change to infoxml supposed to be there?

No it is not - is there a way I can remove it?

[rb6502]

If you push a new CL to your branch that this PR's coming from it should update the PR.

[friedkiwi]

If you push a new CL to your branch that this PR's coming from it should update the PR.

Done.

I've also tested other Sun4 machines that already existed, and they fail at the same stage (the invalid instruction trap in OF is triggered by any OS), so I suspect it's either the SPARC7 or Sun MMU emulation that needs a fix. Once this is merged I'll see if I can figure out what's up.

[cuavas]

If you just fix the indentation on those two lines, we can get this merged. Thanks for adding this.

The Sun machines are having some trouble right now due to work in progress on the sun4c MMU. @MooglyGuy was working on making it pass the tests on systems with more detailed MMU tests in the boot ROMs, but right now I think OS installation is broken on the machines with less strict MMU tests that were previously usable.

[cuavas]

Can you please indent these two lines? We treat ROM definitions as a scope block.

[friedkiwi]

Sorry, my IDE decided it wanted to do the indentation for me. Fixing it now

[friedkiwi]

Indentation fixed now.

[MooglyGuy]

@cuavas is correct, the OS probably won't be installable for the time being, due to the cache emulation being fragile and not entirely understood.

Based on the tests indicated in that output log you posted, it seems that the ELC uses the same sort of brutal cache tests as the SPARCstation 2. Disabling the existing cache emulation in favor of MAME pretending that all accesses are hits would allow SunOS 4.1.x to be installed on the SPARCstation 1 again, but it wouldn't help move either the SPARCstation 2 or, apparently, the ELC forward.

I'm 100% okay with this change, I just want to be clear that it's unlikely for the ELC to immediately come up and be working unless someone with a more keen eye than me can work out exactly what the system is unhappy about w.r.t. the existing cache implementation in the MMU device (and more broadly, how it differs between the SS1 and SS2/ELC/etc., since there are clearly some subtle differences beyond the broader sun4c/sun4m/etc. separation).

[friedkiwi]

@cuavas is correct, the OS probably won't be installable for the time being, due to the cache emulation being fragile and not entirely understood.

Based on the tests indicated in that output log you posted, it seems that the ELC uses the same sort of brutal cache tests as the SPARCstation 2. Disabling the existing cache emulation in favor of MAME pretending that all accesses are hits would allow SunOS 4.1.x to be installed on the SPARCstation 1 again, but it wouldn't help move either the SPARCstation 2 or, apparently, the ELC forward.

I'm 100% okay with this change, I just want to be clear that it's unlikely for the ELC to immediately come up and be working unless someone with a more keen eye than me can work out exactly what the system is unhappy about w.r.t. the existing cache implementation in the MMU device (and more broadly, how it differs between the SS1 and SS2/ELC/etc., since there are clearly some subtle differences beyond the broader sun4c/sun4m/etc. separation).

I have a large pile of hardware and can do comparison tests on real hardware if that helps? This originally started because I noticed I had a model that didn't have a definition or ROM dumped yet, so I did that to try to preserve it for future generations.

[cuavas]

We use one tab indent per scope level – you can see this for all the other ROM definitions in the file. Please follow the format of the surrounding code.

[Tafoid]

@friedkiwi
AFAIK, the data to support this new romset has not been shared. Please send this, ASAP, to: to cover this Pull Request. Thank you!

[Tafoid]

@friedkiwi
You have less than 2 days (as of this message) to forward the rom data to support your PR before the source is frozen for MAME 0.237. Should it not be available when that time comes, your submission very well may be reverted until such time as the data does show up.

[friedkiwi]

@friedkiwi You have less than 2 days (as of this message) to forward the rom data to support your PR before the source is frozen for MAME 0.237. Should it not be available when that time comes, your submission very well may be reverted until such time as the data does show up.

Sorry, I was distracted by my day job. I will send it right now.

[friedkiwi]

Sent, also see https://archive.org/details/sun-sparcstation-elc-bootrom for board shots etc.

[Tafoid]

Thanks very much for your contributions. Good day!