potensiometer position detector ,
Verilog
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README.md

README.md

VR_LOC_DET

Potentiometer(VR) position(Location) detector

FPGA can detect Potentiometer potion via digital IO pin. only use digital 2 output and 1 input pin but not A/D pin use.

Description

FPGA

show block chart chart/VR_LOC_DET.bdf on Quartus

  1. this have 2 deferent random generator(M-Seq) output TPAT_P/N

  2. TPAT_P/N connected on poteinsiometer(VR)'s A-C pin

  3. if potensiometer's position is near by TPAT_P, most match TPAT_P. and if otherside ,most match TPAT_N.

  4. if positon is center, TPAT_P match 50% and TPAT_N match 50% (why pattern is random pattern)

  5. if only match TPAT_P and no match TPAT_N make 'hFF if only match TPAT_N and no match TPAT_P make 'h01 else make center value 'h80

  6. VR location is detected through IIR LowPass filter 5.'s value.

sorry I'dont know detail of this system is active well. this system depend on transient , but I can't understand detail of FPGA Input transient.

multi potentiometer

20170525th support multi potentiometer,

parameter C_CH_N =2 ; for 2 potentiometer using.
VRLOC_DAT_i[1] ;connect 2nd potentiometer B pin
VRLOC_PTRN_[P:N]_o ; connect 1st and 2nd potentiometer A,C pin

and 
VRLOC[15:8]_o ; 2nd potentiometer location,you get.

Features

Demo

show this youtube http://mangakoji.hatenablog.com/entry/2017/04/16/203755

Requirement

writen in VerilogHDL.

#platform: CQ MAX10-FB (Altera MAX10:10M08SAE144C8) but may be can use any FPGA/ASIC

Usage

clone and compile on Altera QuartusII I compiled on v16.1 web

Help: http://mangakoji.hatenablog.com/entry/2017/04/16/203755

Licence:


Copyright © @manga_koji 2017-04-16su Distributed under the [MIT License][mit]. [MIT]: http://www.opensource.org/licenses/mit-license.php

enjoy!