Skip to content


Folders and files

Last commit message
Last commit date

Latest commit



26 Commits

Repository files navigation

PACoGen: Posit Arithmetic Core Generator


A parameterized Verilog HDL posit arithmetic core generator is developed for posit arithmetic (adder, multiplier and division arithmetic). These generators support the posit standard including rounding to nearest rounding method and can be used to generate the Verilog HDL for any combination of Word-Size (N) and Exponent-Size (ES).

This work is based on folowing articles, but primarily on [1]. Please refer them for more detailed description of PACoGen.

  1. Manish Kumar Jaiswal, and Hayden K.-H. So, "PACoGen: A Hardware Posit Arithmetic Core Generator", Accepted for Publication, IEEE Access, May 2019.
  2. Manish Kumar Jaiswal and Hayden K.-H. So, "Architecture Generator for Type-3 Unum Posit Adder/Subtractor", IEEE International Symposium on Circuits and Systems (ISCAS 2018), pp. 1-5, Florence, Italy, May 2018.
  3. Manish Kumar Jaiswal and Hayden K.-H. So, "Universal Number Posit Arithmetic Generator on FPGA", Design Automation and Test (DATE 2018), pp. 1159-1162, Dresden, Germany, Mar 2018.

Please refer/cite these papers if you find this work useful for/in your research.

Posit standards are followed from the developer's paper which can be find at