diff --git a/FeaCore_config b/FeaCore_config index 66ceab4a..c4f62fce 100644 --- a/FeaCore_config +++ b/FeaCore_config @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.35.7 -# Mon Dec 5 00:04:07 2011 +# Tue Dec 6 00:25:03 2011 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -78,8 +78,7 @@ CONFIG_RESOURCE_COUNTERS=y CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y CONFIG_RT_GROUP_SCHED=y -CONFIG_BLK_CGROUP=y -# CONFIG_DEBUG_BLK_CGROUP is not set +# CONFIG_BLK_CGROUP is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set CONFIG_RELAY=y # CONFIG_NAMESPACES is not set @@ -2388,7 +2387,7 @@ CONFIG_JBD2=y # CONFIG_JBD2_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set -CONFIG_JFS_FS=y +CONFIG_JFS_FS=m CONFIG_JFS_POSIX_ACL=y CONFIG_JFS_SECURITY=y # CONFIG_JFS_DEBUG is not set @@ -2494,7 +2493,7 @@ CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set # CONFIG_CEPH_FS is not set -CONFIG_CIFS=y +CONFIG_CIFS=m CONFIG_CIFS_STATS=y CONFIG_CIFS_STATS2=y CONFIG_CIFS_WEAK_PW_HASH=y diff --git a/arch/arm/mach-msm/acpuclock-7x30.c b/arch/arm/mach-msm/acpuclock-7x30.c index c561606d..69095acb 100755 --- a/arch/arm/mach-msm/acpuclock-7x30.c +++ b/arch/arm/mach-msm/acpuclock-7x30.c @@ -1,18 +1,18 @@ /* - * - * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +* +* Copyright (C) 2007 Google, Inc. +* Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved. +* +* This software is licensed under the terms of the GNU General Public +* License version 2, as published by the Free Software Foundation, and +* may be copied, distributed, and modified under those terms. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ #include #include @@ -36,21 +36,21 @@ #include "acpuclock.h" #include "spm.h" -#define SCSS_CLK_CTL_ADDR (MSM_ACC_BASE + 0x04) -#define SCSS_CLK_SEL_ADDR (MSM_ACC_BASE + 0x08) +#define SCSS_CLK_CTL_ADDR (MSM_ACC_BASE + 0x04) +#define SCSS_CLK_SEL_ADDR (MSM_ACC_BASE + 0x08) -#define PLL2_L_VAL_ADDR (MSM_CLK_CTL_BASE + 0x33C) +#define PLL2_L_VAL_ADDR (MSM_CLK_CTL_BASE + 0x33C) #define dprintk(msg...) \ - cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "cpufreq-msm", msg) +cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "cpufreq-msm", msg) -#define VREF_SEL 1 /* 0: 0.625V (50mV step), 1: 0.3125V (25mV step). */ -#define V_STEP (25 * (2 - VREF_SEL)) /* Minimum voltage step size. */ -#define VREG_DATA (VREG_CONFIG | (VREF_SEL << 5)) -#define VREG_CONFIG (BIT(7) | BIT(6)) /* Enable VREG, pull-down if disabled. */ +#define VREF_SEL 1 /* 0: 0.625V (50mV step), 1: 0.3125V (25mV step). */ +#define V_STEP (25 * (2 - VREF_SEL)) /* Minimum voltage step size. */ +#define VREG_DATA (VREG_CONFIG | (VREF_SEL << 5)) +#define VREG_CONFIG (BIT(7) | BIT(6)) /* Enable VREG, pull-down if disabled. */ /* Cause a compile error if the voltage is not a multiple of the step size. */ -#define MV(mv) ((mv) / (!((mv) % V_STEP))) +#define MV(mv) ((mv) / (!((mv) % V_STEP))) /* mv = (750mV + (raw * 25mV)) * (2 - VREF_SEL) */ #define VDD_RAW(mv) (((MV(mv) / V_STEP) - 30) | VREG_DATA) @@ -60,94 +60,94 @@ extern int charging_boot; #define LPM_LOW_CPU_CLK 245760 struct clock_state { - struct clkctl_acpu_speed *current_speed; - struct mutex lock; - uint32_t acpu_switch_time_us; - uint32_t vdd_switch_time_us; - struct clk *ebi1_clk; - unsigned long power_collapse_khz; - unsigned long wait_for_irq_khz; - int wfi_ramp_down; - int pwrc_ramp_down; +struct clkctl_acpu_speed *current_speed; +struct mutex lock; +uint32_t acpu_switch_time_us; +uint32_t vdd_switch_time_us; +struct clk *ebi1_clk; +unsigned long power_collapse_khz; +unsigned long wait_for_irq_khz; +int wfi_ramp_down; +int pwrc_ramp_down; }; struct clkctl_acpu_speed { - unsigned int acpu_clk_khz; - int src; - unsigned int acpu_src_sel; - unsigned int acpu_src_div; - unsigned int axi_clk_hz; - unsigned int vdd_mv; - unsigned int vdd_raw; - unsigned long lpj; /* loops_per_jiffy */ +unsigned int acpu_clk_khz; +int src; +unsigned int acpu_src_sel; +unsigned int acpu_src_div; +unsigned int axi_clk_hz; +unsigned int vdd_mv; +unsigned int vdd_raw; +unsigned long lpj; /* loops_per_jiffy */ }; static struct clock_state drv_state = { 0 }; static struct cpufreq_frequency_table freq_table[] = { - { 0, 122880 }, - { 1, 245760 }, - { 2, 368640 }, - { 3, 768000 }, - /* 806.4MHz is updated to 1024MHz at runtime for MSM8x55. */ - { 4, 806400 }, - { 5, 1017600 }, - { 6, 1113600 }, - { 7, 1209600 }, - { 8, 1305600 }, - { 9, 1401600 }, - { 10, 1497600 }, - { 11, 1516800 }, - { 12, 1612800 }, - { 13, 1708800 }, - { 14, 1804800 }, - { 15, CPUFREQ_TABLE_END }, +{ 0, 122880 }, +{ 1, 245760 }, +{ 2, 368640 }, +{ 3, 768000 }, +/* 806.4MHz is updated to 1024MHz at runtime for MSM8x55. */ +{ 4, 806400 }, +{ 5, 1017600 }, +{ 6, 1113600 }, +{ 7, 1209600 }, +{ 8, 1305600 }, +{ 9, 1401600 }, +{ 10, 1497600 }, +{ 11, 1516800 }, +{ 12, 1612800 }, +{ 13, 1708800 }, +{ 14, 1804800 }, +{ 15, CPUFREQ_TABLE_END }, }; /* Use negative numbers for sources that can't be enabled/disabled */ #define SRC_LPXO (-2) -#define SRC_AXI (-1) +#define SRC_AXI (-1) /* - * Each ACPU frequency has a certain minimum MSMC1 voltage requirement - * that is implicitly met by voting for a specific minimum AXI frequency. - * Do NOT change the AXI frequency unless you are _absoulutely_ sure you - * know all the h/w requirements. - */ +* Each ACPU frequency has a certain minimum MSMC1 voltage requirement +* that is implicitly met by voting for a specific minimum AXI frequency. +* Do NOT change the AXI frequency unless you are _absoulutely_ sure you +* know all the h/w requirements. +*/ static struct clkctl_acpu_speed acpu_freq_tbl[] = { - { 24576, SRC_LPXO, 0, 0, 30720000, 900, VDD_RAW(900) }, - { 61440, PLL_3, 5, 11, 61440000, 900, VDD_RAW(900) }, - { 122880, PLL_3, 5, 5, 61440000, 900, VDD_RAW(900) }, - { 184320, PLL_3, 5, 4, 61440000, 900, VDD_RAW(900) }, - { MAX_AXI_KHZ, SRC_AXI, 1, 0, 61440000, 900, VDD_RAW(900) }, - { 245760, PLL_3, 5, 2, 61440000, 900, VDD_RAW(900) }, - { 368640, PLL_3, 5, 1, 122800000, 900, VDD_RAW(900) }, - /* AXI has MSMC1 implications. See above. */ - { 768000, PLL_1, 2, 0, 153600000, 1000, VDD_RAW(1000) }, - /* - * AXI has MSMC1 implications. See above. - * 806.4MHz is increased to match the SoC's capabilities at runtime - */ - { 806400, PLL_2, 3, 0, 192000000, 1075, VDD_RAW(1075) }, - { 1017600, PLL_2, 3, 0, 192000000, 1125, VDD_RAW(1125) }, - { 1113600, PLL_2, 3, 0, 192000000, 1150, VDD_RAW(1150) }, - { 1209600, PLL_2, 3, 0, 192000000, 1175, VDD_RAW(1175) }, - { 1305600, PLL_2, 3, 0, 192000000, 1200, VDD_RAW(1200) }, - { 1401600, PLL_2, 3, 0, 192000000, 1225, VDD_RAW(1225) }, - { 1497600, PLL_2, 3, 0, 192000000, 1250, VDD_RAW(1250) }, - { 1516800, PLL_2, 3, 0, 192000000, 1275, VDD_RAW(1275) }, - { 1612800, PLL_2, 3, 0, 192000000, 1275, VDD_RAW(1275) }, - { 1708800, PLL_2, 3, 0, 192000000, 1300, VDD_RAW(1300) }, - { 1804800, PLL_2, 3, 0, 192000000, 1325, VDD_RAW(1325) }, - { 0 } +{ 24576, SRC_LPXO, 0, 0, 30720000, 900, VDD_RAW(900) }, +{ 61440, PLL_3, 5, 11, 61440000, 900, VDD_RAW(900) }, +{ 122880, PLL_3, 5, 5, 61440000, 900, VDD_RAW(900) }, +{ 184320, PLL_3, 5, 4, 61440000, 900, VDD_RAW(900) }, +{ MAX_AXI_KHZ, SRC_AXI, 1, 0, 61440000, 900, VDD_RAW(900) }, +{ 245760, PLL_3, 5, 2, 61440000, 900, VDD_RAW(900) }, +{ 368640, PLL_3, 5, 1, 122800000, 900, VDD_RAW(900) }, +/* AXI has MSMC1 implications. See above. */ +{ 768000, PLL_1, 2, 0, 153600000, 1000, VDD_RAW(1000) }, +/* +* AXI has MSMC1 implications. See above. +* 806.4MHz is increased to match the SoC's capabilities at runtime +*/ +{ 806400, PLL_2, 3, 0, 192000000, 1050, VDD_RAW(1050) }, +{ 1017600, PLL_2, 3, 0, 192000000, 1100, VDD_RAW(1100) }, +{ 1113600, PLL_2, 3, 0, 192000000, 1125, VDD_RAW(1125) }, +{ 1209600, PLL_2, 3, 0, 192000000, 1150, VDD_RAW(1150) }, +{ 1305600, PLL_2, 3, 0, 192000000, 1175, VDD_RAW(1175) }, +{ 1401600, PLL_2, 3, 0, 192000000, 1200, VDD_RAW(1200) }, +{ 1497600, PLL_2, 3, 0, 192000000, 1225, VDD_RAW(1225) }, +{ 1516800, PLL_2, 3, 0, 192000000, 1250, VDD_RAW(1250) }, +{ 1612800, PLL_2, 3, 0, 192000000, 1275, VDD_RAW(1275) }, +{ 1708800, PLL_2, 3, 0, 192000000, 1300, VDD_RAW(1300) }, +{ 1804800, PLL_2, 3, 0, 192000000, 1350, VDD_RAW(1350) }, +{ 0 } }; #define POWER_COLLAPSE_KHZ MAX_AXI_KHZ unsigned long acpuclk_power_collapse(void) { - int ret = acpuclk_get_rate(smp_processor_id()); - if (ret > drv_state.power_collapse_khz) - acpuclk_set_rate(smp_processor_id(), drv_state.power_collapse_khz, SETRATE_PC); - return ret; +int ret = acpuclk_get_rate(smp_processor_id()); +if (ret > drv_state.power_collapse_khz) +acpuclk_set_rate(smp_processor_id(), drv_state.power_collapse_khz, SETRATE_PC); +return ret; } unsigned long acpuclk_get_wfi_rate(void) @@ -158,281 +158,281 @@ unsigned long acpuclk_get_wfi_rate(void) #define WAIT_FOR_IRQ_KHZ MAX_AXI_KHZ unsigned long acpuclk_wait_for_irq(void) { - int ret = acpuclk_get_rate(smp_processor_id()); - if (ret > drv_state.wait_for_irq_khz) - acpuclk_set_rate(smp_processor_id(), drv_state.wait_for_irq_khz, SETRATE_SWFI); - return ret; +int ret = acpuclk_get_rate(smp_processor_id()); +if (ret > drv_state.wait_for_irq_khz) +acpuclk_set_rate(smp_processor_id(), drv_state.wait_for_irq_khz, SETRATE_SWFI); +return ret; } static int acpuclk_set_acpu_vdd(struct clkctl_acpu_speed *s) { - int ret = msm_spm_set_vdd(0, s->vdd_raw); - if (ret) - return ret; +int ret = msm_spm_set_vdd(0, s->vdd_raw); +if (ret) +return ret; - /* Wait for voltage to stabilize. */ - udelay(drv_state.vdd_switch_time_us); - return 0; +/* Wait for voltage to stabilize. */ +udelay(drv_state.vdd_switch_time_us); +return 0; } /* Set clock source and divider given a clock speed */ static void acpuclk_set_src(const struct clkctl_acpu_speed *s) { - uint32_t reg_clksel, reg_clkctl, src_sel; - - reg_clksel = readl(SCSS_CLK_SEL_ADDR); - - /* CLK_SEL_SRC1NO */ - src_sel = reg_clksel & 1; - - /* Program clock source and divider. */ - reg_clkctl = readl(SCSS_CLK_CTL_ADDR); - reg_clkctl &= ~(0xFF << (8 * src_sel)); - reg_clkctl |= s->acpu_src_sel << (4 + 8 * src_sel); - reg_clkctl |= s->acpu_src_div << (0 + 8 * src_sel); - writel(reg_clkctl, SCSS_CLK_CTL_ADDR); - - /* Program PLL2 L val for overclocked speeds. */ - if(s->src == PLL_2) { - writel(s->acpu_clk_khz/19200, PLL2_L_VAL_ADDR); - } - - /* Toggle clock source. */ - reg_clksel ^= 1; - - /* Program clock source selection. */ - writel(reg_clksel, SCSS_CLK_SEL_ADDR); +uint32_t reg_clksel, reg_clkctl, src_sel; + +reg_clksel = readl(SCSS_CLK_SEL_ADDR); + +/* CLK_SEL_SRC1NO */ +src_sel = reg_clksel & 1; + +/* Program clock source and divider. */ +reg_clkctl = readl(SCSS_CLK_CTL_ADDR); +reg_clkctl &= ~(0xFF << (8 * src_sel)); +reg_clkctl |= s->acpu_src_sel << (4 + 8 * src_sel); +reg_clkctl |= s->acpu_src_div << (0 + 8 * src_sel); +writel(reg_clkctl, SCSS_CLK_CTL_ADDR); + +/* Program PLL2 L val for overclocked speeds. */ +if(s->src == PLL_2) { +writel(s->acpu_clk_khz/19200, PLL2_L_VAL_ADDR); +} + +/* Toggle clock source. */ +reg_clksel ^= 1; + +/* Program clock source selection. */ +writel(reg_clksel, SCSS_CLK_SEL_ADDR); } int acpuclk_set_rate(int cpu, unsigned long rate, enum setrate_reason reason) { - struct clkctl_acpu_speed *tgt_s, *strt_s; - int res, rc = 0; - - if(charging_boot) - { - rate = LPM_LOW_CPU_CLK; - } - - if (reason == SETRATE_CPUFREQ) - mutex_lock(&drv_state.lock); - - strt_s = drv_state.current_speed; - - if (rate == strt_s->acpu_clk_khz) - goto out; - - for (tgt_s = acpu_freq_tbl; tgt_s->acpu_clk_khz != 0; tgt_s++) { - if (tgt_s->acpu_clk_khz == rate) - break; - } - if (tgt_s->acpu_clk_khz == 0) { - rc = -EINVAL; - goto out; - } - - if (reason == SETRATE_CPUFREQ) { - /* Increase VDD if needed. */ - if (tgt_s->vdd_mv > strt_s->vdd_mv) { - rc = acpuclk_set_acpu_vdd(tgt_s); - if (rc < 0) { - pr_err("ACPU VDD increase to %d mV failed " - "(%d)\n", tgt_s->vdd_mv, rc); - goto out; - } - } - } - - dprintk("Switching from ACPU rate %u KHz -> %u KHz\n", - strt_s->acpu_clk_khz, tgt_s->acpu_clk_khz); - - /* Increase the AXI bus frequency if needed. This must be done before - * increasing the ACPU frequency, since voting for high AXI rates - * implicitly takes care of increasing the MSMC1 voltage, as needed. */ - if (tgt_s->axi_clk_hz > strt_s->axi_clk_hz) { - rc = clk_set_min_rate(drv_state.ebi1_clk, - tgt_s->axi_clk_hz); - if (rc < 0) { - pr_err("Setting AXI min rate failed (%d)\n", rc); - goto out; - } - } - - /* Make sure target PLL is on. */ - if (strt_s->src != tgt_s->src && tgt_s->src >= 0) { - dprintk("Enabling PLL %d\n", tgt_s->src); - local_src_enable(tgt_s->src); - } - - /* Perform the frequency switch */ - acpuclk_set_src(tgt_s); - drv_state.current_speed = tgt_s; - loops_per_jiffy = tgt_s->lpj; - - /* Nothing else to do for SWFI. */ - if (reason == SETRATE_SWFI) - goto out; - - /* Turn off previous PLL if not used. */ - if (strt_s->src != tgt_s->src && strt_s->src >= 0) { - dprintk("Disabling PLL %d\n", strt_s->src); - local_src_disable(strt_s->src); - } - - /* Decrease the AXI bus frequency if we can. */ - if (tgt_s->axi_clk_hz < strt_s->axi_clk_hz) { - res = clk_set_min_rate(drv_state.ebi1_clk, - tgt_s->axi_clk_hz); - if (res < 0) - pr_warning("Setting AXI min rate failed (%d)\n", res); - } - - /* Nothing else to do for power collapse. */ - if (reason == SETRATE_PC) - goto out; - - /* Drop VDD level if we can. */ - if (tgt_s->vdd_mv < strt_s->vdd_mv) { - res = acpuclk_set_acpu_vdd(tgt_s); - if (res) - pr_warning("ACPU VDD decrease to %d mV failed (%d)\n", - tgt_s->vdd_mv, res); - } - - dprintk("ACPU speed change complete\n"); +struct clkctl_acpu_speed *tgt_s, *strt_s; +int res, rc = 0; + +if(charging_boot) +{ +rate = LPM_LOW_CPU_CLK; +} + +if (reason == SETRATE_CPUFREQ) +mutex_lock(&drv_state.lock); + +strt_s = drv_state.current_speed; + +if (rate == strt_s->acpu_clk_khz) +goto out; + +for (tgt_s = acpu_freq_tbl; tgt_s->acpu_clk_khz != 0; tgt_s++) { +if (tgt_s->acpu_clk_khz == rate) +break; +} +if (tgt_s->acpu_clk_khz == 0) { +rc = -EINVAL; +goto out; +} + +if (reason == SETRATE_CPUFREQ) { +/* Increase VDD if needed. */ +if (tgt_s->vdd_mv > strt_s->vdd_mv) { +rc = acpuclk_set_acpu_vdd(tgt_s); +if (rc < 0) { +pr_err("ACPU VDD increase to %d mV failed " +"(%d)\n", tgt_s->vdd_mv, rc); +goto out; +} +} +} + +dprintk("Switching from ACPU rate %u KHz -> %u KHz\n", +strt_s->acpu_clk_khz, tgt_s->acpu_clk_khz); + +/* Increase the AXI bus frequency if needed. This must be done before +* increasing the ACPU frequency, since voting for high AXI rates +* implicitly takes care of increasing the MSMC1 voltage, as needed. */ +if (tgt_s->axi_clk_hz > strt_s->axi_clk_hz) { +rc = clk_set_min_rate(drv_state.ebi1_clk, +tgt_s->axi_clk_hz); +if (rc < 0) { +pr_err("Setting AXI min rate failed (%d)\n", rc); +goto out; +} +} + +/* Make sure target PLL is on. */ +if (strt_s->src != tgt_s->src && tgt_s->src >= 0) { +dprintk("Enabling PLL %d\n", tgt_s->src); +local_src_enable(tgt_s->src); +} + +/* Perform the frequency switch */ +acpuclk_set_src(tgt_s); +drv_state.current_speed = tgt_s; +loops_per_jiffy = tgt_s->lpj; + +/* Nothing else to do for SWFI. */ +if (reason == SETRATE_SWFI) +goto out; + +/* Turn off previous PLL if not used. */ +if (strt_s->src != tgt_s->src && strt_s->src >= 0) { +dprintk("Disabling PLL %d\n", strt_s->src); +local_src_disable(strt_s->src); +} + +/* Decrease the AXI bus frequency if we can. */ +if (tgt_s->axi_clk_hz < strt_s->axi_clk_hz) { +res = clk_set_min_rate(drv_state.ebi1_clk, +tgt_s->axi_clk_hz); +if (res < 0) +pr_warning("Setting AXI min rate failed (%d)\n", res); +} + +/* Nothing else to do for power collapse. */ +if (reason == SETRATE_PC) +goto out; + +/* Drop VDD level if we can. */ +if (tgt_s->vdd_mv < strt_s->vdd_mv) { +res = acpuclk_set_acpu_vdd(tgt_s); +if (res) +pr_warning("ACPU VDD decrease to %d mV failed (%d)\n", +tgt_s->vdd_mv, res); +} + +dprintk("ACPU speed change complete\n"); out: - if (reason == SETRATE_CPUFREQ) - mutex_unlock(&drv_state.lock); +if (reason == SETRATE_CPUFREQ) +mutex_unlock(&drv_state.lock); - return rc; +return rc; } unsigned long acpuclk_get_rate(int cpu) { - WARN_ONCE(drv_state.current_speed == NULL, - "acpuclk_get_rate: not initialized\n"); - if (drv_state.current_speed) - return drv_state.current_speed->acpu_clk_khz; - else - return 0; +WARN_ONCE(drv_state.current_speed == NULL, +"acpuclk_get_rate: not initialized\n"); +if (drv_state.current_speed) +return drv_state.current_speed->acpu_clk_khz; +else +return 0; } uint32_t acpuclk_get_switch_time(void) { - return drv_state.acpu_switch_time_us; +return drv_state.acpu_switch_time_us; } unsigned long clk_get_max_axi_khz(void) { - return MAX_AXI_KHZ; +return MAX_AXI_KHZ; } EXPORT_SYMBOL(clk_get_max_axi_khz); /*---------------------------------------------------------------------------- - * Clock driver initialization - *---------------------------------------------------------------------------*/ +* Clock driver initialization +*---------------------------------------------------------------------------*/ static void __init acpuclk_init(void) { - struct clkctl_acpu_speed *s; - uint32_t div, sel, src_num; - uint32_t reg_clksel, reg_clkctl; - int res; - - drv_state.ebi1_clk = clk_get(NULL, "ebi1_clk"); - BUG_ON(IS_ERR(drv_state.ebi1_clk)); - - reg_clksel = readl(SCSS_CLK_SEL_ADDR); - - /* Determine the ACPU clock rate. */ - switch ((reg_clksel >> 1) & 0x3) { - case 0: /* Running off the output of the raw clock source mux. */ - reg_clkctl = readl(SCSS_CLK_CTL_ADDR); - src_num = reg_clksel & 0x1; - sel = (reg_clkctl >> (12 - (8 * src_num))) & 0x7; - div = (reg_clkctl >> (8 - (8 * src_num))) & 0xF; - - /* Check frequency table for matching sel/div pair. */ - for (s = acpu_freq_tbl; s->acpu_clk_khz != 0; s++) { - if (s->acpu_src_sel == sel && s->acpu_src_div == div) - break; - } - if (s->acpu_clk_khz == 0) { - pr_err("Error - ACPU clock reports invalid speed\n"); - return; - } - break; - case 2: /* Running off of the SCPLL selected through the core mux. */ - /* Switch to run off of the SCPLL selected through the raw - * clock source mux. */ - for (s = acpu_freq_tbl; s->acpu_clk_khz != 0 - && s->src != PLL_2 && s->acpu_src_div == 0; s++) - ; - if (s->acpu_clk_khz != 0) { - /* Program raw clock source mux. */ - acpuclk_set_src(s); - - /* Switch to raw clock source input of the core mux. */ - reg_clksel = readl(SCSS_CLK_SEL_ADDR); - reg_clksel &= ~(0x3 << 1); - writel(reg_clksel, SCSS_CLK_SEL_ADDR); - break; - } - /* else fall through */ - default: - pr_err("Error - ACPU clock reports invalid source\n"); - return; - } - - /* Set initial ACPU VDD. */ - acpuclk_set_acpu_vdd(s); - - drv_state.current_speed = s; - - /* Initialize current PLL's reference count. */ - if (s->src >= 0) - local_src_enable(s->src); - - res = clk_set_min_rate(drv_state.ebi1_clk, s->axi_clk_hz); - if (res < 0) - pr_warning("Setting AXI min rate failed!\n"); - - pr_info("ACPU running at %d KHz\n", s->acpu_clk_khz); - - return; +struct clkctl_acpu_speed *s; +uint32_t div, sel, src_num; +uint32_t reg_clksel, reg_clkctl; +int res; + +drv_state.ebi1_clk = clk_get(NULL, "ebi1_clk"); +BUG_ON(IS_ERR(drv_state.ebi1_clk)); + +reg_clksel = readl(SCSS_CLK_SEL_ADDR); + +/* Determine the ACPU clock rate. */ +switch ((reg_clksel >> 1) & 0x3) { +case 0: /* Running off the output of the raw clock source mux. */ +reg_clkctl = readl(SCSS_CLK_CTL_ADDR); +src_num = reg_clksel & 0x1; +sel = (reg_clkctl >> (12 - (8 * src_num))) & 0x7; +div = (reg_clkctl >> (8 - (8 * src_num))) & 0xF; + +/* Check frequency table for matching sel/div pair. */ +for (s = acpu_freq_tbl; s->acpu_clk_khz != 0; s++) { +if (s->acpu_src_sel == sel && s->acpu_src_div == div) +break; +} +if (s->acpu_clk_khz == 0) { +pr_err("Error - ACPU clock reports invalid speed\n"); +return; +} +break; +case 2: /* Running off of the SCPLL selected through the core mux. */ +/* Switch to run off of the SCPLL selected through the raw +* clock source mux. */ +for (s = acpu_freq_tbl; s->acpu_clk_khz != 0 +&& s->src != PLL_2 && s->acpu_src_div == 0; s++) +; +if (s->acpu_clk_khz != 0) { +/* Program raw clock source mux. */ +acpuclk_set_src(s); + +/* Switch to raw clock source input of the core mux. */ +reg_clksel = readl(SCSS_CLK_SEL_ADDR); +reg_clksel &= ~(0x3 << 1); +writel(reg_clksel, SCSS_CLK_SEL_ADDR); +break; +} +/* else fall through */ +default: +pr_err("Error - ACPU clock reports invalid source\n"); +return; +} + +/* Set initial ACPU VDD. */ +acpuclk_set_acpu_vdd(s); + +drv_state.current_speed = s; + +/* Initialize current PLL's reference count. */ +if (s->src >= 0) +local_src_enable(s->src); + +res = clk_set_min_rate(drv_state.ebi1_clk, s->axi_clk_hz); +if (res < 0) +pr_warning("Setting AXI min rate failed!\n"); + +pr_info("ACPU running at %d KHz\n", s->acpu_clk_khz); + +return; } /* Initalize the lpj field in the acpu_freq_tbl. */ static void __init lpj_init(void) { - int i; - const struct clkctl_acpu_speed *base_clk = drv_state.current_speed; - - for (i = 0; acpu_freq_tbl[i].acpu_clk_khz; i++) { - acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy, - base_clk->acpu_clk_khz, - acpu_freq_tbl[i].acpu_clk_khz); - } +int i; +const struct clkctl_acpu_speed *base_clk = drv_state.current_speed; + +for (i = 0; acpu_freq_tbl[i].acpu_clk_khz; i++) { +acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy, +base_clk->acpu_clk_khz, +acpu_freq_tbl[i].acpu_clk_khz); +} } -#define RPM_BYPASS_MASK (1 << 3) -#define PMIC_MODE_MASK (1 << 4) +#define RPM_BYPASS_MASK (1 << 3) +#define PMIC_MODE_MASK (1 << 4) void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata) { - pr_info("acpu_clock_init()\n"); +pr_info("acpu_clock_init()\n"); - mutex_init(&drv_state.lock); - drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us; - drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us; - //drv_state.power_collapse_khz = clkdata->power_collapse_khz; - drv_state.wfi_ramp_down = 1; - drv_state.pwrc_ramp_down = 1; - acpuclk_init(); - lpj_init(); - +mutex_init(&drv_state.lock); +drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us; +drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us; +//drv_state.power_collapse_khz = clkdata->power_collapse_khz; +drv_state.wfi_ramp_down = 1; +drv_state.pwrc_ramp_down = 1; +acpuclk_init(); +lpj_init(); - cpufreq_frequency_table_get_attr(freq_table, smp_processor_id()); -} +cpufreq_frequency_table_get_attr(freq_table, smp_processor_id()); + +} \ No newline at end of file