Another RISC-V ISA simulator.
This code is suitable to hard refactor at any time
This is another RISC-V ISA simulator, this is coded in SystemC + TLM-2. It supports RV32IMC Instruction set by now (with some bugs).
Brief description of the modules:
- CPU: Top entity that includes all other modules.
- Memory: Memory highly based on TLM-2 example with read file capability
- Registers: Implements the register file, PC register & CSR registers
- Execute: Executes ISA instructions
- Executes C instruction extensions
- Executes M instruction extensions
- Executes A instruction extensions
- Instruction: Decodes instruction and acces to any instruction field
- C_Instruction: Decodes Compressed instructions (C extension)
- M_Instruction: Decodes Multiplication and Division instructions (M extension)
- A_Instruction: Decodes Atomic instructions (A extension)
- Simulator: Top-level entity that builds & starts the simulation
- BusCtrl: Simple bus manager
- Trace: Simple trace peripheral
- Timer: Simple IRQ programable real-time counter peripheral
- Performance: Performance indicators stores here (singleton class)
- Log: Log class to log them all (singleton class)
Current performance is about 284500 instructions / sec in a Intel Core firstname.lastname@example.orgGhz
This is a preliminar and incomplete version.
Task to do:
- Implement all missing instructions (Execute)
- Implement CSRs (where/how?)
- Add full support to read file with memory contents (to memory.h)
- .elf files
- .hex files (only partial .hex support)
- Connect some TLM peripherals
- Debug module similiar to ARM's ITM
- Some standard UART model
- Implement interrupts
- implement timer (mtimecmp) & timer interrupt
- generic IRQ comtroller
- Test, test, test & test. I'm sure there are a
lot ofsome bugs in the code
- riscv-test almost complete (see Test)
- riscv-compliance WiP
- Improve structure and modules hierarchy
- Add 64 & 128 bits architecture (RV64I, RV128I)
In order to compile the project you need SystemC-2.3.2 installed in your system. Just change SYSTEMC path in Makefile.
Then, you need to modifiy your LD_LIBRARY_PATH environtment variable to add path systemc library. In my case:
$ export LD_LIBRARY_PATH=/home/marius/Work/RiscV/code/systemc-2.3.2/lib-linux64
And then you can execute the simulator:
$ ./RISCV_TLM asm/BasicLoop.hex
See Test page for more information.
In the asm directory there are some basic assembly examples.
I "compile" one file with the follwing command:
$ cd asm $ riscv32-unknown-elf-as EternalLoop.asm -o EternalLoop.o $ riscv32-unknown-elf-ld -T ../my_linker_script.ld EternalLoop.o -o EternalLoop.elf $ riscv32-unknown-elf-objcopy -O ihex EternalLoop.elf EternalLoop.hex $ cd .. $ ./RISCV_SCTLM asm/EternalLoop.hex
This example needs that you hit Ctr+C to stop execution.
The C directory contains simple examples in C. Each directory contains an example, to compile it just:
and then execute the .hex file like the example before.
The code is documented using doxygen. In the doc folder there is a Doxygen.cfg file ready to be used.
There are several ways to contribute to this project:
- Pull request are welcome (see TODO list)
- Good documentation
Copyright (C) 2018 Màrius Montón (@mariusmonton)
This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program. If not, see http://www.gnu.org/licenses/.