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Updated files for new Quartus II version

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1 parent 247dfe2 commit ee870b88a0d2c8ff540f47553e7fcbb76e550b7f Zeus Gómez Marmolejo committed Mar 11, 2012
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8 README
@@ -43,10 +43,10 @@ http://zet.aluzina.org
starting from offset 0.
In Linux:
- you will need the Nios II Embedded Design Suite and Quartus II
- installed. Setup the environment variables $NIOS2EDS and $QUARTUSDIR
- pointing to the directories of the Nios II EDS and Quartus II
- repectively. Then run the script boards/altera*/bin/flash_bios.sh
+ You will need Quartus II installed. Run the script:
+ $NIOS2EDS/nios2_command_shell.sh boards/altera-de*/bin/flash_bios.sh
+ where NIOS2EDS points to the NIOS II Embedded Development System
+ directory included with the Quartus II installation.
3) Build the bitfiles
To create the bitfiles, you will need the Quartus II software. The
@@ -1,18 +1,6 @@
#!/bin/bash
-if [ "x$NIOS2EDS" == "x" ]
-then
- echo '$NIOS2EDS environment var must be set with the directory of the NIOS2 EDS'
- exit 1
-fi
-
-if [ "x$QUARTUSDIR" == "x" ]
-then
- echo '$QUARTUSDIR environment var must be set with the dir of QUARTUS II'
- exit 1
-fi
-
-SCRIPTDIR=$(pwd)/$(dirname $0)
+SCRIPTDIR=$(dirname $0)
BIOSDIR=$SCRIPTDIR/../../../src/bios
if [ ! -f "$BIOSDIR/bios.rom" ]
@@ -21,11 +9,7 @@ then
exit 1
fi
-. $NIOS2EDS/nios2_sdk_shell_bashrc
-export PATH=$NIOS2EDS/bin:$PATH
-
-cd $NIOS2EDS/bin
-./bin2flash \
+bin2flash \
--input=$BIOSDIR/bios.rom \
--output=$BIOSDIR/bios.flash \
--location=0x0
@@ -45,9 +29,9 @@ AlteraBegin;
AlteraEnd;
END
-$QUARTUSDIR/bin/quartus_pgm /tmp/flash_bios.cdf
+$QUARTUS_ROOTDIR/bin/quartus_pgm /tmp/flash_bios.cdf
-./nios2-flash-programmer \
+nios2-flash-programmer \
--base=0x02400000 \
$BIOSDIR/bios.flash
@@ -41,7 +41,7 @@
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:09:38 MARCH 18, 2009"
-set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
+set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP2"
set_global_assignment -name VERILOG_FILE ../../../cores/vdu/rtl/vdu_ram_2k_char.v
set_global_assignment -name VERILOG_FILE ../../../cores/vdu/rtl/vdu_ram_2k_attr.v
set_global_assignment -name SDC_FILE kotku.sdc
@@ -318,7 +318,6 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
# Incremental Compilation Assignments
# ===================================
-set_global_assignment -name INCREMENTAL_COMPILATION OFF
# Advanced I/O Timing Assignments
# ===============================
@@ -330,7 +329,7 @@ set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
- set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------
@@ -418,7 +417,6 @@ set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
# Incremental Compilation Assignments
# ===================================
- set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
@@ -427,4 +425,5 @@ set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
# -------------------------
# end ENTITY(kotku)
-# -----------------
+# -----------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
@@ -1,2 +1,6 @@
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "47 " "Warning: * pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems)." { } { } 0 0 "%1!d! pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems)." 1 1 "" 0 -1}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "pll:pll\|altpll:altpll_component\|pll clk\[0\] sdram_clk_~output " "Warning: PLL \"*\" output port * feeds output pin \"*\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 1 1 "" 0 -1}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Warning (20028): Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 1 0 "" 0 -1}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 1 0 "" 0 -1}
+{ "Warning" "WINFER_RAM_SINGLE_PORT_WMIF_POWER_UP" "vdu:vdu\|vdu_ram_2k_attr:ram_2k_attr\|mem " "Warning (276021): Created node \"vdu:vdu\|vdu_ram_2k_attr:ram_2k_attr\|mem\" as a single-port RAM by generating altsyncram megafunction to implement register logic. Power-up values at the outputs of the RAM are different from the original design." { } { { "../../../cores/vdu/rtl/vdu_ram_2k_attr.v" "mem" { Text "/home/zeus/zet/cores/vdu/rtl/vdu_ram_2k_attr.v" 30 -1 0 } } } 0 276021 "Created node \"%1!s!\" as a single-port RAM by generating altsyncram megafunction to implement register logic. Power-up values at the outputs of the RAM are different from the original design." 1 0 "" 0 -1}
+{ "Warning" "WINFER_RAM_SINGLE_PORT_WMIF_POWER_UP" "vdu:vdu\|vdu_ram_2k_char:ram_2k_char\|mem " "Warning (276021): Created node \"vdu:vdu\|vdu_ram_2k_char:ram_2k_char\|mem\" as a single-port RAM by generating altsyncram megafunction to implement register logic. Power-up values at the outputs of the RAM are different from the original design." { } { { "../../../cores/vdu/rtl/vdu_ram_2k_char.v" "mem" { Text "/home/zeus/zet/cores/vdu/rtl/vdu_ram_2k_char.v" 30 -1 0 } } } 0 276021 "Created node \"%1!s!\" as a single-port RAM by generating altsyncram megafunction to implement register logic. Power-up values at the outputs of the RAM are different from the original design." 1 0 "" 0 -1}
@@ -1,18 +1,6 @@
#!/bin/bash
-if [ "x$NIOS2EDS" == "x" ]
-then
- echo '$NIOS2EDS environment var must be set with the directory of the NIOS2 EDS'
- exit 1
-fi
-
-if [ "x$QUARTUSDIR" == "x" ]
-then
- echo '$QUARTUSDIR environment var must be set with the dir of QUARTUS II'
- exit 1
-fi
-
-SCRIPTDIR=$(pwd)/$(dirname $0)
+SCRIPTDIR=$(dirname $0)
BIOSDIR=$SCRIPTDIR/../../../src/bios
if [ ! -f "$BIOSDIR/bios.rom" ]
@@ -21,11 +9,7 @@ then
exit 1
fi
-. $NIOS2EDS/nios2_sdk_shell_bashrc
-export PATH=$NIOS2EDS/bin:$PATH
-
-cd $NIOS2EDS/bin
-./bin2flash \
+bin2flash \
--input=$BIOSDIR/bios.rom \
--output=$BIOSDIR/bios.flash \
--location=0x0
@@ -45,9 +29,9 @@ AlteraBegin;
AlteraEnd;
END
-$QUARTUSDIR/bin/quartus_pgm /tmp/flash_bios.cdf
+$QUARTUS_ROOTDIR/bin/quartus_pgm /tmp/flash_bios.cdf
-./nios2-flash-programmer \
+nios2-flash-programmer \
--base=0x0 \
$BIOSDIR/bios.flash
@@ -41,7 +41,7 @@
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:09:38 MARCH 18, 2009"
-set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
+set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP2"
set_global_assignment -name VERILOG_FILE ../rtl/pll.v
set_global_assignment -name SDC_FILE kotku.sdc
set_global_assignment -name VERILOG_FILE ../../../cores/sram/csr_sram.v
@@ -339,7 +339,6 @@ set_instance_assignment -name RESERVE_PIN "AS OUTPUT DRIVING GROUND" -to sram_ad
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ENABLE_CLOCK_LATENCY ON
-set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
# Analysis & Synthesis Assignments
# ================================
@@ -383,10 +382,6 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-# Incremental Compilation Assignments
-# ===================================
-set_global_assignment -name INCREMENTAL_COMPILATION OFF
-
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "NEAR END"
@@ -397,7 +392,7 @@ set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "NEAR END"
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
- set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------
@@ -731,7 +726,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "NEAR END"
# Incremental Compilation Assignments
# ===================================
- set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
@@ -740,4 +734,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "NEAR END"
# -------------------------
# end ENTITY(kotku)
-# -----------------
+# -----------------
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
@@ -1,18 +1,6 @@
#!/bin/bash
-if [ "x$NIOS2EDS" == "x" ]
-then
- echo '$NIOS2EDS environment var must be set with the directory of the NIOS2 EDS'
- exit 1
-fi
-
-if [ "x$QUARTUSDIR" == "x" ]
-then
- echo '$QUARTUSDIR environment var must be set with the dir of QUARTUS II'
- exit 1
-fi
-
-SCRIPTDIR=$(pwd)/$(dirname $0)
+SCRIPTDIR=$(dirname $0)
BIOSDIR=$SCRIPTDIR/../../../src/bios
if [ ! -f "$BIOSDIR/bios.rom" ]
@@ -21,11 +9,7 @@ then
exit 1
fi
-. $NIOS2EDS/nios2_sdk_shell_bashrc
-export PATH=$NIOS2EDS/bin:$PATH
-
-cd $NIOS2EDS/bin
-./bin2flash \
+bin2flash \
--input=$BIOSDIR/bios.rom \
--output=$BIOSDIR/bios.flash \
--location=0x0
@@ -45,9 +29,9 @@ AlteraBegin;
AlteraEnd;
END
-$QUARTUSDIR/bin/quartus_pgm /tmp/flash_bios.cdf
+$QUARTUS_ROOTDIR/bin/quartus_pgm /tmp/flash_bios.cdf
-./nios2-flash-programmer \
+nios2-flash-programmer \
--base=0x0a800000 \
$BIOSDIR/bios.flash
@@ -41,7 +41,7 @@
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:09:38 MARCH 18, 2009"
-set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
+set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP2"
set_global_assignment -name VERILOG_FILE ../rtl/pll.v
set_global_assignment -name SDC_FILE kotku.sdc
set_global_assignment -name VERILOG_FILE ../../../cores/sram/csr_sram.v
@@ -438,7 +438,6 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Incremental Compilation Assignments
# ===================================
-set_global_assignment -name INCREMENTAL_COMPILATION OFF
# Advanced I/O Timing Assignments
# ===============================
@@ -450,7 +449,7 @@ set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "NEAR END"
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
- set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------
@@ -590,7 +589,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "NEAR END"
# Incremental Compilation Assignments
# ===================================
- set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
@@ -599,4 +597,5 @@ set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "NEAR END"
# -------------------------
# end ENTITY(kotku)
-# -----------------
+# -----------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
@@ -1,2 +1,4 @@
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "58 " "Warning: * pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems)." { } { } 0 0 "%1!d! pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems)." 1 1 "" 0 -1}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "pll:pll\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1 clk\[2\] tft_lcd_clk_~output " "Warning: PLL \"*\" output port * feeds output pin \"*\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 1 1 "" 0 -1}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Warning (20028): Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 1 0 "" 0 -1}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 1 0 "" 0 -1}
@@ -1,18 +1,6 @@
#!/bin/bash
-if [ "x$NIOS2EDS" == "x" ]
-then
- echo '$NIOS2EDS environment var must be set with the directory of the NIOS2 EDS'
- exit 1
-fi
-
-if [ "x$QUARTUSDIR" == "x" ]
-then
- echo '$QUARTUSDIR environment var must be set with the dir of QUARTUS II'
- exit 1
-fi
-
-SCRIPTDIR=$(pwd)/$(dirname $0)
+SCRIPTDIR=$(dirname $0)
BIOSDIR=$SCRIPTDIR/../../../src/bios
if [ ! -f "$BIOSDIR/bios.rom" ]
@@ -21,11 +9,7 @@ then
exit 1
fi
-. $NIOS2EDS/nios2_sdk_shell_bashrc
-export PATH=$NIOS2EDS/bin:$PATH
-
-cd $NIOS2EDS/bin
-./bin2flash \
+bin2flash \
--input=$BIOSDIR/bios.rom \
--output=$BIOSDIR/bios.flash \
--location=0x0
@@ -45,9 +29,9 @@ AlteraBegin;
AlteraEnd;
END
-$QUARTUSDIR/bin/quartus_pgm /tmp/flash_bios.cdf
+$QUARTUS_ROOTDIR/bin/quartus_pgm /tmp/flash_bios.cdf
-./nios2-flash-programmer \
+nios2-flash-programmer \
--base=0x0 \
$BIOSDIR/bios.flash
@@ -41,7 +41,7 @@
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:09:38 MARCH 18, 2009"
-set_global_assignment -name LAST_QUARTUS_VERSION "10.1 SP1"
+set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP2"
set_global_assignment -name VERILOG_FILE ../rtl/pll.v
set_global_assignment -name SDC_FILE kotku.sdc
set_global_assignment -name VERILOG_FILE ../../../cores/sram/csr_sram.v
@@ -343,7 +343,6 @@ set_instance_assignment -name RESERVE_PIN "AS OUTPUT DRIVING VCC" -to tft_lcd_sy
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ENABLE_CLOCK_LATENCY ON
-set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
# Analysis & Synthesis Assignments
# ================================

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