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port audio ASRC implementation from main branch

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marqs85 committed Mar 10, 2019
1 parent 2dbdfe5 commit bb7cdaef6751a3aa9f90283ad59fafc582328e44
Showing with 18,414 additions and 115 deletions.
  1. +1 −3 README.md
  2. +12 −9 cps2_digiav.qsf
  3. +5 −12 cps2_digiav.sdc
  4. BIN output_files/cps2_digiav.jic
  5. BIN output_files/cps2_digiav.pof
  6. BIN output_files/cps2_digiav.sof
  7. +1 −1 pcb/doc/install.md
  8. +17 −4 rtl/cps2_digiav.v
  9. +153 −0 rtl/fir_2ch_audio.bsf
  10. +18 −0 rtl/fir_2ch_audio.cmp
  11. +101 −0 rtl/fir_2ch_audio.qip
  12. +25 −0 rtl/fir_2ch_audio.sip
  13. +31 −0 rtl/fir_2ch_audio.spd
  14. +112 −0 rtl/fir_2ch_audio.v
  15. +915 −0 rtl/fir_2ch_audio/altera_avalon_sc_fifo.v
  16. +88 −0 rtl/fir_2ch_audio/auk_dspip_avalon_streaming_controller_hpfir.vhd
  17. +545 −0 rtl/fir_2ch_audio/auk_dspip_avalon_streaming_sink_hpfir.vhd
  18. +467 −0 rtl/fir_2ch_audio/auk_dspip_avalon_streaming_source_hpfir.vhd
  19. +583 −0 rtl/fir_2ch_audio/auk_dspip_lib_pkg_hpfir.vhd
  20. +370 −0 rtl/fir_2ch_audio/auk_dspip_math_pkg_hpfir.vhd
  21. +187 −0 rtl/fir_2ch_audio/auk_dspip_roundsat_hpfir.vhd
  22. +377 −0 rtl/fir_2ch_audio/dspba_library.vhd
  23. +72 −0 rtl/fir_2ch_audio/dspba_library_package.vhd
  24. +87 −0 rtl/fir_2ch_audio/fir_2ch_audio_0002.vhd
  25. +273 −0 rtl/fir_2ch_audio/fir_2ch_audio_0002_ast.vhd
  26. +593 −0 rtl/fir_2ch_audio/fir_2ch_audio_0002_rtl_core.vhd
  27. +20 −0 rtl/fir_2ch_audio_sim.f
  28. +308 −0 rtl/fir_2ch_audio_sim/aldec/rivierapro_setup.tcl
  29. +915 −0 rtl/fir_2ch_audio_sim/altera_avalon_sc_fifo.v
  30. +88 −0 rtl/fir_2ch_audio_sim/auk_dspip_avalon_streaming_controller_hpfir.vhd
  31. +545 −0 rtl/fir_2ch_audio_sim/auk_dspip_avalon_streaming_sink_hpfir.vhd
  32. +467 −0 rtl/fir_2ch_audio_sim/auk_dspip_avalon_streaming_source_hpfir.vhd
  33. +583 −0 rtl/fir_2ch_audio_sim/auk_dspip_lib_pkg_hpfir.vhd
  34. +370 −0 rtl/fir_2ch_audio_sim/auk_dspip_math_pkg_hpfir.vhd
  35. +187 −0 rtl/fir_2ch_audio_sim/auk_dspip_roundsat_hpfir.vhd
  36. +22 −0 rtl/fir_2ch_audio_sim/cadence/cds.lib
  37. +2 −0 rtl/fir_2ch_audio_sim/cadence/hdl.var
  38. +219 −0 rtl/fir_2ch_audio_sim/cadence/ncsim_setup.sh
  39. +377 −0 rtl/fir_2ch_audio_sim/dspba_library.vhd
  40. +72 −0 rtl/fir_2ch_audio_sim/dspba_library_package.vhd
  41. +87 −0 rtl/fir_2ch_audio_sim/fir_2ch_audio.vhd
  42. +273 −0 rtl/fir_2ch_audio_sim/fir_2ch_audio_ast.vhd
  43. +8 −0 rtl/fir_2ch_audio_sim/fir_2ch_audio_coef_int.txt
  44. +6,176 −0 rtl/fir_2ch_audio_sim/fir_2ch_audio_input.txt
  45. +165 −0 rtl/fir_2ch_audio_sim/fir_2ch_audio_mlab.m
  46. +132 −0 rtl/fir_2ch_audio_sim/fir_2ch_audio_model.m
  47. +176 −0 rtl/fir_2ch_audio_sim/fir_2ch_audio_msim.tcl
  48. +58 −0 rtl/fir_2ch_audio_sim/fir_2ch_audio_nativelink.tcl
  49. +19 −0 rtl/fir_2ch_audio_sim/fir_2ch_audio_param.txt
  50. +593 −0 rtl/fir_2ch_audio_sim/fir_2ch_audio_rtl_core.vhd
  51. +511 −0 rtl/fir_2ch_audio_sim/fir_2ch_audio_tb.vhd
  52. +302 −0 rtl/fir_2ch_audio_sim/mentor/msim_setup.tcl
  53. +17 −0 rtl/fir_2ch_audio_sim/synopsys/vcsmx/synopsys_sim.setup
  54. +221 −0 rtl/fir_2ch_audio_sim/synopsys/vcsmx/vcsmx_setup.sh
  55. +102 −0 rtl/i2s_rx_asrc.v
  56. +81 −0 rtl/i2s_tx_asrc.v
  57. +198 −0 rtl/i2s_upsampler_asrc.v
  58. +8 −7 software/sys_controller/av_controller.c
  59. +74 −74 software/sys_controller/mem_init/sys_onchip_memory2_0.hex
  60. +3 −3 software/sys_controller/si5351/si5351_regs.h
  61. +2 −2 software/sys_controller_bsp/settings.bsp
@@ -3,7 +3,7 @@ CPS2 digital AV interface (Rev 2 - CPS3 branch)

Features (current)
--------------------------
* framelocked 1080p@59.6Hz output with max. 40 scanline latency
* framelocked 1080p@59.60Hz output with max. 40 scanline latency
* 24bit/48kHz audio output
* supports CPS3 standard and widescreen modes

@@ -12,13 +12,11 @@ TODO
* OSD/UI
* resolution select
* more scanline options
* audio ASRC on FPGA
* settings store / profiles

Installation
--------------------------
The add-on board can be installed on top of CPS3 board, preferably close to JAMMA connector. The following additional parts are required:
* SRC4190 IC (until audio ASRC on FPGA is implemented)
* 2pcs 0603 10k SMD resistors and TL2243 switch (or 2 external buttons connecting "vol+" and "vol-" pads to GND when pressed)
* ribbon cable (~15cm, at least 5x4=20 conductors)
* coaxial cable (~50cm total)
@@ -140,22 +140,25 @@ set_global_assignment -name USE_SIGNALTAP_FILE output_files/cps3.stp
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name ENABLE_LOGIC_ANALYZER_INTERFACE OFF







set_global_assignment -name QIP_FILE sys/synthesis/sys.qip
set_global_assignment -name VERILOG_FILE rtl/syncgen.v
set_global_assignment -name VERILOG_FILE rtl/btn_debounce.v
set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qip
set_global_assignment -name SDC_FILE cps2_digiav.sdc
set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qip
set_global_assignment -name QIP_FILE rtl/linebuf.qip
set_global_assignment -name VERILOG_FILE rtl/timescale.v
set_global_assignment -name VERILOG_FILE rtl/scanconverter.v
set_global_assignment -name VERILOG_FILE rtl/i2s_upsampler.v
set_global_assignment -name VERILOG_FILE rtl/i2s_upsampler_asrc.v
set_global_assignment -name VERILOG_FILE rtl/i2s_tx_asrc.v
set_global_assignment -name VERILOG_FILE rtl/i2s_rx_asrc.v
set_global_assignment -name VERILOG_FILE rtl/cps2_digiav.v
set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
set_global_assignment -name QIP_FILE rtl/pll_pclk.qip






set_global_assignment -name QIP_FILE rtl/fir_2ch_audio.qip
set_global_assignment -name SIP_FILE rtl/fir_2ch_audio.sip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
@@ -8,6 +8,8 @@ create_clock -period 24.576MHz -name mclk [get_ports MCLK_SI]
#derive_pll_clocks
#create_generated_clock -source {pll_pclk_inst|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name clk25 {pll_pclk_inst|altpll_component|auto_generated|pll1|clk[0]}
#create_generated_clock -source {pll_pclk_inst|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -duty_cycle 50.00 -name pclk_5x {pll_pclk_inst|altpll_component|auto_generated|pll1|clk[1]}

create_generated_clock -source [get_ports MCLK_SI] -divide_by 8 -multiply_by 1 -duty_cycle 50.00 -name i2s_clkout {i2s_upsampler_asrc:upsampler0|i2s_tx_asrc:i2s_tx|mclk_div_ctr[1]}
derive_clock_uncertainty


@@ -26,32 +28,23 @@ set_input_delay -clock mclk 0 [get_ports {sda HDMI_TX_INT_N BTN*}]
set critoutputs_hdmi {HDMI_TX_RD* HDMI_TX_GD* HDMI_TX_BD* HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}
set i2soutputs_hdmi {HDMI_TX_I2S_DATA HDMI_TX_I2S_WS}
set_output_delay -reference_pin HDMI_TX_PCLK -clock clk_1080p 0 $critoutputs_hdmi
set_output_delay -reference_pin HDMI_TX_I2S_BCK -clock clk5 0 $i2soutputs_hdmi
set_output_delay -reference_pin HDMI_TX_I2S_BCK -clock i2s_clkout 0 $i2soutputs_hdmi
set_false_path -to [remove_from_collection [all_outputs] "$critoutputs_hdmi $i2soutputs_hdmi"]


### CPU/scanconverter clock relations ###

set_clock_groups -exclusive \
-group {clk5} \
-group {clk5 i2s_clkout} \
-group {pclk} \
-group {clk_1080p} \
-group {mclk}

# Filter out impossible output mux combinations
#set clkmuxregs [get_cells {scanconverter:scanconverter_inst|R_out[*] scanconverter:scanconverter_inst|G_out[*] scanconverter:scanconverter_inst|B_out[*] scanconverter:scanconverter_inst|HSYNC_out scanconverter:scanconverter_inst|DATA_enable scanconverter:scanconverter_inst|*_pp1*}]
#set clkmuxnodes [get_pins {scanconverter_inst|linebuf_*|altsyncram_*|auto_generated|ram_*|portbaddr*}]
#set_false_path -from [get_clocks {pclk_vga}] -through $clkmuxregs
set_false_path -from [get_clocks i2s_clkout] -to [get_clocks clk5]

# Ignore paths from registers which are updated only at the end of vsync
#set_false_path -from [get_cells {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_*}]

# Ignore paths from registers which are updated only at leading edge of hsync
#set_false_path -from [get_registers {scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|HSYNC_start*}]

# Ignore paths to registers which do not drive critical logic
#set_false_path -to [get_cells {scanconverter:scanconverter_inst|line_out_idx*}]


### JTAG Signal Constraints ###

BIN +0 Bytes (100%) output_files/cps2_digiav.jic
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BIN +0 Bytes (100%) output_files/cps2_digiav.pof
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BIN +3.51 KB (100%) output_files/cps2_digiav.sof
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@@ -16,7 +16,7 @@ RGB, audio and power are easily available on top side of CPS3. Extract RGB and a
Step 3: Preparation of cps2_digiav board
--------------------------

Solder U11 (SRC4190), SW1 (TL2243) and R7+R8 (2x10k 0603 SMD resistors) on cps2_digiav board.
Bridge SMD jumpers J3, J5 and J6 on top side of the PCB, and solder R7+R8 (2x10k 0603 SMD resistors). If you want to add on-board button module for operation control, solder SW1 (TL2243). For external buttons (2pcs), connect their one end to GND and other end to btn_vol+/- pad.


Step 4: RGB hookup to cps2_digiav board
@@ -77,6 +77,8 @@ wire [5:0] vcnt_sg_lbuf;
wire [2:0] hctr_sg, vctr_sg;
wire HSYNC_sg, VSYNC_sg, DE_sg, mask_enable_sg;

wire I2S_BCK_o, I2S_DATA_o, I2S_WS_o;

wire BTN_volminus_debounced;
wire BTN_volplus_debounced;

@@ -99,7 +101,7 @@ begin
end
end

always @(PCLK_in) begin
always @(posedge PCLK_in) begin
if (reset_n_ctr == 4'hf)
reset_n <= 1'b1;
else
@@ -111,10 +113,10 @@ assign HDMI_TX_DE = DE_out;
assign HDMI_TX_PCLK = PCLK_out;
assign HDMI_TX_HS = HSYNC_out;
assign HDMI_TX_VS = VSYNC_out;
assign HDMI_TX_I2S_DATA = I2S_DATA;
assign HDMI_TX_I2S_BCK = I2S_BCK;
assign HDMI_TX_I2S_DATA = I2S_DATA_o;
assign HDMI_TX_I2S_BCK = I2S_BCK_o;
//CPS3 audio channels are reversed
assign HDMI_TX_I2S_WS = ~I2S_WS;
assign HDMI_TX_I2S_WS = ~I2S_WS_o;
//assign HDMI_TX_I2S_MCLK = 0;
assign HDMI_TX_RD = R_out;
assign HDMI_TX_GD = G_out;
@@ -191,6 +193,17 @@ syncgen u_sg (
.v_ctr (vctr_sg),
);

i2s_upsampler_asrc upsampler0 (
.AMCLK_i (MCLK_SI),
.nARST (reset_n),
.ASCLK_i (I2S_BCK),
.ASDATA_i (I2S_DATA),
.ALRCLK_i (I2S_WS),
.ASCLK_o (I2S_BCK_o),
.ASDATA_o (I2S_DATA_o),
.ALRCLK_o (I2S_WS_o)
);

btn_debounce #(.MIN_PULSE_WIDTH(25000)) deb0 (
.i_clk (PCLK_in),
.i_btn (BTN_volminus),
@@ -0,0 +1,153 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2017 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 448 248)
(text "fir_2ch_audio" (rect 184 -1 238 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 232 20 244)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "clk" (rect 0 0 10 12)(font "Arial" (font_size 8)))
(text "clk" (rect 4 61 22 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 144 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "reset_n" (rect 0 0 30 12)(font "Arial" (font_size 8)))
(text "reset_n" (rect 4 101 46 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 144 112)(line_width 1))
)
(port
(pt 0 152)
(input)
(text "ast_sink_data[15..0]" (rect 0 0 79 12)(font "Arial" (font_size 8)))
(text "ast_sink_data[15..0]" (rect 4 141 124 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 144 152)(line_width 3))
)
(port
(pt 0 168)
(input)
(text "ast_sink_valid" (rect 0 0 56 12)(font "Arial" (font_size 8)))
(text "ast_sink_valid" (rect 4 157 88 168)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 144 168)(line_width 1))
)
(port
(pt 0 184)
(input)
(text "ast_sink_error[1..0]" (rect 0 0 77 12)(font "Arial" (font_size 8)))
(text "ast_sink_error[1..0]" (rect 4 173 124 184)(font "Arial" (font_size 8)))
(line (pt 0 184)(pt 144 184)(line_width 3))
)
(port
(pt 0 200)
(input)
(text "ast_sink_sop" (rect 0 0 53 12)(font "Arial" (font_size 8)))
(text "ast_sink_sop" (rect 4 189 76 200)(font "Arial" (font_size 8)))
(line (pt 0 200)(pt 144 200)(line_width 1))
)
(port
(pt 0 216)
(input)
(text "ast_sink_eop" (rect 0 0 53 12)(font "Arial" (font_size 8)))
(text "ast_sink_eop" (rect 4 205 76 216)(font "Arial" (font_size 8)))
(line (pt 0 216)(pt 144 216)(line_width 1))
)
(port
(pt 448 72)
(output)
(text "ast_source_data[23..0]" (rect 0 0 92 12)(font "Arial" (font_size 8)))
(text "ast_source_data[23..0]" (rect 332 61 464 72)(font "Arial" (font_size 8)))
(line (pt 448 72)(pt 288 72)(line_width 3))
)
(port
(pt 448 88)
(output)
(text "ast_source_valid" (rect 0 0 68 12)(font "Arial" (font_size 8)))
(text "ast_source_valid" (rect 361 77 457 88)(font "Arial" (font_size 8)))
(line (pt 448 88)(pt 288 88)(line_width 1))
)
(port
(pt 448 104)
(output)
(text "ast_source_error[1..0]" (rect 0 0 89 12)(font "Arial" (font_size 8)))
(text "ast_source_error[1..0]" (rect 337 93 469 104)(font "Arial" (font_size 8)))
(line (pt 448 104)(pt 288 104)(line_width 3))
)
(port
(pt 448 120)
(output)
(text "ast_source_sop" (rect 0 0 64 12)(font "Arial" (font_size 8)))
(text "ast_source_sop" (rect 365 109 449 120)(font "Arial" (font_size 8)))
(line (pt 448 120)(pt 288 120)(line_width 1))
)
(port
(pt 448 136)
(output)
(text "ast_source_eop" (rect 0 0 64 12)(font "Arial" (font_size 8)))
(text "ast_source_eop" (rect 365 125 449 136)(font "Arial" (font_size 8)))
(line (pt 448 136)(pt 288 136)(line_width 1))
)
(port
(pt 448 152)
(output)
(text "ast_source_channel" (rect 0 0 80 12)(font "Arial" (font_size 8)))
(text "ast_source_channel" (rect 345 141 453 152)(font "Arial" (font_size 8)))
(line (pt 448 152)(pt 288 152)(line_width 1))
)
(drawing
(text "clk" (rect 129 43 276 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 149 67 316 144)(font "Arial" (color 0 0 0)))
(text "rst" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset_n" (rect 149 107 340 224)(font "Arial" (color 0 0 0)))
(text "avalon_streaming_sink" (rect 10 123 146 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "data" (rect 149 147 322 304)(font "Arial" (color 0 0 0)))
(text "valid" (rect 149 163 328 336)(font "Arial" (color 0 0 0)))
(text "error" (rect 149 179 328 368)(font "Arial" (color 0 0 0)))
(text "startofpacket" (rect 149 195 376 400)(font "Arial" (color 0 0 0)))
(text "endofpacket" (rect 149 211 364 432)(font "Arial" (color 0 0 0)))
(text "avalon_streaming_source" (rect 289 43 716 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "data" (rect 267 67 558 144)(font "Arial" (color 0 0 0)))
(text "valid" (rect 265 83 560 176)(font "Arial" (color 0 0 0)))
(text "error" (rect 263 99 556 208)(font "Arial" (color 0 0 0)))
(text "startofpacket" (rect 228 115 534 240)(font "Arial" (color 0 0 0)))
(text "endofpacket" (rect 233 131 532 272)(font "Arial" (color 0 0 0)))
(text "channel" (rect 253 147 548 304)(font "Arial" (color 0 0 0)))
(text " altera_fir_compiler_ii " (rect 353 232 850 474)(font "Arial" ))
(line (pt 144 32)(pt 288 32)(line_width 1))
(line (pt 288 32)(pt 288 232)(line_width 1))
(line (pt 144 232)(pt 288 232)(line_width 1))
(line (pt 144 32)(pt 144 232)(line_width 1))
(line (pt 145 52)(pt 145 76)(line_width 1))
(line (pt 146 52)(pt 146 76)(line_width 1))
(line (pt 145 92)(pt 145 116)(line_width 1))
(line (pt 146 92)(pt 146 116)(line_width 1))
(line (pt 145 132)(pt 145 220)(line_width 1))
(line (pt 146 132)(pt 146 220)(line_width 1))
(line (pt 287 52)(pt 287 156)(line_width 1))
(line (pt 286 52)(pt 286 156)(line_width 1))
(line (pt 0 0)(pt 448 0)(line_width 1))
(line (pt 448 0)(pt 448 248)(line_width 1))
(line (pt 0 248)(pt 448 248)(line_width 1))
(line (pt 0 0)(pt 0 248)(line_width 1))
)
)
@@ -0,0 +1,18 @@
component fir_2ch_audio is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
ast_sink_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
ast_sink_valid : in std_logic := 'X'; -- valid
ast_sink_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error
ast_sink_sop : in std_logic := 'X'; -- startofpacket
ast_sink_eop : in std_logic := 'X'; -- endofpacket
ast_source_data : out std_logic_vector(23 downto 0); -- data
ast_source_valid : out std_logic; -- valid
ast_source_error : out std_logic_vector(1 downto 0); -- error
ast_source_sop : out std_logic; -- startofpacket
ast_source_eop : out std_logic; -- endofpacket
ast_source_channel : out std_logic_vector(0 downto 0) -- channel
);
end component fir_2ch_audio;

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