Implementation of well known old game LIFE in FPGA Altera MAX10. FPGA Board marsohod3.
Verilog C++
Latest commit 2dba1f2 Apr 28, 2016 @marsohod4you update readme
Permalink
Failed to load latest commit information.
output_files here it works! Apr 28, 2016
some_life here it works! Apr 28, 2016
PLLJ_PLLSPE_INFO.txt here it works! Apr 28, 2016
README.md update readme Apr 28, 2016
altddio_out1.bsf here it works! Apr 28, 2016
altddio_out1.cmp here it works! Apr 28, 2016
altddio_out1.inc here it works! Apr 28, 2016
altddio_out1.ppf here it works! Apr 28, 2016
altddio_out1.qip here it works! Apr 28, 2016
altddio_out1.v here it works! Apr 28, 2016
altddio_out1_bb.v here it works! Apr 28, 2016
altddio_out1_inst.v here it works! Apr 28, 2016
hdmi.v here it works! Apr 28, 2016
hvsync.v here it works! Apr 28, 2016
max10.qpf here it works! Apr 28, 2016
max10_50.qsf here it works! Apr 28, 2016
max10_50.qws here it works! Apr 28, 2016
max10_50.sdc here it works! Apr 28, 2016
max10_50_assignment_defaults.qdf here it works! Apr 28, 2016
max10_8.qsf here it works! Apr 28, 2016
max10_8.qws here it works! Apr 28, 2016
max10_8.sdc here it works! Apr 28, 2016
max10_8_assignment_defaults.qdf here it works! Apr 28, 2016
mypll.bsf here it works! Apr 28, 2016
mypll.ppf here it works! Apr 28, 2016
mypll.qip here it works! Apr 28, 2016
mypll.v here it works! Apr 28, 2016
mypll_bb.v here it works! Apr 28, 2016
mypll_inst.v here it works! Apr 28, 2016
rom_font.qip here it works! Apr 28, 2016
rom_font.v here it works! Apr 28, 2016
rom_font_bb.v here it works! Apr 28, 2016
rom_font_inst.v here it works! Apr 28, 2016
screen_ram.qip here it works! Apr 28, 2016
screen_ram.v here it works! Apr 28, 2016
screen_ram_bb.v here it works! Apr 28, 2016
screen_ram_inst.v here it works! Apr 28, 2016
serial.v here it works! Apr 28, 2016
sloader.v here it works! Apr 28, 2016
top.v here it works! Apr 28, 2016
torus.v here it works! Apr 28, 2016
txtd.v here it works! Apr 28, 2016
vgafont.mif here it works! Apr 28, 2016
xcell.v here it works! Apr 28, 2016

README.md

FPGA_game_life

Verilog HDL Implementation of well known old game LIFE in FPGA Altera MAX10. CAD: Altera Quartus Prime Lite. FPGA Board marsohod3. Now supports 64x32 cells. Initial field seed over serial port: just send TXT file like ./some_life/gosper50.txt to board. Serial settings: 115200, 8bit, 1stop, no parity. Field display over HDMI port 1280x720. Board description: https://marsohod.org/plata-marsokhod3

View video demo at: https://youtu.be/1fjvGrfTt_w