{"payload":{"header_redesign_enabled":false,"results":[{"id":"580967817","archived":false,"color":"#DAE1C2","followers":22,"has_funding_file":false,"hl_name":"martinKindall/risc-v-single-cycle","hl_trunc_description":"A Single Cycle Risc-V 32 bit CPU","language":"SystemVerilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":580967817,"name":"risc-v-single-cycle","owner_id":21063181,"owner_login":"martinKindall","updated_at":"2023-02-11T10:34:39.632Z","has_issues":true}},"sponsorable":false,"topics":["riscv","systemverilog","basys3","rv32i","riscv32","basys3-fpga","riscv-assembly","single-cycle-processor"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":68,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AmartinKindall%252Frisc-v-single-cycle%2B%2Blanguage%253ASystemVerilog","metadata":null,"csrf_tokens":{"/martinKindall/risc-v-single-cycle/star":{"post":"iI4JMMmyIhkcfOPgx0m9xlMUZR97FvkknbeHOqVe6sIYV_cCDJyLdc16X3WfQdinW82nEPo6VWyMMIouh9svRA"},"/martinKindall/risc-v-single-cycle/unstar":{"post":"bwQV59S3qTxb33WUd8zhDraPXdastdCCkiJNbM4H8DZyNGfMreQlj2IGxUdSDS7JjtQwhIBK0oIDDNFSBTV1CQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"kQn8XK_4aimpeqSxMpREDRNToi-4TF12dS8aOeA5AWPN5KrxxbaeDNNjYRhRR0IldUEMXUolit1cIisRD1bbbA"}}},"title":"Repository search results"}