{"payload":{"header_redesign_enabled":false,"results":[{"id":"130754579","archived":false,"color":"#b2b7f8","followers":197,"has_funding_file":false,"hl_name":"masc-ucsc/livehd","hl_trunc_description":"Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation","language":"Verilog","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":130754579,"name":"livehd","owner_id":5561144,"owner_login":"masc-ucsc","updated_at":"2024-05-01T20:39:50.066Z","has_issues":true}},"sponsorable":false,"topics":["asic","fpga","simulation","live","synthesis","hdl","lgraph"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":103,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Amasc-ucsc%252Flivehd%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/masc-ucsc/livehd/star":{"post":"ndZSQXsCeMUd_fZN2mbGRoSAJnFD6YQS3lErLTx07FpG-8aeb5CPSMHWglI9BPlG1j5BInIIbHV-1xJCZSUEeg"},"/masc-ucsc/livehd/unstar":{"post":"Amj0lcAvA6qSm91v_KQz9IPHdnW7IHkFp91JiH64sJWkE0xpV2QsKQ_YPl_NjK17PraG-Fc13TKts5t2QC2-Ow"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"Wtb_c7Xiu7fhi7nDmz3YU-uvkJ8-5AB2XQTpTVdYLSUFgwsPPbs-newlVfqYBuk1jIK0WTlIA3kIKJZ-9BMdCA"}}},"title":"Repository search results"}