💻 A pipelined processor for the LC-3b ISA with advanced features
Switch branches/tags
Nothing to show
Clone or download
Fetching latest commit…
Cannot retrieve the latest commit at this time.
Permalink
Failed to load latest commit information.
bin
src
testcode
.gitignore
LICENSE
README.md

README.md

Pipelined LC-3b Processor

Features

  • 5 stage pipelined processor (IF, ID, EX, MEM, WB)
  • Supports the full LC-3b ISA
  • Physical memory
  • Split L1 cache (instruction cache and data cache)
  • Unified L2 cache with cache arbiter
  • Eviction write buffer
  • Memory-mapped I/O
  • MEM stage instruction leapfrogging
  • Instruction prefetching in hardware

Technical Specifications

  • Theoretical maximum frequency: 115.07 MHz
  • Slack: 0.00 ns