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Initial Code

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1 parent c81b565 commit ee5b1965a59efadc068718ff97ba30c1dc00adae @matthewbridges committed Aug 21, 2012
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  1. +41 −0 .gitignore
  2. +87 −0 Dugong.gise
  3. +415 −0 Dugong.xise
  4. +193 −0 src/inst_mem.vhd
  5. +78 −0 src/program_counter.vhd
  6. +105 −0 tb/inst_mem_tb.vhd
  7. +101 −0 tb/program_counter_tb.vhd
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+#Gitignore for files generated by Xilinx ISE
+
+*.log
+*.svf
+*.scr
+*.cmd
+*.bak
+*.lso
+*.elf
+*.ace
+*~
+*#
+*.swp
+*.ini
+*.html
+*.vhi
+*.wdb
+*.stx
+*.xmsgs
+*.xreport
+*.exe
+*.cmd_log
+*_beh.prj
+*.ncd
+isim
+db
+incremental_db
+work
+*.cr.mti
+vsim.wlf
+transcript
+webtalk.log
+webtalk_impact.xml
+pepExtractor.prj
+impact.xsl
+impact_impact.xwbt
+
+#ignore OS noise
+
+Thumbs.db
+.DS_Store
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+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="Dugong.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
+ <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="inst_mem_tb_beh.prj"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="inst_mem_tb_isim_beh.exe"/>
+ <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="inst_mem_tb_isim_beh.wdb"/>
+ <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="program_counter_tb_isim_beh.exe"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">
+ <transform xil_pn:end_ts="1345557293" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1345557293">
+ <status xil_pn:value="SuccessfullyRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1345557400" xil_pn:in_ck="2871353801013851752" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1345557400">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <outfile xil_pn:name="src/inst_mem.vhd"/>
+ <outfile xil_pn:name="src/program_counter.vhd"/>
+ <outfile xil_pn:name="tb/inst_mem_tb.vhd"/>
+ <outfile xil_pn:name="tb/program_counter_tb.vhd"/>
+ </transform>
+ <transform xil_pn:end_ts="1345557400" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-3587550231636952569" xil_pn:start_ts="1345557400">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1345557400" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-5713101725367321467" xil_pn:start_ts="1345557400">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1345557293" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="6960783419059534124" xil_pn:start_ts="1345557293">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1345557400" xil_pn:in_ck="2871353801013851752" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1345557400">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <outfile xil_pn:name="src/inst_mem.vhd"/>
+ <outfile xil_pn:name="src/program_counter.vhd"/>
+ <outfile xil_pn:name="tb/inst_mem_tb.vhd"/>
+ <outfile xil_pn:name="tb/program_counter_tb.vhd"/>
+ </transform>
+ <transform xil_pn:end_ts="1345557407" xil_pn:in_ck="2871353801013851752" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-9193408158767227058" xil_pn:start_ts="1345557400">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <outfile xil_pn:name="fuse.log"/>
+ <outfile xil_pn:name="inst_mem_tb_beh.prj"/>
+ <outfile xil_pn:name="inst_mem_tb_isim_beh.exe"/>
+ <outfile xil_pn:name="isim"/>
+ <outfile xil_pn:name="isim.log"/>
+ <outfile xil_pn:name="xilinxsim.ini"/>
+ </transform>
+ <transform xil_pn:end_ts="1345557407" xil_pn:in_ck="-94734211775620901" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="8700287104508614107" xil_pn:start_ts="1345557407">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <outfile xil_pn:name="inst_mem_tb_isim_beh.wdb"/>
+ <outfile xil_pn:name="isim.cmd"/>
+ <outfile xil_pn:name="isim.log"/>
+ </transform>
+ </transforms>
+
+</generated_project>
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