ECP5 FPGA dev board
- Make an ECP5 FPGA dev board
- Keep it super simple and cheap
- Configured by on-board FLASH or direct with a Raspberry Pi
- 6 PMODs, 2 buttons, 2 LEDs, FLASH for configuration bitstreams.
There is also an iCE40 version of this board: https://github.com/mattvenn/first-fpga-pcb
What a Lattice ecp5 FPGA needs
Check ECP5 family datasheet for more information.
- A clock input. Has to be provided by an oscillator, it doesn't have a crystal driver. Has to go to a PCLK pad
- 1.1v core supply for the internal logic. Should supply at least 600mA
- 2.5v auxiliary power supply. Should supply 10mA
- 3.3v IO supply for the IO pins. In this design, all banks of IO have the same supply. Same PSU is used for all PMODs, and is rated at 1A.
- Get configured over SPI interface. This can be done directly by a microcontroller or a computer, or the bitstream can be programmed into some FLASH, and the FPGA will read it at boot. If FLASH isn't provided then the bitstream needs to be programmed at every power up or configuration reset. See sysconfig documentation for more info.
- Decoupling capacitors for each IO bank.
- FPGA ecp5 12k (LFE5U-12F-6BG256C) or 45k (LFE5U-45F-6BG256C) part, 14mm bga with 256 pins, 0.8mm pitch
- 2 x TLV62568 DC/DC switchers for core (1.1v) and IO (3.3v).
- 2.5v reg TLV73325PDBVT
- 16MHz oscillator SIT2001BI-S2-33N-16.000000G
- 16MB FLASH W25Q128JVSIM (same as icebreaker)
- core supply (1.1v) is now DC/DC for 1A using TLV62568
- pmod and IO supply is now DC/DC for 1A using TLV62568
- move ferrite beads to input side of psu
- pullups on io2/3 of flash
- pulldown on tclk of jtag
- fix vias under bga by moving to 0.25mm drill 0.45mm annular ring
- add more ground vias under BGA
- Add missing qspi to the Pi to be able to program bitstream faster.
- configuration bits for FPGA should be tied to gnd not through a 10k resistor. The voltage is about 1v, so might be a little close to the threshold of the 3.3v IOBANK supply. Replace with 0Ohm resistors? Or just tie to gnd?
- used IS25LP016D-JBLE as flash, but it has problems with enabling QE for QSPI. Relace with the model used on icebreaker
RPi connection info
See test/mv_ecp.lpf for FPGA pinning. The following are the physical pins on the raspberry pi:
- serial: TX, RX on pins 8 and 10
- I2C: bitbanged on pins 38 and 40. Optional pullup resistors R1 & R2. Need to set up in boot/config.txt
- GPIOs: pins 31, 32, 33, 36.
- SPI: SDO, SDI, CLK, CE0 on pins 19, 21, 23, 24. These are connected to the onboard FLASH for bitstream config.
- Extra SPI CE1: pin 26
- fomu_flash will leave the SPI device in an unusable state. Run
sudo rmmod spi_bcm2835 && sudo modprobe spi_bcm2835to reset it.
- connected I2C pins are just GPIOs. I have found the Pi's I2C hardware unusable, so always use the slower bitbanged version.
To enable add this to /boot/config.txt:
Simple test connects buttons to LEDs and toggles all other pins every second.
Yosys and NextPNR are used to create the bitstream and then it's copied to the Raspberry Pi specified by PI_ADDR in the Makefile.
Fomu-Flash is used to flash the SPI memory. Clone the repo on the Pi and set the path in the Makefile with FOMU_FLASH.
Run make in ./test to build, copy and program the bitstream.
- In particular, the ECP5 and ECP5-5G Hardware Checklist is very useful
- ECP5 library part for Kicad created with https://github.com/xesscorp/KiCad-Schematic-Symbol-Libraries
- Hardware is licensed under the Permissive CERN open hardware license v2
- Software is licensed under the GNU Lesser General Public License v2.1
- Documentation is licensed under the CCO
Open Source Hardware
This board is an OSHWA approved design: ES000012