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Commits on Dec 20, 2018

  1. target/ppc: convert vmin* and vmax* to vector operations 

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  2. target/ppc: convert vadd*s and vsub*s to vector operations 

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  3. target/ppc: Split out VSCR_SAT to a vector field 

    Change the representation of VSCR_SAT such that it is easy
to set from vector code.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  4. target/ppc: Add set_vscr_sat 

    This is required before changing the representation of the register.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  5. target/ppc: Use mtvscr/mfvscr for vmstate 

    This is required before changing the representation of the register.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  6. target/ppc: Add helper_mfvscr 

    This is required before changing the representation of the register.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  7. target/ppc: Remove vscr_nj and vscr_sat 

    These macros are no longer used.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  8. target/ppc: Use helper_mtvscr for reset and gdb 

    Not setting flush_to_zero from gdb_set_avr_reg was a bug.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  9. target/ppc: Pass integer to helper_mtvscr 

    We can re-use this helper elsewhere if we're not passing
in an entire vector register.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  10. target/ppc: convert xxsel to vector operations 

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  11. target/ppc: convert xxspltw to vector operations 

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  12. target/ppc: convert xxspltib to vector operations 

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  13. target/ppc: convert VSX logical operations to vector operations 

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  14. target/ppc: convert vsplt[bhw] to use vector operations 

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  15. target/ppc: convert vspltis[bhw] to use vector operations 

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  16. target/ppc: convert vaddu[b,h,w,d] and vsubu[b,h,w,d] over to use vec… 

    …tor operations

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
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  17. target/ppc: convert VMX logical instructions to use vector operations 

    Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
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  18. target/arm: Use vector minmax expanders for aarch32 

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  19. target/arm: Use vector minmax expanders for aarch64 

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  20. tcg/i386: Implement vector minmax arithmetic 

    The instruction set does not directly provide MO_64.  We can still
implement signed 64-bit with comparison and vpblendvb.  Since the
ISA has no unsigned comparison, it would take 4 insns to implement
unsigned 64-bit, which is probably quicker as integers.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  21. tcg: Add opcodes for vector minmax arithmetic 

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  22. tcg/i386: Implement vector saturating arithmetic 

    Only MO_8 and MO_16 are implemented, since that's all the
instruction set provides.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  23. tcg: Add opcodes for vector saturated arithmetic 

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  24. tcg: Add write_aofs to GVecGen4 

    This allows writing 2 output, 3 input operations.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  25. tcg: Add gvec expanders for nand, nor, eqv 

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  26. target/arm: Rely on optimization within tcg_gen_gvec_or 

    Since we're now handling a == b generically, we no longer need
to do it by hand within target/arm/.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  27. tcg: Add logical simplifications during gvec expand 

    We handle many of these during integer expansion, and the
rest of them during integer optimization.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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  28. target/ppc: replace AVR* macros with Vsr* macros 

    Now that the VMX and VSR register sets have been combined, the same macros can
be used to access both AVR and VSR field members.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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  29. target/ppc: move FP and VMX registers into aligned vsr register array 

    The VSX register array is a block of 64 128-bit registers where the first 32
registers consist of the existing 64-bit FP registers extended to 128-bit
using new VSR registers, and the last 32 registers are the VMX 128-bit
registers as show below:

            64-bit               64-bit
    +--------------------+--------------------+
    |        FP0         |                    |  VSR0
    +--------------------+--------------------+
    |        FP1         |                    |  VSR1
    +--------------------+--------------------+
    |        ...         |        ...         |  ...
    +--------------------+--------------------+
    |        FP30        |                    |  VSR30
    +--------------------+--------------------+
    |        FP31        |                    |  VSR31
    +--------------------+--------------------+
    |                  VMX0                   |  VSR32
    +-----------------------------------------+
    |                  VMX1                   |  VSR33
    +-----------------------------------------+
    |                  ...                    |  ...
    +-----------------------------------------+
    |                  VMX30                  |  VSR62
    +-----------------------------------------+
    |                  VMX31                  |  VSR63
    +-----------------------------------------+

In order to allow for future conversion of VSX instructions to use TCG vector
operations, recreate the same layout using an aligned version of the existing
vsr register array.

Since the old fpr and avr register arrays are removed, the existing callers
must also be updated to use the correct offset in the vsr register array. This
also includes switching the relevant VMState fields over to using subarrays
to make sure that migration is preserved.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
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  30. target/ppc: merge ppc_vsr_t and ppc_avr_t union types 

    Since the VSX registers are actually a superset of the VMX registers then they
can be represented by the same type. Merge ppc_avr_t into ppc_vsr_t and change
ppc_avr_t to be a simple typedef alias.

Note that due to a difference in the naming of the float32 member between
ppc_avr_t and ppc_vsr_t, references to the ppc_avr_t f member must be replaced
with f32 instead.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
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  31. target/ppc: switch FPR, VMX and VSX helpers to access data directly f… 

    …rom cpu_env

Instead of accessing the FPR, VMX and VSX registers through static arrays of
TCGv_i64 globals, remove them and change the helpers to load/store data directly
within cpu_env.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
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  32. target/ppc: introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpe… 

    …rs for VSR register access

These helpers allow us to move VSR register values to/from the specified TCGv_i64
argument.

To prevent VSX helpers accessing the cpu_vsr array directly, add extra TCG
temporaries as required.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
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  33. target/ppc: introduce get_avr64() and set_avr64() helpers for VMX reg… 

    …ister access

These helpers allow us to move AVR register values to/from the specified TCGv_i64
argument.

To prevent VMX helpers accessing the cpu_avr{l,h} arrays directly, add extra TCG
temporaries as required.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
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  34. target/ppc: introduce get_fpr() and set_fpr() helpers for FP register… 

    … access

These helpers allow us to move FP register values to/from the specified TCGv_i64
argument in the VSR helpers to be introduced shortly.

To prevent FP helpers accessing the cpu_fpr array directly, add extra TCG
temporaries as required.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
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  35. target/ppc: switch EXTRACT_HELPER macros over to use sextract32/extra… 

    …ct32

These ensure that we consistently handle signed and unsigned extensions correctly
when decoding immediates from instruction opcodes.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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