diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin9xx_drm_overlay_utils.c b/drivers/gpu/drm/hisilicon/kirin/kirin9xx_drm_overlay_utils.c
index 2b9672a3d057ce..a692db19804812 100644
--- a/drivers/gpu/drm/hisilicon/kirin/kirin9xx_drm_overlay_utils.c
+++ b/drivers/gpu/drm/hisilicon/kirin/kirin9xx_drm_overlay_utils.c
@@ -1341,7 +1341,6 @@ static void hisi_dss_mif_on(struct dss_hw_ctx *ctx)
 void hisi_dss_smmu_on(struct dss_hw_ctx *ctx)
 {
 	void __iomem *smmu_base;
-	struct iommu_domain_data *domain_data = NULL;
 	uint32_t phy_pgd_base = 0;
 	uint64_t fama_phy_pgd_base;
 
@@ -1374,10 +1373,15 @@ void hisi_dss_smmu_on(struct dss_hw_ctx *ctx)
 	set_reg(smmu_base + SMMU_SMRx_NS + 38 * 0x4, 0x1, 32, 0); /*cmd sec stream id*/
 
 	/*TTBR0*/
-	domain_data = (struct iommu_domain_data *)(ctx->mmu_domain->priv);
-	fama_phy_pgd_base = domain_data->phy_pgd_base;
-	phy_pgd_base = (uint32_t)(domain_data->phy_pgd_base);
-	DRM_DEBUG("fama_phy_pgd_base = %llu, phy_pgd_base =0x%x \n", fama_phy_pgd_base, phy_pgd_base);
+	fama_phy_pgd_base = iommu_iova_to_phys(ctx->mmu_domain, 0);
+	phy_pgd_base = (uint32_t)fama_phy_pgd_base;
+
+	if (!phy_pgd_base) {
+		DRM_ERROR("phy_pdg_base is NULL! probably smmu_lpae is missing at DT\n");
+		WARN_ON(1);
+		return;
+	}
+
 	set_reg(smmu_base + SMMU_CB_TTBR0, phy_pgd_base, 32, 0);
 }
 
diff --git a/drivers/iommu/hisi_smmu_lpae.c b/drivers/iommu/hisi_smmu_lpae.c
index d1ab4ad010343f..0eeb4787222c57 100644
--- a/drivers/iommu/hisi_smmu_lpae.c
+++ b/drivers/iommu/hisi_smmu_lpae.c
@@ -476,6 +476,15 @@ static phys_addr_t hisi_smmu_iova_to_phys_lpae(struct iommu_domain *domain,
 	if (!pgdp)
 		return 0;
 
+	/*
+	 * The DRM driver needs to know the physical address of the
+	 * start of the memory-mapped region, in order to set it on some
+	 * registers. Add support for it, by returning the base of the
+	 * memory mapped domain, when iova is zero.
+	 */
+	if (!iova)
+		return virt_to_phys(hisi_smmu_dev->smmu_pgd);
+
 	pgd = *(pgdp + smmu_pgd_index(iova));
 	if (smmu_pgd_none_lpae(pgd))
 		return 0;