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v06/08x

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1 parent f41a31d commit fb4b1082903ceee0312fe48e81f30801f7feb082 MDJ committed Jun 24, 2012
@@ -99,11 +99,9 @@ CONFIG_HIGHMEM=y
CONFIG_VMALLOC_RESERVE=0x25600000
CONFIG_CC_STACKPROTECTOR=y
CONFIG_CP_ACCESS=y
-CONFIG_IOSCHED_VR=y
CONFIG_DEFAULT_SIO=y
CONFIG_DEFAULT_IOSCHED="sio"
CONFIG_ACPU_CUSTOM_FREQ_SUPPORT=y
-CONFIG_ACPU_MAX_FREQ=1890000
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_TABLE=y
CONFIG_CPU_FREQ_STAT=y
@@ -89,21 +89,21 @@ acpuclk_set_rate footprint cpu1 : phy 0x889F1040 : virt 0xFE703040
#define CPU_FOOT_PRINT_BASE_CPU0_VIRT (MSM_KERNEL_FOOTPRINT_BASE + 0x0)
static void set_acpuclk_foot_print(unsigned cpu, unsigned state)
{
- unsigned *status = (unsigned *)(CPU_FOOT_PRINT_BASE_CPU0_VIRT + 0x3C) + cpu;
+ unsigned *status = (unsigned *)(CPU_FOOT_PRINT_BASE_CPU0_VIRT + 0x44) + cpu;
*status = (CPU_FOOT_PRINT_MAGIC | state);
mb();
}
static void set_acpuclk_cpu_freq_foot_print(unsigned cpu, unsigned khz)
{
- unsigned *status = (unsigned *)(CPU_FOOT_PRINT_BASE_CPU0_VIRT + 0x30) + cpu;
+ unsigned *status = (unsigned *)(CPU_FOOT_PRINT_BASE_CPU0_VIRT + 0x44) + cpu;
*status = khz;
mb();
}
static void set_acpuclk_L2_freq_foot_print(unsigned khz)
{
- unsigned *status = (unsigned *)(CPU_FOOT_PRINT_BASE_CPU0_VIRT + 0x3A);
+ unsigned *status = (unsigned *)(CPU_FOOT_PRINT_BASE_CPU0_VIRT + 0x32);
*status = khz;
mb();
}
@@ -147,13 +147,6 @@ static void set_acpuclk_L2_freq_foot_print(unsigned khz)
/* PTE EFUSE register. */
#define QFPROM_PTE_EFUSE_ADDR (MSM_QFPROM_BASE + 0x00C0)
-/* HTC: Custom max frequency. */
-#ifdef CONFIG_ACPU_CUSTOM_FREQ_SUPPORT
-static int acpu_max_freq = CONFIG_ACPU_MAX_FREQ;
-#else
-static int acpu_max_freq = 1890000;
-#endif
-
enum scalables {
CPU0 = 0,
CPU1,
@@ -218,7 +211,7 @@ static struct scalable scalable_8960[] = {
.hfpll_base = MSM_HFPLL_BASE + 0x200,
.aux_clk_sel = MSM_ACC0_BASE + 0x014,
.l2cpmr_iaddr = L2CPUCPMR_IADDR,
- .vreg[VREG_CORE] = { "krait0", 1300000 },
+ .vreg[VREG_CORE] = { "krait0", 1350000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000,
RPM_VREG_VOTER1,
RPM_VREG_ID_PM8921_L24 },
@@ -236,7 +229,7 @@ static struct scalable scalable_8960[] = {
.hfpll_base = MSM_HFPLL_BASE + 0x300,
.aux_clk_sel = MSM_ACC1_BASE + 0x014,
.l2cpmr_iaddr = L2CPUCPMR_IADDR,
- .vreg[VREG_CORE] = { "krait1", 1300000 },
+ .vreg[VREG_CORE] = { "krait1", 1350000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000,
RPM_VREG_VOTER2,
RPM_VREG_ID_PM8921_L24 },
@@ -532,15 +525,15 @@ static struct l2_level l2_freq_tbl_8960_kraitv2[] = {
[8] = { { 756000, HFPLL, 1, 0, 0x1C }, 1150000, 1150000, 4 },
[9] = { { 810000, HFPLL, 1, 0, 0x1E }, 1150000, 1150000, 4 },
[10] = { { 864000, HFPLL, 1, 0, 0x20 }, 1150000, 1150000, 4 },
- [11] = { { 918000, HFPLL, 1, 0, 0x22 }, 1150000, 1150000, 6 },
- [12] = { { 972000, HFPLL, 1, 0, 0x24 }, 1150000, 1150000, 6 },
- [13] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 6 },
- [14] = { { 1080000, HFPLL, 1, 0, 0x28 }, 1150000, 1150000, 6 },
- [15] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 6 },
- [16] = { { 1188000, HFPLL, 1, 0, 0x2C }, 1150000, 1150000, 6 },
- [17] = { { 1242000, HFPLL, 1, 0, 0x2E }, 1150000, 1150000, 6 },
- [18] = { { 1296000, HFPLL, 1, 0, 0x30 }, 1150000, 1150000, 6 },
- [19] = { { 1350000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 6 },
+ [11] = { { 918000, HFPLL, 1, 0, 0x22 }, 1150000, 1150000, 7 },
+ [12] = { { 972000, HFPLL, 1, 0, 0x24 }, 1150000, 1150000, 7 },
+ [13] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 7 },
+ [14] = { { 1080000, HFPLL, 1, 0, 0x28 }, 1150000, 1150000, 7 },
+ [15] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 7 },
+ [16] = { { 1188000, HFPLL, 1, 0, 0x2C }, 1150000, 1150000, 7 },
+ [17] = { { 1242000, HFPLL, 1, 0, 0x2E }, 1150000, 1150000, 7 },
+ [18] = { { 1350000, HFPLL, 1, 0, 0x30 }, 1150000, 1150000, 7 },
+ [19] = { { 1458000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 7 },
};
static struct acpu_level acpu_freq_tbl_8960_kraitv2_slow[] = {
@@ -566,17 +559,19 @@ static struct acpu_level acpu_freq_tbl_8960_kraitv2_slow[] = {
{ 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1225000 },
{ 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1237500 },
{ 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(16), 1237500 },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(16), 1250000 },
- { 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(17), 1275000 },
- { 1, { 1728000, HFPLL, 1, 0, 0x3C }, L2(18), 1300000 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(18), 1250000 },
+ { 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(18), 1275000 },
+ { 1, { 1728000, HFPLL, 1, 0, 0x3C }, L2(19), 1300000 },
{ 1, { 1809000, HFPLL, 1, 0, 0x3E }, L2(19), 1325000 },
{ 1, { 1890000, HFPLL, 1, 0, 0x40 }, L2(19), 1350000 },
+ { 1, { 1998000, HFPLL, 1, 0, 0x42 }, L2(19), 1350000 },
+ { 1, { 2106000, HFPLL, 1, 0, 0x44 }, L2(19), 1350000 },
{ 0, { 0 } }
};
static struct acpu_level acpu_freq_tbl_8960_kraitv2_nom[] = {
{ 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 800000 },
- { 1, { 192000, PLL_8, 0, 2, 0x00 }, L2(1), 850000 },
+ { 1, { 192000, PLL_8, 0, 2, 0x00 }, L2(1), 800000 },
{ 1, { 384000, HFPLL, 2, 0, 0x20 }, L2(7), 850000 },
{ 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 900000 },
{ 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 950000 },
@@ -589,19 +584,21 @@ static struct acpu_level acpu_freq_tbl_8960_kraitv2_nom[] = {
{ 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(7), 1050000 },
{ 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(7), 1075000 },
{ 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(7), 1075000 },
- { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1125000 },
+ { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1100000 },
{ 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(16), 1125000 },
- { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1150000 },
+ { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1125000 },
{ 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1150000 },
- { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1175000 },
+ { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1150000 },
{ 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1175000 },
- { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1187500 },
+ { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1175000 },
{ 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(16), 1187500 },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(16), 1200000 },
- { 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(17), 1225000 },
- { 1, { 1728000, HFPLL, 1, 0, 0x3C }, L2(18), 1250000 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(18), 1200000 },
+ { 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(18), 1225000 },
+ { 1, { 1728000, HFPLL, 1, 0, 0x3C }, L2(19), 1250000 },
{ 1, { 1809000, HFPLL, 1, 0, 0x3E }, L2(19), 1275000 },
{ 1, { 1890000, HFPLL, 1, 0, 0x40 }, L2(19), 1300000 },
+ { 1, { 1998000, HFPLL, 1, 0, 0x42 }, L2(19), 1325000 },
+ { 1, { 2106000, HFPLL, 1, 0, 0x44 }, L2(19), 1350000 },
{ 0, { 0 } }
};
@@ -626,13 +623,15 @@ static struct acpu_level acpu_freq_tbl_8960_kraitv2_fast[] = {
{ 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1100000 },
{ 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1125000 },
{ 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1125000 },
- { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1137500 },
+ { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1125000 },
{ 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(16), 1137500 },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(16), 1150000 },
- { 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(17), 1200000 },
- { 1, { 1728000, HFPLL, 1, 0, 0x3C }, L2(18), 1225000 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(18), 1150000 },
+ { 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(18), 1175000 },
+ { 1, { 1728000, HFPLL, 1, 0, 0x3C }, L2(19), 1200000 },
{ 1, { 1809000, HFPLL, 1, 0, 0x3E }, L2(19), 1250000 },
- { 1, { 1890000, HFPLL, 1, 0, 0x40 }, L2(19), 1300000 },
+ { 1, { 1890000, HFPLL, 1, 0, 0x40 }, L2(19), 1275000 },
+ { 1, { 1998000, HFPLL, 1, 0, 0x42 }, L2(19), 1300000 },
+ { 1, { 2106000, HFPLL, 1, 0, 0x44 }, L2(19), 1325000 },
{ 0, { 0 } }
};
@@ -1545,24 +1544,9 @@ static struct acpu_level * __init select_freq_plan(void)
kraitv2_apply_vmin(acpu_freq_tbl);
}
- /* Adjust frequency table according to custom acpu_max_freq */
- if (acpu_max_freq) {
- for (l = acpu_freq_tbl; l->speed.khz != 0; l++) {
- if (l->speed.khz == acpu_max_freq) {
- /* Custom max freq found in table.
- * Mark all subsequent frequencies
- * as not supported.
- */
- for (++l; l->speed.khz != 0; l++)
- l->use_for_scaling = 0;
- break;
- }
- }
- }
-
/* Find the max supported scaling frequency. */
for (l = acpu_freq_tbl; l->speed.khz != 0; l++)
- if (l->use_for_scaling && l->speed.khz==1890000)
+ if (l->use_for_scaling)
max_acpu_level = l;
BUG_ON(!max_acpu_level);
pr_info("Max ACPU freq: %u KHz\n", max_acpu_level->speed.khz);
@@ -748,7 +748,7 @@ static int msm8960_slim_0_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
SNDRV_PCM_HW_PARAM_CHANNELS);
pr_debug("%s()\n", __func__);
- rate->min = rate->max = 96000;
+ rate->min = rate->max = 48000;
channels->min = channels->max = msm8960_slim_0_rx_ch;
return 0;
@@ -764,7 +764,7 @@ static int msm8960_slim_0_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
SNDRV_PCM_HW_PARAM_CHANNELS);
pr_debug("%s()\n", __func__);
- rate->min = rate->max = 96000;
+ rate->min = rate->max = 48000;
channels->min = channels->max = msm8960_slim_0_tx_ch;
return 0;
@@ -777,7 +777,7 @@ static int msm8960_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
SNDRV_PCM_HW_PARAM_RATE);
pr_debug("%s()\n", __func__);
- rate->min = rate->max = 96000;
+ rate->min = rate->max = 48000;
return 0;
}
@@ -359,11 +359,11 @@ enum {
#endif
-#define MSM_PMEM_ADSP_SIZE 0x6D00000
+#define MSM_PMEM_ADSP_SIZE 0x6000000 /* 96 Mbytes */
#define MSM_PMEM_ADSP2_SIZE 0x700000
#define MSM_PMEM_AUDIO_SIZE 0x2B4000
-#define MSM_PMEM_SIZE 0x4000000 /* 64 Mbytes */
-#define MSM_LIQUID_PMEM_SIZE 0x4000000 /* 64 Mbytes */
+#define MSM_PMEM_SIZE 0x2000000 /* 32 Mbytes */
+#define MSM_LIQUID_PMEM_SIZE 0x1000000 /* 16 Mbytes */
#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
#define MSM_PMEM_KERNEL_EBI1_SIZE 0x280000
@@ -4285,11 +4285,11 @@ static struct msm_spm_platform_data msm_spm_data[] __initdata = {
#ifdef CONFIG_PERFLOCK
static unsigned ville_perf_acpu_table[] = {
- 810000000, /* LOWEST */
- 918000000, /* LOW */
- 1026000000, /* MEDIUM */
- 1242000000,/* HIGH */
- 1512000000, /* HIGHEST */
+ 918000000, /* LOWEST */
+ 1188000000, /* LOW */
+ 1512000000, /* MEDIUM */
+ 1890000000,/* HIGH */
+ 2106000000, /* HIGHEST */
};
static struct perflock_platform_data ville_perflock_data = {
@@ -58,23 +58,12 @@ static int override_cpu;
static int set_cpu_freq(struct cpufreq_policy *policy, unsigned int new_freq)
{
int ret = 0;
-#ifdef CONFIG_PERFLOCK
- int perf_freq = 1890000;
-#endif
+
struct cpufreq_freqs freqs;
freqs.old = policy->cur;
-#ifdef CONFIG_PERFLOCK
- perf_freq = perflock_override(policy, new_freq);
- if (perf_freq) {
- if (policy->cur == perf_freq)
- return 0;
- else
- freqs.new = perf_freq;
- } else if (override_cpu) {
-#else
+
if (override_cpu) {
-#endif
if (policy->cur == policy->max)
return 0;
else
@@ -202,7 +191,7 @@ static int __cpuinit msm_cpufreq_init(struct cpufreq_policy *policy)
#ifdef CONFIG_MSM_CPU_FREQ_SET_MIN_MAX
policy->min = CONFIG_MSM_CPU_FREQ_MIN;
policy->max = CONFIG_MSM_CPU_FREQ_MAX;
-
+#endif
cur_freq = acpuclk_get_rate(policy->cpu);
if (cpufreq_frequency_table_target(policy, table, cur_freq,
@@ -227,13 +216,16 @@ static int __cpuinit msm_cpufreq_init(struct cpufreq_policy *policy)
policy->cur = cur_freq;
- policy->cpuinfo.transition_latency = 30 * 1000;
+ policy->cpuinfo.transition_latency = 10 * 1000;
#ifdef CONFIG_SMP
cpu_work = &per_cpu(cpufreq_work, policy->cpu);
INIT_WORK(&cpu_work->work, set_cpu_work);
init_completion(&cpu_work->complete);
#endif
+ policy->min = 192000;
+ policy->max = 2106000;
+
return 0;
}
View
@@ -45,7 +45,7 @@ config CFQ_GROUP_IOSCHED
config IOSCHED_VR
tristate "V(R) I/O scheduler"
- default n
+ default y
---help---
Requests are chosen according to SSTF with a penalty of rev_penalty
for switching head direction.
@@ -367,7 +367,7 @@ static ssize_t show_##file_name \
}
show_one(cpuinfo_min_freq, cpuinfo.min_freq);
-show_one(cpuinfo_max_freq, cpuinfo.max_freq);
+show_one(cpuinfo_max_freq, max);
show_one(cpuinfo_transition_latency, cpuinfo.transition_latency);
show_one(scaling_min_freq, min);
show_one(scaling_max_freq, max);
@@ -61,7 +61,7 @@ static spinlock_t down_cpumask_lock;
static u64 hispeed_freq;
/* Go to hi speed when CPU load at or above this value. */
-#define DEFAULT_GO_HISPEED_LOAD 85
+#define DEFAULT_GO_HISPEED_LOAD 95
static unsigned long go_hispeed_load;
/*
@@ -73,7 +73,7 @@ static unsigned long min_sample_time;
/*
* The sample rate of the timer used to increase frequency
*/
-#define DEFAULT_TIMER_RATE 30 * USEC_PER_MSEC;
+#define DEFAULT_TIMER_RATE 20 * USEC_PER_MSEC;
static unsigned long timer_rate;
static int cpufreq_governor_interactive(struct cpufreq_policy *policy,
@@ -147,7 +147,7 @@ static void cpufreq_interactive_timer(unsigned long data)
delta_time = (unsigned int) cputime64_sub(pcpu->timer_run_time,
pcpu->freq_change_time);
- if (delta_idle > delta_time)
+ if ((delta_time == 0) || (delta_idle > delta_time))
load_since_change = 0;
else
load_since_change =
@@ -32,14 +32,14 @@
*/
#define DEF_FREQUENCY_DOWN_DIFFERENTIAL (10)
-#define DEF_FREQUENCY_UP_THRESHOLD (85)
+#define DEF_FREQUENCY_UP_THRESHOLD (90)
#define DEF_SAMPLING_DOWN_FACTOR (1)
#define MAX_SAMPLING_DOWN_FACTOR (100000)
#define MICRO_FREQUENCY_DOWN_DIFFERENTIAL (3)
#define MICRO_FREQUENCY_UP_THRESHOLD (90)
#define MICRO_FREQUENCY_MIN_SAMPLE_RATE (10000)
-#define MIN_FREQUENCY_UP_THRESHOLD (11)
-#define MAX_FREQUENCY_UP_THRESHOLD (100)
+#define MIN_FREQUENCY_UP_THRESHOLD (10)
+#define MAX_FREQUENCY_UP_THRESHOLD (98)
#define MIN_FREQUENCY_DOWN_DIFFERENTIAL (1)
#ifdef CONFIG_CPU_FREQ_GOV_ONDEMAND_2_PHASE
@@ -47,7 +47,7 @@ static void sb_close(struct sbuff *m)
if (likely(m != &emergency))
kfree(m);
else {
- xchg(&emergency_ptr, m);
+ (void) xchg(&emergency_ptr, m);
local_bh_enable();
}
}
View
@@ -3,7 +3,7 @@
* them to run sooner, but does not allow tons of sleepers to
* rip the spread apart.
*/
-SCHED_FEAT(GENTLE_FAIR_SLEEPERS, 1)
+SCHED_FEAT(GENTLE_FAIR_SLEEPERS, 0)
/*
* Place new tasks ahead so that they do not starve already running
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