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1 parent db6f069 commit efb7bbadd3c476a202a952d8fdd38d3c628e30aa @mertcetin committed Oct 6, 2012
Showing with 12,320 additions and 0 deletions.
  1. +31 −0 4_col_BRAM.v
  2. +62 −0 BlockRAMvec.v
  3. +61 −0 CurrentBlk.v
  4. +60 −0 MV_Array.v
  5. +157 −0 MV_Selector.v
  6. +1,814 −0 PE_Array.v
  7. +4,747 −0 SW_AddrGen.v
  8. +1,148 −0 Update_Win_22.v
  9. +162 −0 controller.v
  10. +2,884 −0 frames.txt
  11. +47 −0 lfsr.v
  12. +67 −0 median.v
  13. +230 −0 testbench3DRS64.v
  14. +73 −0 toplevel.v
  15. +79 −0 update.v
  16. +335 −0 wavepr.do
  17. +363 −0 waveyeni.do
View
@@ -0,0 +1,31 @@
+module SW_Reg_4col(clk,WE,AddrIn,DataIn,AddrOut,DataOut);
+input clk;
+input [10:0] AddrOut;
+input [8:0] AddrIn;
+input [31:0] DataIn;
+input WE;
+
+output [7:0] DataOut;
+
+reg [8:0] dump;
+
+reg [7:0] reg_file[0:351];
+
+assign DataOut = reg_file[dump];
+
+always @(posedge clk)
+begin
+ dump <= AddrOut;
+ if (WE)
+ begin
+ reg_file[AddrIn*4+3] <= DataIn[31:24];
+ reg_file[AddrIn*4+2] <= DataIn[23:16];
+ reg_file[AddrIn*4+1] <= DataIn[15:8];
+ reg_file[AddrIn*4] <= DataIn[7:0];
+ end
+end
+
+
+
+
+endmodule
View
@@ -0,0 +1,62 @@
+module BlockRAM_Vec(clk,WE,Addr,AddrOut,MVreadOut,VecIn,VecOut);
+input clk;
+input [13:0] Addr,AddrOut;
+input [13:0] VecIn;
+input WE;
+
+output [13:0] VecOut,MVreadOut;
+
+reg [13:0] dump,dump2;
+
+reg [13:0] VecMem[0:8039];
+
+assign VecOut = VecMem[dump];
+assign MVreadOut = VecMem[dump2];
+
+integer file;
+
+initial
+begin
+ file = $fopen("MVectors.txt");
+end
+
+always @(posedge clk)
+begin
+ dump <= Addr;
+ dump2 <= AddrOut;
+ if (WE)
+ begin
+ VecMem[Addr] <= VecIn;
+ if(VecIn[13:7] > 36)
+ begin
+ if (VecIn[6:0] > 36)
+ begin
+ $fdisplay (file, "( -%d, -%d)",~VecIn[6:0]+1'b1,~VecIn[13:7]+1'b1);
+ $display ("( -%d, -%d)",~VecIn[6:0]+1'b1,~VecIn[13:7]+1'b1);
+ end
+ else
+ begin
+ $fdisplay (file, "( %d, -%d)",VecIn[6:0],~VecIn[13:7]+1'b1);
+ $display ("( %d, -%d)",VecIn[6:0],~VecIn[13:7]+1'b1);
+ end
+ end
+ else
+ begin
+ if(VecIn[6:0] > 36)
+ begin
+ $fdisplay (file, "( -%d, %d)",~VecIn[6:0]+1'b1,VecIn[13:7]);
+ $display ("( -%d, %d)",~VecIn[6:0]+1'b1,VecIn[13:7]);
+ end
+ else
+ begin
+ $fdisplay (file, "( %d, %d)",VecIn[6:0],VecIn[13:7]);
+ $display ("( %d, %d)",VecIn[6:0],VecIn[13:7]);
+ end
+ end
+ end
+end
+
+
+
+
+endmodule
View
@@ -0,0 +1,61 @@
+module RegFileCur(clk,reset,WE,DataIN,DataOUT);
+ input clk,reset,WE;
+ input [63:0] DataIN;
+ output [(16*16*8)-1:0] DataOUT;
+ reg [(16*16*8)-1:0] CurrentBlock;
+ reg [4:0] write_count;
+
+ always @(posedge clk, posedge reset)
+ begin
+ if (reset)
+ begin
+ CurrentBlock <= 2048'b0;
+ write_count <= 0;
+ end
+ else if (WE)
+ begin
+ write_count <= write_count + 1;
+ case (write_count)
+ 0: CurrentBlock[(32*8*8)-1:(31*8*8)] <= DataIN;
+ 1: CurrentBlock[(31*8*8)-1:(30*8*8)] <= DataIN;
+ 2: CurrentBlock[(30*8*8)-1:(29*8*8)] <= DataIN;
+ 3: CurrentBlock[(29*8*8)-1:(28*8*8)] <= DataIN;
+ 4: CurrentBlock[(28*8*8)-1:(27*8*8)] <= DataIN;
+ 5: CurrentBlock[(27*8*8)-1:(26*8*8)] <= DataIN;
+ 6: CurrentBlock[(26*8*8)-1:(25*8*8)] <= DataIN;
+ 7: CurrentBlock[(25*8*8)-1:(24*8*8)] <= DataIN;
+ 8: CurrentBlock[(24*8*8)-1:(23*8*8)] <= DataIN;
+ 9: CurrentBlock[(23*8*8)-1:(22*8*8)] <= DataIN;
+ 10: CurrentBlock[(22*8*8)-1:(21*8*8)] <= DataIN;
+ 11: CurrentBlock[(21*8*8)-1:(20*8*8)] <= DataIN;
+ 12: CurrentBlock[(20*8*8)-1:(19*8*8)] <= DataIN;
+ 13: CurrentBlock[(19*8*8)-1:(18*8*8)] <= DataIN;
+ 14: CurrentBlock[(18*8*8)-1:(17*8*8)] <= DataIN;
+ 15: CurrentBlock[(17*8*8)-1:(16*8*8)] <= DataIN;
+ 16: CurrentBlock[(16*8*8)-1:(15*8*8)] <= DataIN;
+ 17: CurrentBlock[(15*8*8)-1:(14*8*8)] <= DataIN;
+ 18: CurrentBlock[(14*8*8)-1:(13*8*8)] <= DataIN;
+ 19: CurrentBlock[(13*8*8)-1:(12*8*8)] <= DataIN;
+ 20: CurrentBlock[(12*8*8)-1:(11*8*8)] <= DataIN;
+ 21: CurrentBlock[(11*8*8)-1:(10*8*8)] <= DataIN;
+ 22: CurrentBlock[(10*8*8)-1:(9*8*8)] <= DataIN;
+ 23: CurrentBlock[(9*8*8)-1:(8*8*8)] <= DataIN;
+ 24: CurrentBlock[(8*8*8)-1:(7*8*8)] <= DataIN;
+ 25: CurrentBlock[(7*8*8)-1:(6*8*8)] <= DataIN;
+ 26: CurrentBlock[(6*8*8)-1:(5*8*8)] <= DataIN;
+ 27: CurrentBlock[(5*8*8)-1:(4*8*8)] <= DataIN;
+ 28: CurrentBlock[(4*8*8)-1:(3*8*8)] <= DataIN;
+ 29: CurrentBlock[(3*8*8)-1:(2*8*8)] <= DataIN;
+ 30: CurrentBlock[(2*8*8)-1:(1*8*8)] <= DataIN;
+ 31: CurrentBlock[(1*8*8)-1:(0*8*8)] <= DataIN;
+ //default: CurrentBlock <= CurrentBlock;
+ endcase
+ end
+ else
+ write_count <= 0;
+ end
+
+
+ assign DataOUT = CurrentBlock;
+
+endmodule
View
@@ -0,0 +1,60 @@
+module MV_Array(clk,reset,WE,feed,curpos,MVector,vecout,AddrOut,topMVout);
+input clk,reset,WE,feed;
+input [13:0] MVector;
+input [13:0] curpos;
+input wire [13:0] AddrOut;
+output wire [13:0] vecout,topMVout;
+reg [1:0] count;
+reg [13:0] Addr;
+wire [13:0] vecout1addr,vecout2addr,vecout3addr;
+wire [6:0] bposx,bposy;
+// max 120x67 total blocks of 16x16 px size
+//reg [13:0] VecMem[0:8039];
+wire [6:0] vec1x,vec2y, vec3y, vec3x;
+parameter blockcountROW = 80;
+parameter blockcountCOL = 45;
+
+assign bposy = curpos[13:7];
+assign bposx = curpos[6:0];
+
+assign vecout1addr = {bposy,vec1x};
+assign vecout2addr = {vec2y,bposx};
+assign vecout3addr = {vec3y,vec3x};
+
+
+assign vec1x = (bposx == 0) ? bposx : bposx-1;
+assign vec2y = (bposy == 0) ? bposy : bposy-1;
+assign vec3y = (bposy == blockcountCOL-1) ? bposy : bposy+1 ;
+assign vec3x = (bposx >= blockcountROW-2) ? blockcountROW-1 : bposx+2;
+always @ (posedge clk, posedge reset)
+begin
+ if(reset)
+ begin
+ count <= 0;
+ end
+ else if (feed)
+ count <= count + 1;
+ else
+ count <= 0;
+end
+
+always @*
+begin
+ if (feed)
+ begin
+ case(count)
+ 0: Addr = vecout1addr;
+ 1: Addr = vecout2addr;
+ 2: Addr = vecout3addr;
+ default: Addr = 0;
+ endcase
+ end
+ else
+ Addr = curpos;
+end
+
+BlockRAM_Vec vecmem(clk,WE,Addr,AddrOut,topMVout,MVector,vecout);
+
+endmodule
+
+
View
@@ -0,0 +1,157 @@
+module MV_Selector(clk,reset,WE,SADin,MVin,MVSelected,done_out,MVwait);
+input clk,reset,WE,MVwait;
+input [15:0] SADin;
+input [13:0] MVin;
+reg [15:0] SADSelected;
+output reg [13:0] MVSelected;
+
+reg [15:0] SADmin;
+reg [13:0] MVmin;
+
+reg [15:0] SADs0, SADs1, SADs2;
+reg [13:0] MVs0, MVs1, MVs2;
+reg [1:0] count;
+
+reg WE_delay1, WE_delay2, WE_delay3,MVwait_delay1,MVwait_delay2;
+reg [13:0] MV_delay1, MV_delay2, MV_delay3;
+reg done;
+output reg done_out;
+
+integer i;
+
+always @(posedge clk, posedge reset)
+begin
+ if (reset)
+ begin
+ WE_delay1 <= 0;
+ WE_delay2 <= 0;
+ WE_delay3 <= 0;
+ MV_delay1 <= 0;
+ MV_delay2 <= 0;
+ MV_delay3 <= 0;
+ MVwait_delay1 <= 0;
+ MVwait_delay2 <= 0;
+ end
+ else
+ begin
+ WE_delay1 <= WE;
+ WE_delay2 <= WE_delay1;
+ WE_delay3 <= WE_delay2;
+ MVwait_delay1 <= MVwait;
+ MVwait_delay2 <= MVwait_delay1;
+ MV_delay1 <= MVin;
+ MV_delay2 <= MV_delay1;
+ MV_delay3 <= MV_delay2;
+ end
+end
+
+
+always @(posedge clk, posedge reset)
+begin
+ if (reset)
+ begin
+ SADs0 <= 16'hFFFF;
+ MVs0 <= 14'b0;
+ SADs1 <= 16'hFFFF;
+ MVs1 <= 14'b0;
+ SADs2 <= 16'hFFFF;
+ MVs2 <= 14'b0;
+ done <= 1'b0;
+ end
+ else if (WE_delay3)
+ begin
+ case (count)
+ 0:
+ begin
+ SADs0 <= SADin;
+ MVs0 <= MV_delay2;
+ end
+ 1:
+ begin
+ SADs1 <= SADin;
+ MVs1 <= MV_delay2;
+ if (MVwait_delay2)
+ SADs2 <= 16'hFFFF;
+ end
+ 2:
+ begin
+ SADs2 <= SADin;
+ MVs2 <= MV_delay2;
+ end
+ endcase
+ //SADs[count] <= SADin;
+ //MVs[count] <= MV_delay2;
+ //if (WE_delay2)
+ //count <= count + 1;
+ //else
+ //begin
+ if (MVwait_delay2)
+ begin
+ done <= 1'b1;
+ end
+ //end
+ end
+ else
+ done <= 1'b0;
+end
+
+always @(posedge clk, posedge reset)
+begin
+ if(reset)
+ count <= 3;
+ else if (WE_delay2)
+ begin
+ count <= count + 1;
+ end
+ else if (WE_delay3 && MVwait)
+ begin
+ count <= 3;
+ end
+end
+
+always @(posedge clk, posedge reset)
+begin
+ if (reset)
+ begin
+ SADSelected <= 0;
+ MVSelected <= 0;
+ done_out <= 0;
+ end
+ //else if (count == 2)
+ else if (done)
+ begin
+ SADSelected <= SADmin;
+ MVSelected <= MVmin;
+ done_out <= 1;
+ end
+ else
+ done_out <= 0;
+end
+
+always @(*)
+begin
+ if (SADs0 <= SADs1)
+ if (SADs0 <= SADs2)
+ begin
+ SADmin = SADs0;
+ MVmin = MVs0;
+ end
+ else
+ begin
+ SADmin = SADs2;
+ MVmin = MVs2;
+ end
+ else
+ if (SADs1<=SADs2)
+ begin
+ SADmin = SADs1;
+ MVmin = MVs1;
+ end
+ else
+ begin
+ SADmin = SADs2;
+ MVmin = MVs2;
+ end
+end
+
+endmodule
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