IWRAM Open Bus LSW/MSW wrong way around? #1575
Based on the description on GBATEK, it appears to me, that the MSW and LSW for IWRAM actually should be the other way around.
It is also interesting to note, that with Thumb code in IWRAM it is possible that data reads/writes influence observed open bus values, as each instruction prefetch only trashes a HWORD of the latch. The test ROM demonstrates this. Although I'd guess (or hope?) that no game actually relies on this :p
The test ROM (the code is also in the repo, but currently very messy):
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