IWRAM Open Bus LSW/MSW wrong way around?

[fleroviux]

https://github.com/mgba-emu/mgba/blob/master/src/gba/memory.c#L355

Based on the description on GBATEK, it appears to me, that the MSW and LSW for IWRAM actually should be the other way around.
Out of general curiosity I wrote a small (currently very immature) test ROM last night, and its result in mGBA 0.8 seems to match my observation.

(left value is actual result, right value is what it expects, according to real HW)

It is also interesting to note, that with Thumb code in IWRAM it is possible that data reads/writes influence observed open bus values, as each instruction prefetch only trashes a HWORD of the latch. The test ROM demonstrates this. Although I'd guess (or hope?) that no game actually relies on this :p

The test ROM (the code is also in the repo, but currently very messy):
https://github.com/fleroviux/openbuster/releases/download/0.1/openbuster.gba