Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[ARM Disassembler] Flawed display of ALU instructions with a register shift #2349

Closed
lunasorcery opened this issue Nov 9, 2021 · 0 comments
Closed

Comments

@lunasorcery
Copy link

@lunasorcery lunasorcery commented Nov 9, 2021

Observed at 0.9.2 (f6d5f51)

For ALU operations (and, bic, etc), the disassembler erroneously omits the lsl when the second operand is left-shifted by r0.

Given the following assembly:

and r3, r3, r2, lsl #0  ; opcode E0033002
and r3, r3, r2, lsl #1  ; opcode E0033082
and r3, r3, r2, lsl r0  ; opcode E0033012
and r3, r3, r2, lsl r1  ; opcode E0033112

mGBA will disassemble as:

and r3, r3, r2          ; zero-shift omitted, as expected
and r3, r3, r2, lsl #1
and r3, r3, r2, r0      ; `lsl` suspiciously missing
and r3, r3, r2, lsl r1
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Linked pull requests

Successfully merging a pull request may close this issue.

None yet
1 participant